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Revision tags: llvmorg-20.1.0, llvmorg-20.1.0-rc3, llvmorg-20.1.0-rc2, llvmorg-20.1.0-rc1, llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7, llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init |
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fc18a882 |
| 08-Jul-2022 |
Nikita Popov <[email protected]> |
[InstCombine] Avoid creating float binop ConstantExprs
Replace ConstantExpr:getFAdd etc with call to ConstantFoldBinaryOpOperands(). I'm using the constant folding API rather than IRBuilder here to
[InstCombine] Avoid creating float binop ConstantExprs
Replace ConstantExpr:getFAdd etc with call to ConstantFoldBinaryOpOperands(). I'm using the constant folding API rather than IRBuilder here to ensure that this does actually constant fold. These transforms don't use m_ImmConstant(), so this would not otherwise be guaranteed (and apparently, they can't use m_ImmConstant because they want to handle scalable vector splats).
There is an opportunity here to further migrate these to the ConstantFoldFPInstOperands() API, which would respect the denormal mode. I've held off on doing so here, because some of this code explicitly checks for denormal results, and I don't want to touch it in a mostly NFC change.
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Revision tags: llvmorg-14.0.6, llvmorg-14.0.5 |
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b8c2781f |
| 09-Jun-2022 |
Simon Moll <[email protected]> |
[NFC] format InstructionSimplify & lowerCaseFunctionNames
Clang-format InstructionSimplify and convert all "FunctionName"s to "functionName". This patch does touch a lot of files but gets done with
[NFC] format InstructionSimplify & lowerCaseFunctionNames
Clang-format InstructionSimplify and convert all "FunctionName"s to "functionName". This patch does touch a lot of files but gets done with the cleanup of InstructionSimplify in one commit.
This is the alternative to the less invasive clang-format only patch: D126783
Reviewed By: spatel, rengolin
Differential Revision: https://reviews.llvm.org/D126889
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3f33d67d |
| 05-Jun-2022 |
Sanjay Patel <[email protected]> |
[InstCombine] fold mul with masked low bit operand to trunc+select
https://alive2.llvm.org/ce/z/o7rQ5q
This shows an extra instruction in some cases, but that is caused by an existing canonicalizat
[InstCombine] fold mul with masked low bit operand to trunc+select
https://alive2.llvm.org/ce/z/o7rQ5q
This shows an extra instruction in some cases, but that is caused by an existing canonicalization of trunc -> and+icmp.
Codegen should be better for any target where a multiply is more costly than the most simple ALU op.
This ends up producing the requested x86 asm from issue #55618, but it's not the same IR. We are missing a canonicalization from the negate+mask pattern to the trunc+select created here.
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8689463b |
| 02-Jun-2022 |
Sanjay Patel <[email protected]> |
[InstCombine] make pattern matching more consistent; NFC
We could go either way on this and several similar matches. Just matching as a binop is possibly slightly more efficient; we don't need to re
[InstCombine] make pattern matching more consistent; NFC
We could go either way on this and several similar matches. Just matching as a binop is possibly slightly more efficient; we don't need to re-confirm the opcode of the instruction.
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3e6ba890 |
| 30-May-2022 |
zhongyunde <[email protected]> |
[InstCombine] Fold a mul with bool value into and
Fixes https://github.com/llvm/llvm-project/issues/55599 X * Y --> X & Y, iff X, Y can be only {0, 1}. https://alive2.llvm.org/ce/z/_RsTKF
Reviewe
[InstCombine] Fold a mul with bool value into and
Fixes https://github.com/llvm/llvm-project/issues/55599 X * Y --> X & Y, iff X, Y can be only {0, 1}. https://alive2.llvm.org/ce/z/_RsTKF
Reviewed By: spatel, nikic
Differential Revision: https://reviews.llvm.org/D126040
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b5b6aa4d |
| 27-May-2022 |
Sanjay Patel <[email protected]> |
[InstCombine] fold multiply by signbit-splat to cmp+select
(ashr i32 X, 31) * C --> (X < 0) ? -C : 0 https://alive2.llvm.org/ce/z/G8u9SS
With a constant operand, this is an improvement in IR and co
[InstCombine] fold multiply by signbit-splat to cmp+select
(ashr i32 X, 31) * C --> (X < 0) ? -C : 0 https://alive2.llvm.org/ce/z/G8u9SS
With a constant operand, this is an improvement in IR and codegen (where it can be converted to a mask op).
Without a constant operand, we would have to negate the operand, so that is probably better left to the backend.
This is similar but not the same optimization that is requested in #55618.
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5a6e0857 |
| 27-May-2022 |
Sanjay Patel <[email protected]> |
[InstCombine] reduce code duplication; NFC
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c4c75005 |
| 26-May-2022 |
Sanjay Patel <[email protected]> |
[InstCombine] fold mul of signbit directly to X < 0 ? Y : 0
This is effectively NFC (intentionally no test diffs) because we already have the related fold that converts the 'and' pattern to select.
[InstCombine] fold mul of signbit directly to X < 0 ? Y : 0
This is effectively NFC (intentionally no test diffs) because we already have the related fold that converts the 'and' pattern to select. So this is just an efficiency improvement.
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Revision tags: llvmorg-14.0.4 |
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e8c20d99 |
| 23-May-2022 |
Sanjay Patel <[email protected]> |
[IR] add and use pattern match specialization for sqrt intrinsic; NFC
This was included in D126190 originally, but it's independent and a useful change for readability.
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be7f09f7 |
| 16-May-2022 |
Sanjay Patel <[email protected]> |
[IR] create and use helper functions that test the signbit; NFCI
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2fa8fc3d |
| 12-May-2022 |
Sanjay Patel <[email protected]> |
[InstCombine] freeze operand in div+mul fold
As discussed in issue #37809, this transform is not safe if the input is an undefined value.
This is similar to recent changes for urem and sdiv: d428f0
[InstCombine] freeze operand in div+mul fold
As discussed in issue #37809, this transform is not safe if the input is an undefined value.
This is similar to recent changes for urem and sdiv: d428f09b2c9d 99ef341ce943
There is no difference in codegen on the basic examples, but this could lead to regressions. We may need to improve freeze analysis or lowering if that happens.
Presumably, in real cases that are similar to the tests where a subsequent transform removes the rem, we will also be able to remove the freeze by seeing that the parameter has 'noundef'.
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99ef341c |
| 11-May-2022 |
Sanjay Patel <[email protected]> |
[InstCombine] freeze operand in sdiv expansion
As discussed in issue #37809, this transform is not safe if the input is an undefined value.
This is similar to a recent change for urem: d428f09b2c9d
[InstCombine] freeze operand in sdiv expansion
As discussed in issue #37809, this transform is not safe if the input is an undefined value.
This is similar to a recent change for urem: d428f09b2c9d
There is no difference in codegen on the basic examples, but this could lead to regressions. We may need to improve freeze analysis or lowering if that happens.
Presumably, in real cases that are similar to the tests where a subsequent transform removes the select, we will also be able to remove the freeze by seeing that the parameter has 'noundef'.
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d428f09b |
| 11-May-2022 |
Sanjay Patel <[email protected]> |
[InstCombine] freeze operand in urem expansion
As discussed in issue #37809, this transform is not safe if the input is an undefined value.
There is no difference in codegen on the basic examples,
[InstCombine] freeze operand in urem expansion
As discussed in issue #37809, this transform is not safe if the input is an undefined value.
There is no difference in codegen on the basic examples, but this could lead to regressions. We may need to improve freeze analysis or lowering if that happens.
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Revision tags: llvmorg-14.0.3, llvmorg-14.0.2 |
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304378fd |
| 20-Apr-2022 |
Jonas Paulsson <[email protected]> |
Reapply "[BuildLibCalls] Introduce getOrInsertLibFunc() for use when building libcalls." (was 0f8c626). This reverts commit 14d9390.
The patch previously failed to recognize cases where user had def
Reapply "[BuildLibCalls] Introduce getOrInsertLibFunc() for use when building libcalls." (was 0f8c626). This reverts commit 14d9390.
The patch previously failed to recognize cases where user had defined a function alias with an identical name as that of the library function. Module::getFunction() would then return nullptr which is what the sanitizer discovered.
In this updated version a new function isLibFuncEmittable() has as well been introduced which is now used instead of TLI->has() anytime a library function is to be emitted . It additionally also makes sure there is e.g. no function alias with the same name in the module.
Reviewed By: Eli Friedman
Differential Revision: https://reviews.llvm.org/D123198
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fa4b4f0f |
| 12-Apr-2022 |
Liqin Weng <[email protected]> |
[InstCombine] fold more constant remainder to select-of-constants remainder
Reviewed By: xbolva00, spatel, Chenbing.Zheng
Differential Revision: https://reviews.llvm.org/D123486
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Revision tags: llvmorg-14.0.1 |
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467cbb62 |
| 08-Apr-2022 |
Chenbing Zheng <[email protected]> |
[InstCombine] fold more constant divisor to select-of-constants divisor
By adding a parameter to function FoldOpIntoSelect, we can fold more Ops to Select. For this example, we tend to fold the divi
[InstCombine] fold more constant divisor to select-of-constants divisor
By adding a parameter to function FoldOpIntoSelect, we can fold more Ops to Select. For this example, we tend to fold the division instruction, so we no longer care whether SelectInst is one use.
This patch slove TODO left in InstCombine/div.ll.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D122967
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Revision tags: llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3 |
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59630917 |
| 02-Mar-2022 |
serge-sans-paille <[email protected]> |
Cleanup includes: Transform/Scalar
Estimated impact on preprocessor output line: before: 1062981579 after: 1062494547
Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cl
Cleanup includes: Transform/Scalar
Estimated impact on preprocessor output line: before: 1062981579 after: 1062494547
Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup Differential Revision: https://reviews.llvm.org/D120817
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Revision tags: llvmorg-14.0.0-rc2 |
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587c7ff1 |
| 23-Feb-2022 |
Nikita Popov <[email protected]> |
[InstCombine] Support min/max intrinsics in udiv->lshr fold
This complements the existing fold for selects. This fold is a bit more conservative, requiring one-use. The other folds here should proba
[InstCombine] Support min/max intrinsics in udiv->lshr fold
This complements the existing fold for selects. This fold is a bit more conservative, requiring one-use. The other folds here should probably also be subjected to a one-use restriction.
https://alive2.llvm.org/ce/z/Q9eCDU https://alive2.llvm.org/ce/z/8YK2CJ
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03e6efb8 |
| 23-Feb-2022 |
Nikita Popov <[email protected]> |
[InstCombine] Further simplify udiv -> lshr folding
Rather than queuing up actions, have one function that does the log2() fold in the obvious way, but with a flag that allows us to check whether th
[InstCombine] Further simplify udiv -> lshr folding
Rather than queuing up actions, have one function that does the log2() fold in the obvious way, but with a flag that allows us to check whether the fold will succeed without actually performing it.
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5ccb0582 |
| 23-Feb-2022 |
Nikita Popov <[email protected]> |
[InstCombine] Simplify udiv -> lshr folding
What we're really doing here is converting Op0 udiv Op1 into Op0 lshr log2(Op1), so phrase it in that way. Actually pushing the lshr into the log2(Op1) ex
[InstCombine] Simplify udiv -> lshr folding
What we're really doing here is converting Op0 udiv Op1 into Op0 lshr log2(Op1), so phrase it in that way. Actually pushing the lshr into the log2(Op1) expression should be seen as a separate transform.
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5fb65557 |
| 23-Feb-2022 |
Nikita Popov <[email protected]> |
[InstCombine] Remove unused visitUDivOperand() argument (NFC)
This function only works on the RHS operand.
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Revision tags: llvmorg-14.0.0-rc1, llvmorg-15-init |
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39e602b6 |
| 22-Jan-2022 |
Sanjay Patel <[email protected]> |
[InstCombine] try to fold binop with phi operands
This is an alternate version of D115914 that handles/tests all binary opcodes.
I suspect that we don't see these patterns too often because -simpli
[InstCombine] try to fold binop with phi operands
This is an alternate version of D115914 that handles/tests all binary opcodes.
I suspect that we don't see these patterns too often because -simplifycfg would convert the minimal cases into selects rather than leave them in phi form (note: instcombine has logic holes for combining the select patterns too though, so that's another potential patch).
We only create a new binop in a predecessor that unconditionally branches to the final block. https://alive2.llvm.org/ce/z/C57M2F https://alive2.llvm.org/ce/z/WHwAoU (not safe to speculate an sdiv for example) https://alive2.llvm.org/ce/z/rdVUvW (but it is ok on this path)
Differential Revision: https://reviews.llvm.org/D117110
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Revision tags: llvmorg-13.0.1, llvmorg-13.0.1-rc3 |
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a7a2860d |
| 20-Jan-2022 |
Sanjay Patel <[email protected]> |
[InstCombine] convert mul with sexted bool and constant to select
We already have the related folds for zext-of-bool, so it should make things more consistent to have this transform to select for se
[InstCombine] convert mul with sexted bool and constant to select
We already have the related folds for zext-of-bool, so it should make things more consistent to have this transform to select for sext-of-bool too: https://alive2.llvm.org/ce/z/YikdfA
Fixes #53319
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Revision tags: llvmorg-13.0.1-rc2 |
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a7ed21aa |
| 08-Dec-2021 |
Sanjay Patel <[email protected]> |
[InstCombine] try to fold div with constant dividend and select-of-constants divisor
We avoid this fold in the more general cases where we use FoldOpIntoSelect. That's because -- unlike most binary
[InstCombine] try to fold div with constant dividend and select-of-constants divisor
We avoid this fold in the more general cases where we use FoldOpIntoSelect. That's because -- unlike most binary opcodes -- 'div' can't usually be speculated with a variable divisor since it can have immediate UB. But in the case where both arms of the select are constants, we can safely evaluate both sides and eliminate 'div' completely.
This is a follow-up to the equivalent fold for 'rem' opcodes: D115173 / f65be726ab50
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f65be726 |
| 07-Dec-2021 |
Sanjay Patel <[email protected]> |
[InstCombine] try to fold rem with constant dividend and select-of-constants divisor
We avoid this fold in the more general cases where we use `FoldOpIntoSelect`. That's because -- unlike most binar
[InstCombine] try to fold rem with constant dividend and select-of-constants divisor
We avoid this fold in the more general cases where we use `FoldOpIntoSelect`. That's because -- unlike most binary opcodes -- 'rem' can't usually be speculated with a variable divisor since it can have immediate UB. But in the case where both arms of the select are constants, we can safely evaluate both sides and eliminate 'rem' completely.
This should fix: https://llvm.org/PR52102
The same optimization for 'div' is planned as a follow-up patch.
Differential Revision: https://reviews.llvm.org/D115173
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