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Searched refs:CopyToReg (Results 1 – 25 of 33) sorted by relevance

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/llvm-project-15.0.7/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/
H A Damdgpu_isel.ll.expected8 ; CHECK-NEXT: t11: ch,glue = CopyToReg t0, Register:i32 $vgpr0, IMPLICIT_DEF:i32
10 ; CHECK-NEXT: t13: ch,glue = CopyToReg t11, Register:i32 $vgpr1, t17, t11:1
24 ; CHECK-NEXT: t7: ch,glue = CopyToReg t0, Register:i32 $vgpr0, t5
25 ; CHECK-NEXT: t9: ch,glue = CopyToReg t7, Register:i32 $vgpr1, t5, t7:1
40 ; CHECK-NEXT: t7: ch,glue = CopyToReg t0, Register:i32 $vgpr0, t5
41 ; CHECK-NEXT: t9: ch,glue = CopyToReg t7, Register:i32 $vgpr1, t5, t7:1
56 ; CHECK-NEXT: t7: ch,glue = CopyToReg t0, Register:i32 $vgpr0, t5
57 ; CHECK-NEXT: t9: ch,glue = CopyToReg t7, Register:i32 $vgpr1, t5, t7:1
H A Dlanai_isel.ll.expected19 ; CHECK-NEXT: t15: ch,glue = CopyToReg t0, Register:i32 $rv, t28
20 ; CHECK-NEXT: t17: ch,glue = CopyToReg t15, Register:i32 $r9, t24, t15:1
34 ; CHECK-NEXT: t13: ch,glue = CopyToReg t0, Register:i32 $rv, t21
38 ; CHECK-NEXT: t15: ch,glue = CopyToReg t13, Register:i32 $r9, t7, t13:1
53 ; CHECK-NEXT: t14: ch,glue = CopyToReg t0, Register:i32 $rv, t33
60 ; CHECK-NEXT: t16: ch,glue = CopyToReg t14, Register:i32 $r9, t27, t14:1
76 ; CHECK-NEXT: t14: ch,glue = CopyToReg t0, Register:i32 $rv, t33
84 ; CHECK-NEXT: t16: ch,glue = CopyToReg t14, Register:i32 $r9, t27, t14:1
H A Dx86_isel.ll.expected11 ; PIC-NEXT: t10: ch,glue = CopyToReg t0, Register:i64 $rax, t7
20 ; WIN-NEXT: t10: ch,glue = CopyToReg t0, Register:i64 $rax, t7
36 ; PIC-NEXT: t11: ch,glue = CopyToReg t0, Register:i64 $rax, t8
46 ; WIN-NEXT: t11: ch,glue = CopyToReg t0, Register:i64 $rax, t8
65 ; PIC-NEXT: t12: ch,glue = CopyToReg t0, Register:i64 $rax, t9
76 ; WIN-NEXT: t11: ch,glue = CopyToReg t0, Register:i64 $rax, t8
95 ; PIC-NEXT: t12: ch,glue = CopyToReg t0, Register:i64 $rax, t9
106 ; WIN-NEXT: t11: ch,glue = CopyToReg t0, Register:i64 $rax, t8
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dcallbr-asm-bb-exports.ll12 ; CHECK-NEXT: t12: ch = CopyToReg t0, Register:i32 %0, t10
15 ; CHECK-NEXT: t15: ch = CopyToReg t0, Register:i32 %1, t13
19 ; CHECK-NEXT: t22: ch,glue = CopyToReg t17, Register:i32 %5, t8
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelDAGToDAG.cpp262 SDValue CopyToReg = in SelectInlineAsmMemoryOperand() local
266 CurDAG->getCopyFromReg(CopyToReg, dl, VReg, TL.getPointerTy(DL)); in SelectInlineAsmMemoryOperand()
292 SDValue CopyToReg = CurDAG->getCopyToReg(Op, dl, VReg, Op); in SelectInlineAsmMemoryOperand() local
294 CurDAG->getCopyFromReg(CopyToReg, dl, VReg, TL.getPointerTy(DL)); in SelectInlineAsmMemoryOperand()
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dcopy-to-reg.ll4 ; Test that CopyToReg instructions don't have non-register operands prior
H A Dfunction-returns.ll472 ; lowering introduces an extra CopyToReg/CopyFromReg obscuring the
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp85 case ISD::CopyToReg: break; in numberRCValPredInSU()
122 case ISD::CopyToReg: NumberDeps++; break; in numberRCValSuccInSU()
444 case ISD::CopyToReg: in SUSchedulingCost()
H A DInstrEmitter.cpp112 if (User->getOpcode() == ISD::CopyToReg && in EmitCopyFromReg()
231 if (User->getOpcode() == ISD::CopyToReg && in CreateVirtualRegisters()
485 if (User->getOpcode() == ISD::CopyToReg && in EmitSubregNode()
1106 } else if (F->getOpcode() == ISD::CopyToReg) { in EmitMachineNode()
1166 case ISD::CopyToReg: { in EmitSpecialNode()
H A DScheduleDAGRRList.cpp710 case ISD::CopyToReg: in EmitNode()
1394 if (Node->getOpcode() == ISD::CopyToReg) { in DelayForLiveRegsBottomUp()
2049 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg) in getNodePriority()
2265 if (N->getOpcode() != ISD::CopyToReg) in unscheduledNode()
2351 Succ.getSUnit()->getNode()->getOpcode() == ISD::CopyToReg) in closestSucc()
2399 if (SuccSU->getNode() && SuccSU->getNode()->getOpcode() == ISD::CopyToReg) { in hasOnlyLiveOutUses()
2728 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg) in canEnableCoalescing()
2970 if (N->getOpcode() == ISD::CopyToReg && in PrescheduleNodesWithMultipleUses()
H A DScheduleDAGSDNodes.cpp114 if (Op != 2 || User->getOpcode() != ISD::CopyToReg) in CheckForPhysRegDependency()
427 if (SUNode->getOpcode() != ISD::CopyToReg) in BuildSchedUnits()
658 if (Latency > 1 && Use->getOpcode() == ISD::CopyToReg && in computeOperandLatency()
H A DScheduleDAGFast.cpp518 if (Node->getOpcode() == ISD::CopyToReg) { in DelayForLiveRegsBottomUp()
H A DSelectionDAGDumper.cpp170 case ISD::CopyToReg: return "CopyToReg"; in getOperationName()
H A DSelectionDAGISel.cpp705 if (N->getOpcode() != ISD::CopyToReg) in ComputeLiveOutVRegInfo()
2817 case ISD::CopyToReg: in SelectCodeCommon()
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Daarch64-checkMergeStoreCandidatesForDependencies.ll18 ; t14: ch,glue = CopyToReg t24, Register:i64 $x0, t19
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h203 CopyToReg, enumerator
H A DSelectionDAG.h752 return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,
763 return getNode(ISD::CopyToReg, dl, VTs,
772 return getNode(ISD::CopyToReg, dl, VTs,
/llvm-project-15.0.7/llvm/test/CodeGen/WebAssembly/
H A Duserstack.ll271 ; The use of the alloca in a phi causes a CopyToReg DAG node to be generated,
272 ; which has to have special handling because CopyToReg can't have a FI operand
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp361 if (N->getOpcode() == ISD::CopyToReg) { in getOperandRegClass()
662 case ISD::CopyToReg: { in Select()
2230 if (Cond.getOpcode() == ISD::CopyToReg) in isCBranchSCC()
H A DSIISelLowering.cpp5234 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg); in LowerBRCOND() local
5235 if (!CopyToReg) in LowerBRCOND()
5240 CopyToReg->getOperand(1), in LowerBRCOND()
5244 DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0)); in LowerBRCOND()
11741 if (Node->getOpcode() == ISD::CopyToReg) { in legalizeTargetIndependentNode()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp277 setOperationAction(ISD::CopyToReg, MVT::Other, Custom); in WebAssemblyTargetLowering()
1410 case ISD::CopyToReg: in LowerOperation()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp1767 if (CCUser->getOpcode() == ISD::CopyToReg || in IsProfitableToFold()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp2959 if (UI->getOpcode() != ISD::CopyToReg || in onlyUsesZeroFlag()
2995 if (UI->getOpcode() != ISD::CopyToReg || in hasNoSignFlagUses()
3053 if (UIOpc == ISD::CopyToReg) { in hasNoCarryFlagUses()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp2430 if (!Glued || Glued->getOpcode() != ISD::CopyToReg) in doPeepholeMaskedRVV()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelLowering.cpp2718 case ISD::CopyToReg: in isI32Insn()

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