1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=finalize-isel -debug-only=isel -o /dev/null %s 2>&1 | FileCheck %s
3
4define i64 @i64_test(i64 %i) nounwind readnone {
5; CHECK-LABEL: i64_test:
6; CHECK:       SelectionDAG has 9 nodes:
7; CHECK-NEXT:    t0: ch = EntryToken
8; CHECK-NEXT:    t11: ch,glue = CopyToReg t0, Register:i32 $vgpr0, IMPLICIT_DEF:i32
9; CHECK-NEXT:    t17: i32 = V_MOV_B32_e32 TargetConstant:i32<0>
10; CHECK-NEXT:    t13: ch,glue = CopyToReg t11, Register:i32 $vgpr1, t17, t11:1
11; CHECK-NEXT:    t14: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t13, t13:1
12; CHECK-EMPTY:
13  %loc = alloca i64
14  %j = load i64, i64 * %loc
15  %r = add i64 %i, %j
16  ret i64 %r
17}
18
19define i64 @i32_test(i32 %i) nounwind readnone {
20; CHECK-LABEL: i32_test:
21; CHECK:       SelectionDAG has 8 nodes:
22; CHECK-NEXT:    t5: i32 = V_MOV_B32_e32 TargetConstant:i32<0>
23; CHECK-NEXT:    t0: ch = EntryToken
24; CHECK-NEXT:    t7: ch,glue = CopyToReg t0, Register:i32 $vgpr0, t5
25; CHECK-NEXT:    t9: ch,glue = CopyToReg t7, Register:i32 $vgpr1, t5, t7:1
26; CHECK-NEXT:    t10: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t9, t9:1
27; CHECK-EMPTY:
28  %loc = alloca i32
29  %j = load i32, i32 * %loc
30  %r = add i32 %i, %j
31  %ext = zext i32 %r to i64
32  ret i64 %ext
33}
34
35define i64 @i16_test(i16 %i) nounwind readnone {
36; CHECK-LABEL: i16_test:
37; CHECK:       SelectionDAG has 8 nodes:
38; CHECK-NEXT:    t5: i32 = V_MOV_B32_e32 TargetConstant:i32<0>
39; CHECK-NEXT:    t0: ch = EntryToken
40; CHECK-NEXT:    t7: ch,glue = CopyToReg t0, Register:i32 $vgpr0, t5
41; CHECK-NEXT:    t9: ch,glue = CopyToReg t7, Register:i32 $vgpr1, t5, t7:1
42; CHECK-NEXT:    t10: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t9, t9:1
43; CHECK-EMPTY:
44  %loc = alloca i16
45  %j = load i16, i16 * %loc
46  %r = add i16 %i, %j
47  %ext = zext i16 %r to i64
48  ret i64 %ext
49}
50
51define i64 @i8_test(i8 %i) nounwind readnone {
52; CHECK-LABEL: i8_test:
53; CHECK:       SelectionDAG has 8 nodes:
54; CHECK-NEXT:    t5: i32 = V_MOV_B32_e32 TargetConstant:i32<0>
55; CHECK-NEXT:    t0: ch = EntryToken
56; CHECK-NEXT:    t7: ch,glue = CopyToReg t0, Register:i32 $vgpr0, t5
57; CHECK-NEXT:    t9: ch,glue = CopyToReg t7, Register:i32 $vgpr1, t5, t7:1
58; CHECK-NEXT:    t10: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t9, t9:1
59; CHECK-EMPTY:
60  %loc = alloca i8
61  %j = load i8, i8 * %loc
62  %r = add i8 %i, %j
63  %ext = zext i8 %r to i64
64  ret i64 %ext
65}
66