1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=lanai -stop-after=finalize-isel -debug-only=isel -o /dev/null %s 2>&1 | FileCheck %s
3
4define i64 @i64_test(i64 %i) nounwind readnone {
5; CHECK-LABEL: i64_test:
6; CHECK:       SelectionDAG has 22 nodes:
7; CHECK-NEXT:    t0: ch = EntryToken
8; CHECK-NEXT:    t5: i32,ch = LDW_RI<Mem:(load (s32) from %fixed-stack.0)> TargetFrameIndex:i32<-2>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
9; CHECK-NEXT:    t7: i32 = ADD_I_LO TargetFrameIndex:i32<0>, TargetConstant:i32<0>
10; CHECK-NEXT:    t29: i32 = OR_I_LO t7, TargetConstant:i32<4>
11; CHECK-NEXT:    t22: i32,ch = LDW_RI<Mem:(dereferenceable load (s32) from %ir.loc + 4, basealign 8)> t29, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
12; CHECK-NEXT:    t24: i32 = ADD_R t5, t22, TargetConstant:i32<0>
13; CHECK-NEXT:    t3: i32,ch = LDW_RI<Mem:(load (s32) from %fixed-stack.1, align 8)> TargetFrameIndex:i32<-1>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
14; CHECK-NEXT:    t19: i32,ch = LDW_RI<Mem:(dereferenceable load (s32) from %ir.loc, align 8)> TargetFrameIndex:i32<0>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
15; CHECK-NEXT:    t25: i32 = ADD_R t3, t19, TargetConstant:i32<0>
16; CHECK-NEXT:    t30: i32,glue = SFSUB_F_RR t24, t5
17; CHECK-NEXT:    t31: i32 = SCC TargetConstant:i32<4>, t30:1
18; CHECK-NEXT:    t28: i32 = ADD_R t25, t31, TargetConstant:i32<0>
19; CHECK-NEXT:    t15: ch,glue = CopyToReg t0, Register:i32 $rv, t28
20; CHECK-NEXT:    t17: ch,glue = CopyToReg t15, Register:i32 $r9, t24, t15:1
21; CHECK-NEXT:    t18: ch = RET Register:i32 $rv, Register:i32 $r9, t17, t17:1
22; CHECK-EMPTY:
23  %loc = alloca i64
24  %j = load i64, i64 * %loc
25  %r = add i64 %i, %j
26  ret i64 %r
27}
28
29define i64 @i32_test(i32 %i) nounwind readnone {
30; CHECK-LABEL: i32_test:
31; CHECK:       SelectionDAG has 14 nodes:
32; CHECK-NEXT:    t0: ch = EntryToken
33; CHECK-NEXT:    t21: i32,ch = CopyFromReg t0, Register:i32 $r0
34; CHECK-NEXT:    t13: ch,glue = CopyToReg t0, Register:i32 $rv, t21
35; CHECK-NEXT:    t3: i32,ch = LDW_RI<Mem:(load (s32) from %fixed-stack.0, align 8)> TargetFrameIndex:i32<-1>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
36; CHECK-NEXT:    t6: i32,ch = LDW_RI<Mem:(dereferenceable load (s32) from %ir.loc)> TargetFrameIndex:i32<0>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
37; CHECK-NEXT:    t7: i32 = ADD_R t3, t6, TargetConstant:i32<0>
38; CHECK-NEXT:    t15: ch,glue = CopyToReg t13, Register:i32 $r9, t7, t13:1
39; CHECK-NEXT:    t16: ch = RET Register:i32 $rv, Register:i32 $r9, t15, t15:1
40; CHECK-EMPTY:
41  %loc = alloca i32
42  %j = load i32, i32 * %loc
43  %r = add i32 %i, %j
44  %ext = zext i32 %r to i64
45  ret i64 %ext
46}
47
48define i64 @i16_test(i16 %i) nounwind readnone {
49; CHECK-LABEL: i16_test:
50; CHECK:       SelectionDAG has 19 nodes:
51; CHECK-NEXT:    t0: ch = EntryToken
52; CHECK-NEXT:    t33: i32,ch = CopyFromReg t0, Register:i32 $r0
53; CHECK-NEXT:    t14: ch,glue = CopyToReg t0, Register:i32 $rv, t33
54; CHECK-NEXT:    t1: i32 = ADD_I_LO TargetFrameIndex:i32<-1>, TargetConstant:i32<0>
55; CHECK-NEXT:    t21: i32 = OR_I_LO t1, TargetConstant:i32<2>
56; CHECK-NEXT:    t23: i32,ch = LDHz_RI<Mem:(load (s16) from %fixed-stack.0 + 2)> t21, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
57; CHECK-NEXT:    t22: i32,ch = LDHz_RI<Mem:(dereferenceable load (s16) from %ir.loc)> TargetFrameIndex:i32<0>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
58; CHECK-NEXT:    t24: i32 = ADD_R t23, t22, TargetConstant:i32<0>
59; CHECK-NEXT:    t27: i32 = AND_I_HI t24, TargetConstant:i32<0>
60; CHECK-NEXT:    t16: ch,glue = CopyToReg t14, Register:i32 $r9, t27, t14:1
61; CHECK-NEXT:    t28: i32 = TargetConstant<65535>
62; CHECK-NEXT:    t17: ch = RET Register:i32 $rv, Register:i32 $r9, t16, t16:1
63; CHECK-EMPTY:
64  %loc = alloca i16
65  %j = load i16, i16 * %loc
66  %r = add i16 %i, %j
67  %ext = zext i16 %r to i64
68  ret i64 %ext
69}
70
71define i64 @i8_test(i8 %i) nounwind readnone {
72; CHECK-LABEL: i8_test:
73; CHECK:       SelectionDAG has 20 nodes:
74; CHECK-NEXT:    t0: ch = EntryToken
75; CHECK-NEXT:    t33: i32,ch = CopyFromReg t0, Register:i32 $r0
76; CHECK-NEXT:    t14: ch,glue = CopyToReg t0, Register:i32 $rv, t33
77; CHECK-NEXT:    t1: i32 = ADD_I_LO TargetFrameIndex:i32<-1>, TargetConstant:i32<0>
78; CHECK-NEXT:    t21: i32 = OR_I_LO t1, TargetConstant:i32<3>
79; CHECK-NEXT:    t23: i32,ch = LDBz_RI<Mem:(load (s8) from %fixed-stack.0 + 3)> t21, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
80; CHECK-NEXT:    t22: i32,ch = LDBz_RI<Mem:(dereferenceable load (s8) from %ir.loc)> TargetFrameIndex:i32<0>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
81; CHECK-NEXT:    t24: i32 = ADD_R t23, t22, TargetConstant:i32<0>
82; CHECK-NEXT:    t26: i32 = SLI TargetConstant:i32<255>
83; CHECK-NEXT:    t27: i32 = AND_R t24, t26, TargetConstant:i32<0>
84; CHECK-NEXT:    t16: ch,glue = CopyToReg t14, Register:i32 $r9, t27, t14:1
85; CHECK-NEXT:    t17: ch = RET Register:i32 $rv, Register:i32 $r9, t16, t16:1
86; CHECK-EMPTY:
87  %loc = alloca i8
88  %j = load i8, i8 * %loc
89  %r = add i8 %i, %j
90  %ext = zext i8 %r to i64
91  ret i64 %ext
92}
93