| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1365 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, in CMSESaveClearFPRegsV8()
1366 ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7}) in CMSESaveClearFPRegsV8()
1459 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, in CMSESaveClearFPRegsV81()
1460 ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7}) in CMSESaveClearFPRegsV81()
1902 int LoReg = JumpReg == ARM::R4 ? ARM::R5 : ARM::R4; in CMSEPushCalleeSaves()
2092 *MBBI, {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12}, ClearRegs); in ExpandMI()
2125 {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, in ExpandMI()
2126 ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, in ExpandMI()
2127 ARM::R10, ARM::R11, ARM::R12}, in ExpandMI()
2332 ARM::t2BICri : ARM::BICri; in ExpandMI()
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| H A D | ARMFeatures.h | 28 case ARM::tADC: in isV8EligibleForIT()
32 case ARM::tAND: in isV8EligibleForIT()
35 case ARM::tBIC: in isV8EligibleForIT()
36 case ARM::tEOR: in isV8EligibleForIT()
42 case ARM::tMUL: in isV8EligibleForIT()
43 case ARM::tMVN: in isV8EligibleForIT()
44 case ARM::tORR: in isV8EligibleForIT()
45 case ARM::tROR: in isV8EligibleForIT()
46 case ARM::tRSB: in isV8EligibleForIT()
47 case ARM::tSBC: in isV8EligibleForIT()
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| H A D | ARMRegisterBankInfo.cpp | 30 namespace ARM { namespace
241 ? &ARM::ValueMappings[ARM::DPR3OpsIdx] in getInstrMapping()
242 : &ARM::ValueMappings[ARM::GPR3OpsIdx]; in getInstrMapping()
263 OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx]; in getInstrMapping()
277 ? &ARM::ValueMappings[ARM::GPR3OpsIdx] in getInstrMapping()
289 : &ARM::ValueMappings[ARM::GPR3OpsIdx]; in getInstrMapping()
299 ? &ARM::ValueMappings[ARM::DPR3OpsIdx] in getInstrMapping()
300 : &ARM::ValueMappings[ARM::SPR3OpsIdx]; in getInstrMapping()
385 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], in getInstrMapping()
386 &ARM::ValueMappings[ARM::GPR3OpsIdx], in getInstrMapping()
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| H A D | ARMBaseInstrInfo.cpp | 487 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); in insertBranch()
2397 {ARM::ADDSri, ARM::ADDri},
2398 {ARM::ADDSrr, ARM::ADDrr},
2399 {ARM::ADDSrsi, ARM::ADDrsi},
2400 {ARM::ADDSrsr, ARM::ADDrsr},
2402 {ARM::SUBSri, ARM::SUBri},
2403 {ARM::SUBSrr, ARM::SUBrr},
2407 {ARM::RSBSri, ARM::RSBri},
2414 {ARM::tADCS, ARM::tADC},
2419 {ARM::tSBCS, ARM::tSBC},
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| H A D | Thumb2SizeReduction.cpp | 84 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 },
85 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 },
86 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1,0 },
118 { ARM::t2SUBri, ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 0,0, 0,0,0 },
120 { ARM::t2SUBSri,ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 2,2, 0,0,0 },
131 { ARM::t2LDRi12,ARM::tLDRi, ARM::tLDRspi, 5, 8, 1, 0, 0,0, 0,1,0 },
140 { ARM::t2STRi12,ARM::tSTRi, ARM::tSTRspi, 5, 8, 1, 0, 0,0, 0,1,0 },
150 { ARM::t2LDMIA_UPD,ARM::tLDMIA_UPD,ARM::tPOP,0, 0, 1, 1, 1,1, 0,1,0 },
265 case ARM::tMUL: in isHighLatencyCPSR()
393 if (i == 1 && (Opc == ARM::t2LDRi12 || Opc == ARM::t2STRi12)) in VerifyLowRegs()
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| H A D | Thumb2InstrInfo.cpp | 409 case ARM::t2LDRi12: return ARM::t2LDRi8; in negativeOffsetOpcode()
414 case ARM::t2STRi12: return ARM::t2STRi8; in negativeOffsetOpcode()
417 case ARM::t2PLDi12: return ARM::t2PLDi8; in negativeOffsetOpcode()
419 case ARM::t2PLIi12: return ARM::t2PLIi8; in negativeOffsetOpcode()
443 case ARM::t2LDRi8: return ARM::t2LDRi12; in positiveOffsetOpcode()
448 case ARM::t2STRi8: return ARM::t2STRi12; in positiveOffsetOpcode()
451 case ARM::t2PLDi8: return ARM::t2PLDi12; in positiveOffsetOpcode()
477 case ARM::t2LDRs: return ARM::t2LDRi12; in immediateOffsetOpcode()
482 case ARM::t2STRs: return ARM::t2STRi12; in immediateOffsetOpcode()
485 case ARM::t2PLDs: return ARM::t2PLDi12; in immediateOffsetOpcode()
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| H A D | ARMInstrInfo.cpp | 62 case ARM::LDRH_PRE: in getUnindexedOpcode()
63 case ARM::LDRH_POST: in getUnindexedOpcode()
64 return ARM::LDRH; in getUnindexedOpcode()
70 case ARM::LDRSH_PRE: in getUnindexedOpcode()
72 return ARM::LDRSH; in getUnindexedOpcode()
81 case ARM::STRH_PRE: in getUnindexedOpcode()
83 return ARM::STRH; in getUnindexedOpcode()
101 expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_pcrel, ARM::LDRi12); in expandLoadStackGuard()
103 expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_abs, ARM::LDRi12); in expandLoadStackGuard()
108 expandLoadStackGuardBase(MI, ARM::MOVi32imm, ARM::LDRi12); in expandLoadStackGuard()
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| H A D | ARMLoadStoreOptimizer.cpp | 499 Opc == ARM::tLDRi || Opc == ARM::tLDRHi || Opc == ARM::tLDRBi; in UpdateBaseRegUses()
501 Opc == ARM::tSTRi || Opc == ARM::tSTRHi || Opc == ARM::tSTRBi; in UpdateBaseRegUses()
1037 if (PReg == ARM::SP || PReg == ARM::PC) in FormCandidates()
1063 if (Reg == ARM::SP || Reg == ARM::PC) in FormCandidates()
1637 NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_PRE : ARM::t2STRD_PRE; in MergeBaseUpdateLSDouble()
1642 NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_POST : ARM::t2STRD_POST; in MergeBaseUpdateLSDouble()
1764 if (Opcode != ARM::LDRD && Opcode != ARM::STRD && Opcode != ARM::t2LDRDi8) in FixInvalidRegPairOp()
1829 ? (isT2 ? (OffImm < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12) in FixInvalidRegPairOp()
1830 : (isT2 ? (OffImm < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12); in FixInvalidRegPairOp()
1834 ? (isT2 ? (OffImm+4 < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12) in FixInvalidRegPairOp()
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| H A D | ARMBaseInstrInfo.h | 564 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; in isUncondBranchOpcode()
640 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc; in isCondBranchOpcode()
644 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm_i12 || in isJumpTableBranchOpcode()
645 Opc == ARM::BR_JTm_rs || Opc == ARM::BR_JTadd || Opc == ARM::tBR_JTr || in isJumpTableBranchOpcode()
651 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND; in isIndirectBranchOpcode()
717 Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD || in isPopOpcode()
722 return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD || in isPushOpcode()
728 Opc == ARM::tSUBi3 || Opc == ARM::tSUBi8 || in isSubImmOpcode()
729 Opc == ARM::tSUBSi3 || Opc == ARM::tSUBSi8 || in isSubImmOpcode()
730 Opc == ARM::t2SUBri || Opc == ARM::t2SUBri12 || Opc == ARM::t2SUBSri; in isSubImmOpcode()
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| H A D | Thumb1FrameLowering.cpp | 90 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDhirr), ARM::SP) in emitPrologueEpilogueSPUpdate()
414 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4) in emitPrologue()
844 for (unsigned ArgReg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) in spillCalleeSavedRegisters()
853 for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::LR}) { in spillCalleeSavedRegisters()
874 static const unsigned AllCopyRegs[] = {ARM::LR, ARM::R7, ARM::R6, in spillCalleeSavedRegisters()
875 ARM::R5, ARM::R4, ARM::R3, in spillCalleeSavedRegisters()
876 ARM::R2, ARM::R1, ARM::R0}; in spillCalleeSavedRegisters()
877 static const unsigned AllHighRegs[] = {ARM::R11, ARM::R10, ARM::R9, ARM::R8}; in spillCalleeSavedRegisters()
982 static const unsigned AllCopyRegs[] = {ARM::R0, ARM::R1, ARM::R2, ARM::R3, in restoreCalleeSavedRegisters()
983 ARM::R4, ARM::R5, ARM::R6, ARM::R7}; in restoreCalleeSavedRegisters()
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| H A D | MVETailPredUtils.h | 30 case ARM::MVE_VCTP8: in VCTPOpcodeToLSTP()
31 return IsDoLoop ? ARM::MVE_DLSTP_8 : ARM::MVE_WLSTP_8; in VCTPOpcodeToLSTP()
32 case ARM::MVE_VCTP16: in VCTPOpcodeToLSTP()
33 return IsDoLoop ? ARM::MVE_DLSTP_16 : ARM::MVE_WLSTP_16; in VCTPOpcodeToLSTP()
34 case ARM::MVE_VCTP32: in VCTPOpcodeToLSTP()
35 return IsDoLoop ? ARM::MVE_DLSTP_32 : ARM::MVE_WLSTP_32; in VCTPOpcodeToLSTP()
36 case ARM::MVE_VCTP64: in VCTPOpcodeToLSTP()
37 return IsDoLoop ? ARM::MVE_DLSTP_64 : ARM::MVE_WLSTP_64; in VCTPOpcodeToLSTP()
46 case ARM::MVE_VCTP8: in getTailPredVectorWidth()
48 case ARM::MVE_VCTP16: in getTailPredVectorWidth()
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| H A D | ARMTargetTransformInfo.h | 72 ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureNEON, ARM::FeatureThumb2,
73 ARM::FeatureFP16, ARM::FeatureVFP4, ARM::FeatureFPARMv8,
74 ARM::FeatureFullFP16, ARM::FeatureFP16FML, ARM::FeatureHWDivThumb,
75 ARM::FeatureHWDivARM, ARM::FeatureDB, ARM::FeatureV7Clrex,
77 ARM::FeaturePerfMon, ARM::FeatureTrustZone, ARM::Feature8MSecExt,
78 ARM::FeatureCrypto, ARM::FeatureCRC, ARM::FeatureRAS,
79 ARM::FeatureFPAO, ARM::FeatureFuseAES, ARM::FeatureZCZeroing,
91 ARM::FeatureHasNoBranchPredictor, ARM::FeatureDSP, ARM::FeatureMP,
92 ARM::FeatureVirtualization, ARM::FeatureMClass, ARM::FeatureRClass,
93 ARM::FeatureAClass, ARM::FeatureNaClTrap, ARM::FeatureStrictAlign,
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| H A D | ARMISelDAGToDAG.cpp | 3570 Opc = (Opc == ARM::tLSLri) ? ARM::t2LSLri : ARM::t2LSRri; in SelectCMPZ()
4100 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc; in Select()
4440 ARM::VLD2d8wb_fixed, ARM::VLD2d16wb_fixed, ARM::VLD2d32wb_fixed, in Select()
4477 ARM::VLD4d8Pseudo_UPD, ARM::VLD4d16Pseudo_UPD, ARM::VLD4d32Pseudo_UPD, in Select()
4505 ARM::VLD1q8wb_fixed, ARM::VLD1q16wb_fixed, ARM::VLD1q32wb_fixed, in Select()
4596 ARM::VST2d8wb_fixed, ARM::VST2d16wb_fixed, ARM::VST2d32wb_fixed, in Select()
4625 ARM::VST4d8Pseudo_UPD, ARM::VST4d16Pseudo_UPD, ARM::VST4d32Pseudo_UPD, in Select()
5294 ARM::MVE_VIDUPu8, ARM::MVE_VIDUPu16, ARM::MVE_VIDUPu32, in Select()
5304 ARM::MVE_VDDUPu8, ARM::MVE_VDDUPu16, ARM::MVE_VDDUPu32, in Select()
5314 ARM::MVE_VIWDUPu8, ARM::MVE_VIWDUPu16, ARM::MVE_VIWDUPu32, in Select()
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| H A D | ARMFrameLowering.cpp | 1906 case ARM::R0: case ARM::R1: in determineCalleeSaves()
1907 case ARM::R2: case ARM::R3: in determineCalleeSaves()
1908 case ARM::R4: case ARM::R5: in determineCalleeSaves()
1909 case ARM::R6: case ARM::R7: in determineCalleeSaves()
1922 case ARM::R0: case ARM::R1: in determineCalleeSaves()
1923 case ARM::R2: case ARM::R3: in determineCalleeSaves()
1924 case ARM::R4: case ARM::R5: in determineCalleeSaves()
1925 case ARM::R6: case ARM::R7: in determineCalleeSaves()
2089 for (unsigned Reg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) { in determineCalleeSaves()
2110 for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6}) { in determineCalleeSaves()
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| H A D | ARMAsmPrinter.cpp | 1445 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16); in emitInstruction()
1633 case ARM::PICSTR: Opcode = ARM::STRrs; break; in emitInstruction()
1634 case ARM::PICSTRB: Opcode = ARM::STRBrs; break; in emitInstruction()
1635 case ARM::PICSTRH: Opcode = ARM::STRH; break; in emitInstruction()
1636 case ARM::PICLDR: Opcode = ARM::LDRrs; break; in emitInstruction()
1637 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break; in emitInstruction()
1638 case ARM::PICLDRH: Opcode = ARM::LDRH; break; in emitInstruction()
1639 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break; in emitInstruction()
1640 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break; in emitInstruction()
1701 unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH; in emitInstruction()
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| H A D | ARMCallingConv.cpp | 24 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS()
65 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64AssignAAPCS()
68 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS()
153 static const MCPhysReg RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
155 static const MCPhysReg SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3,
156 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
157 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
158 ARM::S12, ARM::S13, ARM::S14, ARM::S15 };
159 static const MCPhysReg DRegList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3,
160 ARM::D4, ARM::D5, ARM::D6, ARM::D7 };
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| H A D | ARMSLSHardening.cpp | 134 {"__llvm_slsblr_thunk_arm_r0", ARM::R0, false},
135 {"__llvm_slsblr_thunk_arm_r1", ARM::R1, false},
136 {"__llvm_slsblr_thunk_arm_r2", ARM::R2, false},
213 BuildMI(Entry, DebugLoc(), TII->get(ARM::BX)) in populateThunk()
260 case ARM::BLX: // !isThumb2 in ConvertIndirectCallToIndirectJump()
261 case ARM::BLX_noip: // !isThumb2 in ConvertIndirectCallToIndirectJump()
265 case ARM::tBLXr: // isThumb2 in ConvertIndirectCallToIndirectJump()
266 case ARM::tBLXr_noip: // isThumb2 in ConvertIndirectCallToIndirectJump()
281 assert(Reg != ARM::R12 && Reg != ARM::LR); in ConvertIndirectCallToIndirectJump()
316 if (Op.getReg() == ARM::LR && Op.isDef()) in ConvertIndirectCallToIndirectJump()
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| H A D | Thumb1InstrInfo.cpp | 28 return MCInstBuilder(ARM::tMOVr) in getNop()
29 .addReg(ARM::R8) in getNop()
30 .addReg(ARM::R8) in getNop()
69 BuildMI(MBB, I, DL, get(ARM::tPUSH)) in copyPhysReg()
72 BuildMI(MBB, I, DL, get(ARM::tPOP)) in copyPhysReg()
83 assert((RC == &ARM::tGPRRegClass || in storeRegToStackSlot()
87 if (RC == &ARM::tGPRRegClass || in storeRegToStackSlot()
97 BuildMI(MBB, I, DL, get(ARM::tSTRspi)) in storeRegToStackSlot()
139 expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_pcrel, ARM::tLDRi); in expandLoadStackGuard()
141 expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_abs, ARM::tLDRi); in expandLoadStackGuard()
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Support/ |
| H A D | ARMTargetParser.def | 91 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
95 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
99 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
100 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS))
103 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
104 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS))
107 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
108 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS |
112 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
113 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS |
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMTargetStreamer.cpp | 132 if (STI.hasFeature(ARM::FeatureMClass) && STI.hasFeature(ARM::FeatureDSP)) in getArchForCPU()
174 emitArchExtension(ARM::AEK_HWDIVTHUMB | ARM::AEK_HWDIVARM); in emitTargetAttributes()
218 emitFPU(STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_NEON_FP16 in emitTargetAttributes()
232 : (STI.hasFeature(ARM::FeatureFP64) ? ARM::FK_FPV5_D16 in emitTargetAttributes()
236 ? ARM::FK_VFPV4 in emitTargetAttributes()
237 : (STI.hasFeature(ARM::FeatureFP64) ? ARM::FK_VFPV4_D16 in emitTargetAttributes()
243 ? (STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_VFPV3_FP16 in emitTargetAttributes()
250 : (STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_VFPV3XD_FP16 in emitTargetAttributes()
253 emitFPU(ARM::FK_VFPV2); in emitTargetAttributes()
257 if (STI.hasFeature(ARM::FeatureVFP2_SP) && !STI.hasFeature(ARM::FeatureFP64)) in emitTargetAttributes()
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| H A D | ARMAsmBackend.cpp | 215 case ARM::tBcc: in getRelaxedOpcode()
217 case ARM::tLDRpci: in getRelaxedOpcode()
219 case ARM::tADR: in getRelaxedOpcode()
221 case ARM::tB: in getRelaxedOpcode()
223 case ARM::tCBZ: in getRelaxedOpcode()
224 return ARM::tHINT; in getRelaxedOpcode()
225 case ARM::tCBNZ: in getRelaxedOpcode()
226 return ARM::tHINT; in getRelaxedOpcode()
299 case ARM::fixup_wls: in reasonForFixupRelaxation()
301 case ARM::fixup_le: in reasonForFixupRelaxation()
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| H A D | ARMMCTargetDesc.cpp | 41 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] && in getMCRDeprecationInfo()
130 case ARM::LR: in getARMLoadDeprecationInfo()
133 case ARM::PC: in getARMLoadDeprecationInfo()
156 ARM::ArchKind ArchID = ARM::parseArch(TT.getArchName()); in ParseARMTriple()
210 if (InstDesc.getOpcode() == ARM::tBLXi) in evaluateBranchTarget()
241 {codeview::RegisterId::ARM_R0, ARM::R0}, in initLLVMToCVRegMapping()
242 {codeview::RegisterId::ARM_R1, ARM::R1}, in initLLVMToCVRegMapping()
243 {codeview::RegisterId::ARM_R2, ARM::R2}, in initLLVMToCVRegMapping()
244 {codeview::RegisterId::ARM_R3, ARM::R3}, in initLLVMToCVRegMapping()
245 {codeview::RegisterId::ARM_R4, ARM::R4}, in initLLVMToCVRegMapping()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1120 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1121 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1122 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1123 ARM::R12, ARM::SP, ARM::LR, ARM::PC
1127 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1128 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1129 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1403 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1404 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1405 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 4436 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; in getNextRegister()
4437 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; in getNextRegister()
4438 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; in getNextRegister()
4439 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; in getNextRegister()
4440 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; in getNextRegister()
4441 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; in getNextRegister()
4442 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; in getNextRegister()
4443 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; in getNextRegister()
12247 {ARM::FeatureAES, ARM::FeatureNEON, ARM::FeatureFPARMv8}}, in enableArchExtFeature()
12250 {ARM::FeatureSHA2, ARM::FeatureNEON, ARM::FeatureFPARMv8}}, in enableArchExtFeature()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Support/ |
| H A D | ARMTargetParser.cpp | 28 ARM::ArchKind ARM::parseArch(StringRef Arch) { in parseArch()
92 ARM::ProfileKind ARM::parseArchProfile(StringRef Arch) { in parseArchProfile()
232 ARM::EndianKind ARM::parseArchEndian(StringRef Arch) { in parseArchEndian()
251 ARM::ISAKind ARM::parseArchISA(StringRef Arch) { in parseArchISA()
357 ARM::FPUVersion ARM::getFPUVersion(unsigned FPUKind) { in getFPUVersion()
428 StringRef ARM::getArchName(ARM::ArchKind AK) { in getArchName()
432 StringRef ARM::getCPUAttr(ARM::ArchKind AK) { in getCPUAttr()
436 StringRef ARM::getSubArch(ARM::ArchKind AK) { in getSubArch()
440 unsigned ARM::getArchAttr(ARM::ArchKind AK) { in getArchAttr()
487 for (const ARM::FPUName &CandidateFPU : ARM::FPUNames) { in findDoublePrecisionFPU()
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