Lines Matching refs:ARM
185 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
186 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
187 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
188 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
189 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
190 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
192 { ARM::VLD1d16QPseudo, ARM::VLD1d16Q, true, false, false, SingleSpc, 4, 4 ,false},
193 { ARM::VLD1d16QPseudoWB_fixed, ARM::VLD1d16Qwb_fixed, true, true, false, SingleSpc, 4, 4 ,false…
194 { ARM::VLD1d16QPseudoWB_register, ARM::VLD1d16Qwb_register, true, true, true, SingleSpc, 4, 4 ,fa…
195 { ARM::VLD1d16TPseudo, ARM::VLD1d16T, true, false, false, SingleSpc, 3, 4 ,false},
196 { ARM::VLD1d16TPseudoWB_fixed, ARM::VLD1d16Twb_fixed, true, true, false, SingleSpc, 3, 4 ,false…
197 { ARM::VLD1d16TPseudoWB_register, ARM::VLD1d16Twb_register, true, true, true, SingleSpc, 3, 4 ,fa…
199 { ARM::VLD1d32QPseudo, ARM::VLD1d32Q, true, false, false, SingleSpc, 4, 2 ,false},
200 { ARM::VLD1d32QPseudoWB_fixed, ARM::VLD1d32Qwb_fixed, true, true, false, SingleSpc, 4, 2 ,false…
201 { ARM::VLD1d32QPseudoWB_register, ARM::VLD1d32Qwb_register, true, true, true, SingleSpc, 4, 2 ,fa…
202 { ARM::VLD1d32TPseudo, ARM::VLD1d32T, true, false, false, SingleSpc, 3, 2 ,false},
203 { ARM::VLD1d32TPseudoWB_fixed, ARM::VLD1d32Twb_fixed, true, true, false, SingleSpc, 3, 2 ,false…
204 { ARM::VLD1d32TPseudoWB_register, ARM::VLD1d32Twb_register, true, true, true, SingleSpc, 3, 2 ,fa…
206 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false},
207 { ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,fals…
208 { ARM::VLD1d64QPseudoWB_register, ARM::VLD1d64Qwb_register, true, true, true, SingleSpc, 4, 1 …
209 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false},
210 { ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,fals…
211 { ARM::VLD1d64TPseudoWB_register, ARM::VLD1d64Twb_register, true, true, true, SingleSpc, 3, 1 ,f…
213 { ARM::VLD1d8QPseudo, ARM::VLD1d8Q, true, false, false, SingleSpc, 4, 8 ,false},
214 { ARM::VLD1d8QPseudoWB_fixed, ARM::VLD1d8Qwb_fixed, true, true, false, SingleSpc, 4, 8 ,fals…
215 { ARM::VLD1d8QPseudoWB_register, ARM::VLD1d8Qwb_register, true, true, true, SingleSpc, 4, 8 ,fa…
216 { ARM::VLD1d8TPseudo, ARM::VLD1d8T, true, false, false, SingleSpc, 3, 8 ,false},
217 { ARM::VLD1d8TPseudoWB_fixed, ARM::VLD1d8Twb_fixed, true, true, false, SingleSpc, 3, 8 ,fals…
218 { ARM::VLD1d8TPseudoWB_register, ARM::VLD1d8Twb_register, true, true, true, SingleSpc, 3, 8 ,f…
220 { ARM::VLD1q16HighQPseudo, ARM::VLD1d16Q, true, false, false, SingleHighQSpc, 4, 4 ,false},
221 { ARM::VLD1q16HighQPseudo_UPD, ARM::VLD1d16Qwb_fixed, true, true, true, SingleHighQSpc, 4, 4 ,f…
222 { ARM::VLD1q16HighTPseudo, ARM::VLD1d16T, true, false, false, SingleHighTSpc, 3, 4 ,false},
223 { ARM::VLD1q16HighTPseudo_UPD, ARM::VLD1d16Twb_fixed, true, true, true, SingleHighTSpc, 3, 4 ,f…
224 { ARM::VLD1q16LowQPseudo_UPD, ARM::VLD1d16Qwb_fixed, true, true, true, SingleLowSpc, 4, 4 ,fal…
225 { ARM::VLD1q16LowTPseudo_UPD, ARM::VLD1d16Twb_fixed, true, true, true, SingleLowSpc, 3, 4 ,fal…
227 { ARM::VLD1q32HighQPseudo, ARM::VLD1d32Q, true, false, false, SingleHighQSpc, 4, 2 ,false},
228 { ARM::VLD1q32HighQPseudo_UPD, ARM::VLD1d32Qwb_fixed, true, true, true, SingleHighQSpc, 4, 2 ,f…
229 { ARM::VLD1q32HighTPseudo, ARM::VLD1d32T, true, false, false, SingleHighTSpc, 3, 2 ,false},
230 { ARM::VLD1q32HighTPseudo_UPD, ARM::VLD1d32Twb_fixed, true, true, true, SingleHighTSpc, 3, 2 ,f…
231 { ARM::VLD1q32LowQPseudo_UPD, ARM::VLD1d32Qwb_fixed, true, true, true, SingleLowSpc, 4, 2 ,fal…
232 { ARM::VLD1q32LowTPseudo_UPD, ARM::VLD1d32Twb_fixed, true, true, true, SingleLowSpc, 3, 2 ,fal…
234 { ARM::VLD1q64HighQPseudo, ARM::VLD1d64Q, true, false, false, SingleHighQSpc, 4, 1 ,false},
235 { ARM::VLD1q64HighQPseudo_UPD, ARM::VLD1d64Qwb_fixed, true, true, true, SingleHighQSpc, 4, 1 ,f…
236 { ARM::VLD1q64HighTPseudo, ARM::VLD1d64T, true, false, false, SingleHighTSpc, 3, 1 ,false},
237 { ARM::VLD1q64HighTPseudo_UPD, ARM::VLD1d64Twb_fixed, true, true, true, SingleHighTSpc, 3, 1 ,f…
238 { ARM::VLD1q64LowQPseudo_UPD, ARM::VLD1d64Qwb_fixed, true, true, true, SingleLowSpc, 4, 1 ,fal…
239 { ARM::VLD1q64LowTPseudo_UPD, ARM::VLD1d64Twb_fixed, true, true, true, SingleLowSpc, 3, 1 ,fal…
241 { ARM::VLD1q8HighQPseudo, ARM::VLD1d8Q, true, false, false, SingleHighQSpc, 4, 8 ,false},
242 { ARM::VLD1q8HighQPseudo_UPD, ARM::VLD1d8Qwb_fixed, true, true, true, SingleHighQSpc, 4, 8 ,fal…
243 { ARM::VLD1q8HighTPseudo, ARM::VLD1d8T, true, false, false, SingleHighTSpc, 3, 8 ,false},
244 { ARM::VLD1q8HighTPseudo_UPD, ARM::VLD1d8Twb_fixed, true, true, true, SingleHighTSpc, 3, 8 ,fal…
245 { ARM::VLD1q8LowQPseudo_UPD, ARM::VLD1d8Qwb_fixed, true, true, true, SingleLowSpc, 4, 8 ,false…
246 { ARM::VLD1q8LowTPseudo_UPD, ARM::VLD1d8Twb_fixed, true, true, true, SingleLowSpc, 3, 8 ,false…
248 { ARM::VLD2DUPq16EvenPseudo, ARM::VLD2DUPd16x2, true, false, false, EvenDblSpc, 2, 4 ,false},
249 { ARM::VLD2DUPq16OddPseudo, ARM::VLD2DUPd16x2, true, false, false, OddDblSpc, 2, 4 ,false},
250 { ARM::VLD2DUPq16OddPseudoWB_fixed, ARM::VLD2DUPd16x2wb_fixed, true, true, false, OddDblSpc, 2, …
251 { ARM::VLD2DUPq16OddPseudoWB_register, ARM::VLD2DUPd16x2wb_register, true, true, true, OddDblSpc,…
252 { ARM::VLD2DUPq32EvenPseudo, ARM::VLD2DUPd32x2, true, false, false, EvenDblSpc, 2, 2 ,false},
253 { ARM::VLD2DUPq32OddPseudo, ARM::VLD2DUPd32x2, true, false, false, OddDblSpc, 2, 2 ,false},
254 { ARM::VLD2DUPq32OddPseudoWB_fixed, ARM::VLD2DUPd32x2wb_fixed, true, true, false, OddDblSpc, 2, …
255 { ARM::VLD2DUPq32OddPseudoWB_register, ARM::VLD2DUPd32x2wb_register, true, true, true, OddDblSpc,…
256 { ARM::VLD2DUPq8EvenPseudo, ARM::VLD2DUPd8x2, true, false, false, EvenDblSpc, 2, 8 ,false},
257 { ARM::VLD2DUPq8OddPseudo, ARM::VLD2DUPd8x2, true, false, false, OddDblSpc, 2, 8 ,false},
258 { ARM::VLD2DUPq8OddPseudoWB_fixed, ARM::VLD2DUPd8x2wb_fixed, true, true, false, OddDblSpc, 2, 8…
259 { ARM::VLD2DUPq8OddPseudoWB_register, ARM::VLD2DUPd8x2wb_register, true, true, true, OddDblSpc, …
261 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true},
262 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true},
263 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true},
264 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true},
265 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true},
266 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true},
267 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true},
268 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true},
269 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true},
270 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true},
272 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false},
273 { ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false},
274 { ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,fa…
275 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false},
276 { ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false},
277 { ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,fa…
278 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false},
279 { ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false},
280 { ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,fal…
282 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true},
283 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true},
284 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true},
285 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true},
286 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true},
287 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true},
288 { ARM::VLD3DUPq16EvenPseudo, ARM::VLD3DUPq16, true, false, false, EvenDblSpc, 3, 4 ,true},
289 { ARM::VLD3DUPq16OddPseudo, ARM::VLD3DUPq16, true, false, false, OddDblSpc, 3, 4 ,true},
290 { ARM::VLD3DUPq16OddPseudo_UPD, ARM::VLD3DUPq16_UPD, true, true, true, OddDblSpc, 3, 4 ,true},
291 { ARM::VLD3DUPq32EvenPseudo, ARM::VLD3DUPq32, true, false, false, EvenDblSpc, 3, 2 ,true},
292 { ARM::VLD3DUPq32OddPseudo, ARM::VLD3DUPq32, true, false, false, OddDblSpc, 3, 2 ,true},
293 { ARM::VLD3DUPq32OddPseudo_UPD, ARM::VLD3DUPq32_UPD, true, true, true, OddDblSpc, 3, 2 ,true},
294 { ARM::VLD3DUPq8EvenPseudo, ARM::VLD3DUPq8, true, false, false, EvenDblSpc, 3, 8 ,true},
295 { ARM::VLD3DUPq8OddPseudo, ARM::VLD3DUPq8, true, false, false, OddDblSpc, 3, 8 ,true},
296 { ARM::VLD3DUPq8OddPseudo_UPD, ARM::VLD3DUPq8_UPD, true, true, true, OddDblSpc, 3, 8 ,true},
298 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true},
299 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
300 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true},
301 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
302 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true},
303 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
304 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true},
305 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
306 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true},
307 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
309 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true},
310 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
311 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true},
312 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
313 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true},
314 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
316 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
317 { ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true},
318 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true},
319 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
320 { ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true},
321 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true},
322 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true},
323 { ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true},
324 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true},
326 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true},
327 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true},
328 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true},
329 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true},
330 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true},
331 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true},
332 { ARM::VLD4DUPq16EvenPseudo, ARM::VLD4DUPq16, true, false, false, EvenDblSpc, 4, 4 ,true},
333 { ARM::VLD4DUPq16OddPseudo, ARM::VLD4DUPq16, true, false, false, OddDblSpc, 4, 4 ,true},
334 { ARM::VLD4DUPq16OddPseudo_UPD, ARM::VLD4DUPq16_UPD, true, true, true, OddDblSpc, 4, 4 ,true},
335 { ARM::VLD4DUPq32EvenPseudo, ARM::VLD4DUPq32, true, false, false, EvenDblSpc, 4, 2 ,true},
336 { ARM::VLD4DUPq32OddPseudo, ARM::VLD4DUPq32, true, false, false, OddDblSpc, 4, 2 ,true},
337 { ARM::VLD4DUPq32OddPseudo_UPD, ARM::VLD4DUPq32_UPD, true, true, true, OddDblSpc, 4, 2 ,true},
338 { ARM::VLD4DUPq8EvenPseudo, ARM::VLD4DUPq8, true, false, false, EvenDblSpc, 4, 8 ,true},
339 { ARM::VLD4DUPq8OddPseudo, ARM::VLD4DUPq8, true, false, false, OddDblSpc, 4, 8 ,true},
340 { ARM::VLD4DUPq8OddPseudo_UPD, ARM::VLD4DUPq8_UPD, true, true, true, OddDblSpc, 4, 8 ,true},
342 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true},
343 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
344 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true},
345 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
346 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true},
347 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
348 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true},
349 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
350 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true},
351 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
353 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true},
354 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
355 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true},
356 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
357 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true},
358 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
360 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
361 { ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true},
362 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true},
363 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
364 { ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true},
365 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true},
366 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true},
367 { ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true},
368 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true},
370 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true},
371 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true},
372 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true},
373 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true},
374 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true},
375 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true},
377 { ARM::VST1d16QPseudo, ARM::VST1d16Q, false, false, false, SingleSpc, 4, 4 ,false},
378 { ARM::VST1d16QPseudoWB_fixed, ARM::VST1d16Qwb_fixed, false, true, false, SingleSpc, 4, 4 ,false},
379 { ARM::VST1d16QPseudoWB_register, ARM::VST1d16Qwb_register, false, true, true, SingleSpc, 4, 4 ,fa…
380 { ARM::VST1d16TPseudo, ARM::VST1d16T, false, false, false, SingleSpc, 3, 4 ,false},
381 { ARM::VST1d16TPseudoWB_fixed, ARM::VST1d16Twb_fixed, false, true, false, SingleSpc, 3, 4 ,false},
382 { ARM::VST1d16TPseudoWB_register, ARM::VST1d16Twb_register, false, true, true, SingleSpc, 3, 4 ,fa…
384 { ARM::VST1d32QPseudo, ARM::VST1d32Q, false, false, false, SingleSpc, 4, 2 ,false},
385 { ARM::VST1d32QPseudoWB_fixed, ARM::VST1d32Qwb_fixed, false, true, false, SingleSpc, 4, 2 ,false},
386 { ARM::VST1d32QPseudoWB_register, ARM::VST1d32Qwb_register, false, true, true, SingleSpc, 4, 2 ,fa…
387 { ARM::VST1d32TPseudo, ARM::VST1d32T, false, false, false, SingleSpc, 3, 2 ,false},
388 { ARM::VST1d32TPseudoWB_fixed, ARM::VST1d32Twb_fixed, false, true, false, SingleSpc, 3, 2 ,false},
389 { ARM::VST1d32TPseudoWB_register, ARM::VST1d32Twb_register, false, true, true, SingleSpc, 3, 2 ,fa…
391 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false},
392 { ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false…
393 { ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,f…
394 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false},
395 { ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false…
396 { ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,f…
398 { ARM::VST1d8QPseudo, ARM::VST1d8Q, false, false, false, SingleSpc, 4, 8 ,false},
399 { ARM::VST1d8QPseudoWB_fixed, ARM::VST1d8Qwb_fixed, false, true, false, SingleSpc, 4, 8 ,false},
400 { ARM::VST1d8QPseudoWB_register, ARM::VST1d8Qwb_register, false, true, true, SingleSpc, 4, 8 ,fal…
401 { ARM::VST1d8TPseudo, ARM::VST1d8T, false, false, false, SingleSpc, 3, 8 ,false},
402 { ARM::VST1d8TPseudoWB_fixed, ARM::VST1d8Twb_fixed, false, true, false, SingleSpc, 3, 8 ,false},
403 { ARM::VST1d8TPseudoWB_register, ARM::VST1d8Twb_register, false, true, true, SingleSpc, 3, 8 ,fal…
405 { ARM::VST1q16HighQPseudo, ARM::VST1d16Q, false, false, false, SingleHighQSpc, 4, 4 ,false},
406 { ARM::VST1q16HighQPseudo_UPD, ARM::VST1d16Qwb_fixed, false, true, true, SingleHighQSpc, 4, 8 ,…
407 { ARM::VST1q16HighTPseudo, ARM::VST1d16T, false, false, false, SingleHighTSpc, 3, 4 ,false},
408 { ARM::VST1q16HighTPseudo_UPD, ARM::VST1d16Twb_fixed, false, true, true, SingleHighTSpc, 3, 4 ,…
409 { ARM::VST1q16LowQPseudo_UPD, ARM::VST1d16Qwb_fixed, false, true, true, SingleLowSpc, 4, 4 ,fa…
410 { ARM::VST1q16LowTPseudo_UPD, ARM::VST1d16Twb_fixed, false, true, true, SingleLowSpc, 3, 4 ,fa…
412 { ARM::VST1q32HighQPseudo, ARM::VST1d32Q, false, false, false, SingleHighQSpc, 4, 2 ,false},
413 { ARM::VST1q32HighQPseudo_UPD, ARM::VST1d32Qwb_fixed, false, true, true, SingleHighQSpc, 4, 8 ,…
414 { ARM::VST1q32HighTPseudo, ARM::VST1d32T, false, false, false, SingleHighTSpc, 3, 2 ,false},
415 { ARM::VST1q32HighTPseudo_UPD, ARM::VST1d32Twb_fixed, false, true, true, SingleHighTSpc, 3, 2 ,…
416 { ARM::VST1q32LowQPseudo_UPD, ARM::VST1d32Qwb_fixed, false, true, true, SingleLowSpc, 4, 2 ,fa…
417 { ARM::VST1q32LowTPseudo_UPD, ARM::VST1d32Twb_fixed, false, true, true, SingleLowSpc, 3, 2 ,fa…
419 { ARM::VST1q64HighQPseudo, ARM::VST1d64Q, false, false, false, SingleHighQSpc, 4, 1 ,false},
420 { ARM::VST1q64HighQPseudo_UPD, ARM::VST1d64Qwb_fixed, false, true, true, SingleHighQSpc, 4, 8 ,…
421 { ARM::VST1q64HighTPseudo, ARM::VST1d64T, false, false, false, SingleHighTSpc, 3, 1 ,false},
422 { ARM::VST1q64HighTPseudo_UPD, ARM::VST1d64Twb_fixed, false, true, true, SingleHighTSpc, 3, 1 ,…
423 { ARM::VST1q64LowQPseudo_UPD, ARM::VST1d64Qwb_fixed, false, true, true, SingleLowSpc, 4, 1 ,fa…
424 { ARM::VST1q64LowTPseudo_UPD, ARM::VST1d64Twb_fixed, false, true, true, SingleLowSpc, 3, 1 ,fa…
426 { ARM::VST1q8HighQPseudo, ARM::VST1d8Q, false, false, false, SingleHighQSpc, 4, 8 ,false},
427 { ARM::VST1q8HighQPseudo_UPD, ARM::VST1d8Qwb_fixed, false, true, true, SingleHighQSpc, 4, 8 ,fa…
428 { ARM::VST1q8HighTPseudo, ARM::VST1d8T, false, false, false, SingleHighTSpc, 3, 8 ,false},
429 { ARM::VST1q8HighTPseudo_UPD, ARM::VST1d8Twb_fixed, false, true, true, SingleHighTSpc, 3, 8 ,fa…
430 { ARM::VST1q8LowQPseudo_UPD, ARM::VST1d8Qwb_fixed, false, true, true, SingleLowSpc, 4, 8 ,fals…
431 { ARM::VST1q8LowTPseudo_UPD, ARM::VST1d8Twb_fixed, false, true, true, SingleLowSpc, 3, 8 ,fals…
433 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true},
434 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true},
435 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true},
436 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true},
437 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true},
438 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true},
439 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true},
440 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true},
441 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true},
442 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true},
444 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false},
445 { ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false},
446 { ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,f…
447 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false},
448 { ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false},
449 { ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,f…
450 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false},
451 { ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false},
452 { ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,fa…
454 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true},
455 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
456 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true},
457 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
458 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true},
459 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
460 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true},
461 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true},
462 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true},
463 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true},
465 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true},
466 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
467 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true},
468 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
469 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true},
470 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
472 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true},
473 { ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true},
474 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true},
475 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true},
476 { ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true},
477 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true},
478 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true},
479 { ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true},
480 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true},
482 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true},
483 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
484 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true},
485 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
486 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true},
487 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
488 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true},
489 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true},
490 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true},
491 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true},
493 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true},
494 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
495 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true},
496 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
497 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true},
498 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
500 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true},
501 { ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true},
502 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true},
503 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true},
504 { ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true},
505 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true},
506 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true},
507 { ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true},
508 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true}
536 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs()
537 D1 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs()
538 D2 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs()
539 D3 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
541 D0 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
542 D1 = TRI->getSubReg(Reg, ARM::dsub_5); in GetDSubRegs()
543 D2 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
544 D3 = TRI->getSubReg(Reg, ARM::dsub_7); in GetDSubRegs()
546 D0 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
547 D1 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
548 D2 = TRI->getSubReg(Reg, ARM::dsub_5); in GetDSubRegs()
549 D3 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
551 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs()
552 D1 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs()
553 D2 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
554 D3 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
557 D0 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs()
558 D1 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
559 D2 = TRI->getSubReg(Reg, ARM::dsub_5); in GetDSubRegs()
560 D3 = TRI->getSubReg(Reg, ARM::dsub_7); in GetDSubRegs()
583 bool IsVLD2DUP = TableEntry->RealOpc == ARM::VLD2DUPd8x2 || in ExpandVLD()
584 TableEntry->RealOpc == ARM::VLD2DUPd16x2 || in ExpandVLD()
585 TableEntry->RealOpc == ARM::VLD2DUPd32x2 || in ExpandVLD()
586 TableEntry->RealOpc == ARM::VLD2DUPd8x2wb_fixed || in ExpandVLD()
587 TableEntry->RealOpc == ARM::VLD2DUPd16x2wb_fixed || in ExpandVLD()
588 TableEntry->RealOpc == ARM::VLD2DUPd32x2wb_fixed || in ExpandVLD()
589 TableEntry->RealOpc == ARM::VLD2DUPd8x2wb_register || in ExpandVLD()
590 TableEntry->RealOpc == ARM::VLD2DUPd16x2wb_register || in ExpandVLD()
591 TableEntry->RealOpc == ARM::VLD2DUPd32x2wb_register; in ExpandVLD()
596 SubRegIndex = ARM::dsub_0; in ExpandVLD()
599 SubRegIndex = ARM::dsub_1; in ExpandVLD()
602 unsigned DstRegPair = TRI->getMatchingSuperReg(SubReg, ARM::dsub_0, in ExpandVLD()
603 &ARM::DPairSpcRegClass); in ExpandVLD()
634 if (TableEntry->RealOpc == ARM::VLD1d8Qwb_fixed || in ExpandVLD()
635 TableEntry->RealOpc == ARM::VLD1d16Qwb_fixed || in ExpandVLD()
636 TableEntry->RealOpc == ARM::VLD1d32Qwb_fixed || in ExpandVLD()
637 TableEntry->RealOpc == ARM::VLD1d64Qwb_fixed || in ExpandVLD()
638 TableEntry->RealOpc == ARM::VLD1d8Twb_fixed || in ExpandVLD()
639 TableEntry->RealOpc == ARM::VLD1d16Twb_fixed || in ExpandVLD()
640 TableEntry->RealOpc == ARM::VLD1d32Twb_fixed || in ExpandVLD()
641 TableEntry->RealOpc == ARM::VLD1d64Twb_fixed || in ExpandVLD()
642 TableEntry->RealOpc == ARM::VLD2DUPd8x2wb_fixed || in ExpandVLD()
643 TableEntry->RealOpc == ARM::VLD2DUPd16x2wb_fixed || in ExpandVLD()
644 TableEntry->RealOpc == ARM::VLD2DUPd32x2wb_fixed) { in ExpandVLD()
716 if (TableEntry->RealOpc == ARM::VST1d8Qwb_fixed || in ExpandVST()
717 TableEntry->RealOpc == ARM::VST1d16Qwb_fixed || in ExpandVST()
718 TableEntry->RealOpc == ARM::VST1d32Qwb_fixed || in ExpandVST()
719 TableEntry->RealOpc == ARM::VST1d64Qwb_fixed || in ExpandVST()
720 TableEntry->RealOpc == ARM::VST1d8Twb_fixed || in ExpandVST()
721 TableEntry->RealOpc == ARM::VST1d16Twb_fixed || in ExpandVST()
722 TableEntry->RealOpc == ARM::VST1d32Twb_fixed || in ExpandVST()
723 TableEntry->RealOpc == ARM::VST1d64Twb_fixed) { in ExpandVST()
941 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm; in ExpandMOV32BitImm()
948 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) { in ExpandMOV32BitImm()
957 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); in ExpandMOV32BitImm()
958 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri)) in ExpandMOV32BitImm()
964 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MVNi), DstReg); in ExpandMOV32BitImm()
965 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri)) in ExpandMOV32BitImm()
992 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) { in ExpandMOV32BitImm()
993 LO16Opc = ARM::t2MOVi16; in ExpandMOV32BitImm()
994 HI16Opc = ARM::t2MOVTi16; in ExpandMOV32BitImm()
996 LO16Opc = ARM::MOVi16; in ExpandMOV32BitImm()
997 HI16Opc = ARM::MOVTi16; in ExpandMOV32BitImm()
1076 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2CLRM)).add(predOps(ARMCC::AL)); in CMSEClearGPRegs()
1079 CLRM.addReg(ARM::APSR, RegState::Define); in CMSEClearGPRegs()
1080 CLRM.addReg(ARM::CPSR, RegState::Define | RegState::Implicit); in CMSEClearGPRegs()
1087 BuildMI(MBB, MBBI, DL, TII->get(ARM::tMOVr), Reg) in CMSEClearGPRegs()
1092 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2MSR_M)) in CMSEClearGPRegs()
1112 if ((Reg >= ARM::Q0 && Reg <= ARM::Q7) || in determineFPRegsToClear()
1113 (Reg >= ARM::D0 && Reg <= ARM::D15) || in determineFPRegsToClear()
1114 (Reg >= ARM::S0 && Reg <= ARM::S31)) in determineFPRegsToClear()
1119 if (Reg >= ARM::Q0 && Reg <= ARM::Q7) { in determineFPRegsToClear()
1120 int R = Reg - ARM::Q0; in determineFPRegsToClear()
1122 } else if (Reg >= ARM::D0 && Reg <= ARM::D15) { in determineFPRegsToClear()
1123 int R = Reg - ARM::D0; in determineFPRegsToClear()
1125 } else if (Reg >= ARM::S0 && Reg <= ARM::S31) { in determineFPRegsToClear()
1126 ClearRegs[Reg - ARM::S0] = false; in determineFPRegsToClear()
1182 if (Reg == ARM::NoRegister || Reg == ARM::LR) in CMSEClearFPRegsV8()
1188 ClearBB->addLiveIn(ARM::LR); in CMSEClearFPRegsV8()
1189 DoneBB->addLiveIn(ARM::LR); in CMSEClearFPRegsV8()
1192 BuildMI(MBB, MBB.end(), DL, TII->get(ARM::t2MRS_M), ARM::R12) in CMSEClearFPRegsV8()
1196 BuildMI(MBB, MBB.end(), DL, TII->get(ARM::t2TSTri)) in CMSEClearFPRegsV8()
1197 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1201 BuildMI(MBB, MBB.end(), DL, TII->get(ARM::tBcc)) in CMSEClearFPRegsV8()
1204 .addReg(ARM::CPSR, RegState::Kill); in CMSEClearFPRegsV8()
1211 unsigned Reg = ARM::D0 + D; in CMSEClearFPRegsV8()
1212 BuildMI(ClearBB, DL, TII->get(ARM::VMOVDRR), Reg) in CMSEClearFPRegsV8()
1213 .addReg(ARM::LR) in CMSEClearFPRegsV8()
1214 .addReg(ARM::LR) in CMSEClearFPRegsV8()
1219 unsigned Reg = ARM::S0 + D * 2; in CMSEClearFPRegsV8()
1220 BuildMI(ClearBB, DL, TII->get(ARM::VMOVSR), Reg) in CMSEClearFPRegsV8()
1221 .addReg(ARM::LR) in CMSEClearFPRegsV8()
1226 unsigned Reg = ARM::S0 + D * 2 + 1; in CMSEClearFPRegsV8()
1227 BuildMI(ClearBB, DL, TII->get(ARM::VMOVSR), Reg) in CMSEClearFPRegsV8()
1228 .addReg(ARM::LR) in CMSEClearFPRegsV8()
1236 BuildMI(ClearBB, DL, TII->get(ARM::VMRS), ARM::R12) in CMSEClearFPRegsV8()
1238 BuildMI(ClearBB, DL, TII->get(ARM::t2BICri), ARM::R12) in CMSEClearFPRegsV8()
1239 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1243 BuildMI(ClearBB, DL, TII->get(ARM::t2BICri), ARM::R12) in CMSEClearFPRegsV8()
1244 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1248 BuildMI(ClearBB, DL, TII->get(ARM::VMSR)) in CMSEClearFPRegsV8()
1249 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1272 BuildMI(MBB, MBBI, RetI.getDebugLoc(), TII->get(ARM::VSCCLRMS)) in CMSEClearFPRegsV81()
1275 VSCCLRM.addReg(ARM::S0 + Start, RegState::Define); in CMSEClearFPRegsV81()
1276 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1283 BuildMI(MBB, MBBI, RetI.getDebugLoc(), TII->get(ARM::VSCCLRMS)) in CMSEClearFPRegsV81()
1286 VSCCLRM.addReg(ARM::S0 + Start, RegState::Define); in CMSEClearFPRegsV81()
1287 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1314 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBspi), ARM::SP) in CMSESaveClearFPRegsV8()
1315 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1325 assert(!ARM::DPRRegClass.contains(Reg) || in CMSESaveClearFPRegsV8()
1326 ARM::DPR_VFP2RegClass.contains(Reg)); in CMSESaveClearFPRegsV8()
1327 assert(!ARM::QPRRegClass.contains(Reg)); in CMSESaveClearFPRegsV8()
1328 if (ARM::DPR_VFP2RegClass.contains(Reg)) { in CMSESaveClearFPRegsV8()
1335 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRRD)) in CMSESaveClearFPRegsV8()
1343 } else if (ARM::SPRRegClass.contains(Reg)) { in CMSESaveClearFPRegsV8()
1349 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRS), SaveReg) in CMSESaveClearFPRegsV8()
1362 MachineInstrBuilder VLSTM = BuildMI(MBB, MBBI, DL, TII->get(ARM::VLSTM)) in CMSESaveClearFPRegsV8()
1363 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1365 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, in CMSESaveClearFPRegsV8()
1366 ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7}) in CMSESaveClearFPRegsV8()
1374 if (ARM::DPR_VFP2RegClass.contains(Reg)) in CMSESaveClearFPRegsV8()
1375 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg) in CMSESaveClearFPRegsV8()
1379 else if (ARM::SPRRegClass.contains(Reg)) in CMSESaveClearFPRegsV8()
1380 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVSR), Reg) in CMSESaveClearFPRegsV8()
1386 if (ARM::DPR_VFP2RegClass.contains(Reg)) { in CMSESaveClearFPRegsV8()
1388 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRD), Reg) in CMSESaveClearFPRegsV8()
1389 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1390 .addImm((Reg - ARM::D0) * 2) in CMSESaveClearFPRegsV8()
1395 unsigned SReg0 = TRI->getSubReg(Reg, ARM::ssub_0); in CMSESaveClearFPRegsV8()
1396 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), SReg0) in CMSESaveClearFPRegsV8()
1397 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1398 .addImm((Reg - ARM::D0) * 2) in CMSESaveClearFPRegsV8()
1400 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), SReg0 + 1) in CMSESaveClearFPRegsV8()
1401 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1402 .addImm((Reg - ARM::D0) * 2 + 1) in CMSESaveClearFPRegsV8()
1405 } else if (ARM::SPRRegClass.contains(Reg)) { in CMSESaveClearFPRegsV8()
1406 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), Reg) in CMSESaveClearFPRegsV8()
1407 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1408 .addImm(Reg - ARM::S0) in CMSESaveClearFPRegsV8()
1415 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2LDRi8), SpareReg) in CMSESaveClearFPRegsV8()
1416 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1419 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), SpareReg) in CMSESaveClearFPRegsV8()
1424 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), SpareReg) in CMSESaveClearFPRegsV8()
1429 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMSR)) in CMSESaveClearFPRegsV8()
1450 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBspi), ARM::SP) in CMSESaveClearFPRegsV81()
1451 .addReg(ARM::SP) in CMSESaveClearFPRegsV81()
1456 MachineInstrBuilder VLSTM = BuildMI(MBB, MBBI, DL, TII->get(ARM::VLSTM)) in CMSESaveClearFPRegsV81()
1457 .addReg(ARM::SP) in CMSESaveClearFPRegsV81()
1459 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, in CMSESaveClearFPRegsV81()
1460 ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7}) in CMSESaveClearFPRegsV81()
1466 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTMSDB_UPD), ARM::SP) in CMSESaveClearFPRegsV81()
1467 .addReg(ARM::SP) in CMSESaveClearFPRegsV81()
1469 for (int Reg = ARM::S16; Reg <= ARM::S31; ++Reg) in CMSESaveClearFPRegsV81()
1476 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTR_FPCXTS_pre), ARM::SP) in CMSESaveClearFPRegsV81()
1477 .addReg(ARM::SP) in CMSESaveClearFPRegsV81()
1505 assert(!ARM::DPRRegClass.contains(Reg) || in CMSERestoreFPRegsV8()
1506 ARM::DPR_VFP2RegClass.contains(Reg)); in CMSERestoreFPRegsV8()
1507 assert(!ARM::QPRRegClass.contains(Reg)); in CMSERestoreFPRegsV8()
1508 if (ARM::DPR_VFP2RegClass.contains(Reg)) { in CMSERestoreFPRegsV8()
1515 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRRD)) in CMSERestoreFPRegsV8()
1523 } else if (ARM::SPRRegClass.contains(Reg)) { in CMSERestoreFPRegsV8()
1529 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRS), SaveReg) in CMSERestoreFPRegsV8()
1541 if (ARM::DPR_VFP2RegClass.contains(Reg)) in CMSERestoreFPRegsV8()
1542 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTRD), Reg) in CMSERestoreFPRegsV8()
1543 .addReg(ARM::SP) in CMSERestoreFPRegsV8()
1544 .addImm((Reg - ARM::D0) * 2) in CMSERestoreFPRegsV8()
1546 else if (ARM::SPRRegClass.contains(Reg)) in CMSERestoreFPRegsV8()
1547 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTRS), Reg) in CMSERestoreFPRegsV8()
1548 .addReg(ARM::SP) in CMSERestoreFPRegsV8()
1549 .addImm(Reg - ARM::S0) in CMSERestoreFPRegsV8()
1554 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLLDM)) in CMSERestoreFPRegsV8()
1555 .addReg(ARM::SP) in CMSERestoreFPRegsV8()
1562 if (ARM::DPR_VFP2RegClass.contains(Reg)) in CMSERestoreFPRegsV8()
1563 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg) in CMSERestoreFPRegsV8()
1567 else if (ARM::SPRRegClass.contains(Reg)) in CMSERestoreFPRegsV8()
1568 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVSR), Reg) in CMSERestoreFPRegsV8()
1574 BuildMI(MBB, MBBI, DL, TII->get(ARM::tADDspi), ARM::SP) in CMSERestoreFPRegsV8()
1575 .addReg(ARM::SP) in CMSERestoreFPRegsV8()
1585 if ((Reg >= ARM::Q0 && Reg <= ARM::Q7) || in definesOrUsesFPReg()
1586 (Reg >= ARM::D0 && Reg <= ARM::D15) || in definesOrUsesFPReg()
1587 (Reg >= ARM::S0 && Reg <= ARM::S31)) in definesOrUsesFPReg()
1598 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLLDM)) in CMSERestoreFPRegsV81()
1599 .addReg(ARM::SP) in CMSERestoreFPRegsV81()
1603 BuildMI(MBB, MBBI, DL, TII->get(ARM::tADDspi), ARM::SP) in CMSERestoreFPRegsV81()
1604 .addReg(ARM::SP) in CMSERestoreFPRegsV81()
1609 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(ARM::VLDR_FPCXTS_post), in CMSERestoreFPRegsV81()
1610 ARM::SP) in CMSERestoreFPRegsV81()
1611 .addReg(ARM::SP) in CMSERestoreFPRegsV81()
1617 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDMSIA_UPD), ARM::SP) in CMSERestoreFPRegsV81()
1618 .addReg(ARM::SP) in CMSERestoreFPRegsV81()
1620 for (int Reg = ARM::S16; Reg <= ARM::S31; ++Reg) in CMSERestoreFPRegsV81()
1648 assert((UxtOp == 0 || UxtOp == ARM::tUXTB || UxtOp == ARM::tUXTH) && in ExpandCMP_SWAP()
1650 assert((UxtOp == 0 || ARM::tGPRRegClass.contains(DesiredReg)) && in ExpandCMP_SWAP()
1680 if (LdrexOp == ARM::t2LDREX) in ExpandCMP_SWAP()
1684 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr; in ExpandCMP_SWAP()
1689 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc; in ExpandCMP_SWAP()
1693 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
1704 if (StrexOp == ARM::t2STREX) in ExpandCMP_SWAP()
1708 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri; in ExpandCMP_SWAP()
1716 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
1749 Register RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0); in addExclusiveRegPair()
1750 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair()
1774 Register DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0); in ExpandCMP_SWAP_64()
1775 Register DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1); in ExpandCMP_SWAP_64()
1776 Register DesiredLo = TRI->getSubReg(DesiredReg, ARM::gsub_0); in ExpandCMP_SWAP_64()
1777 Register DesiredHi = TRI->getSubReg(DesiredReg, ARM::gsub_1); in ExpandCMP_SWAP_64()
1793 unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD; in ExpandCMP_SWAP_64()
1799 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr; in ExpandCMP_SWAP_64()
1808 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1810 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc; in ExpandCMP_SWAP_64()
1814 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1822 unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD; in ExpandCMP_SWAP_64()
1828 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri; in ExpandCMP_SWAP_64()
1836 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1869 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL)); in CMSEPushCalleeSaves()
1870 for (int Reg = ARM::R4; Reg < ARM::R8; ++Reg) { in CMSEPushCalleeSaves()
1882 for (int LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4; --LoReg) { in CMSEPushCalleeSaves()
1885 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg) in CMSEPushCalleeSaves()
1891 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL)); in CMSEPushCalleeSaves()
1892 for (int Reg = ARM::R4; Reg < ARM::R8; ++Reg) { in CMSEPushCalleeSaves()
1901 if (JumpReg >= ARM::R4 && JumpReg <= ARM::R7) { in CMSEPushCalleeSaves()
1902 int LoReg = JumpReg == ARM::R4 ? ARM::R5 : ARM::R4; in CMSEPushCalleeSaves()
1903 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg) in CMSEPushCalleeSaves()
1904 .addReg(ARM::R8, LiveRegs.contains(ARM::R8) ? 0 : RegState::Undef) in CMSEPushCalleeSaves()
1906 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)) in CMSEPushCalleeSaves()
1912 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2STMDB_UPD), ARM::SP) in CMSEPushCalleeSaves()
1913 .addReg(ARM::SP) in CMSEPushCalleeSaves()
1915 for (int Reg = ARM::R4; Reg < ARM::R12; ++Reg) { in CMSEPushCalleeSaves()
1929 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL)); in CMSEPopCalleeSaves()
1931 PopMIB.addReg(ARM::R4 + R, RegState::Define); in CMSEPopCalleeSaves()
1932 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), ARM::R8 + R) in CMSEPopCalleeSaves()
1933 .addReg(ARM::R4 + R, RegState::Kill) in CMSEPopCalleeSaves()
1937 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL)); in CMSEPopCalleeSaves()
1939 PopMIB2.addReg(ARM::R4 + R, RegState::Define); in CMSEPopCalleeSaves()
1942 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2LDMIA_UPD), ARM::SP) in CMSEPopCalleeSaves()
1943 .addReg(ARM::SP) in CMSEPopCalleeSaves()
1945 for (int Reg = ARM::R4; Reg < ARM::R12; ++Reg) in CMSEPopCalleeSaves()
1959 case ARM::VBSPd: in ExpandMI()
1960 case ARM::VBSPq: { in ExpandMI()
1964 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBITd : ARM::VBITq; in ExpandMI()
1974 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBIFd : ARM::VBIFq; in ExpandMI()
1984 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBSLd : ARM::VBSLq; in ExpandMI()
1995 unsigned MoveOpc = Opcode == ARM::VBSPd ? ARM::VORRd : ARM::VORRq; in ExpandMI()
2019 case ARM::TCRETURNdi: in ExpandMI()
2020 case ARM::TCRETURNri: { in ExpandMI()
2034 if (RetOpcode == ARM::TCRETURNdi) { in ExpandMI()
2037 ? (STI->isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) in ExpandMI()
2038 : ARM::TAILJMPd; in ExpandMI()
2052 } else if (RetOpcode == ARM::TCRETURNri) { in ExpandMI()
2054 STI->isThumb() ? ARM::tTAILJMPr in ExpandMI()
2055 : (STI->hasV4TOps() ? ARM::TAILJMPr : ARM::TAILJMPr4); in ExpandMI()
2074 case ARM::tBXNS_RET: { in ExpandMI()
2080 TII->get(ARM::VLDR_FPCXTNS_post), ARM::SP) in ExpandMI()
2081 .addReg(ARM::SP) in ExpandMI()
2088 return !Op.isReg() || Op.getReg() != ARM::R12; in ExpandMI()
2092 *MBBI, {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12}, ClearRegs); in ExpandMI()
2094 ARM::LR); in ExpandMI()
2098 TII->get(ARM::tBXNS)) in ExpandMI()
2099 .addReg(ARM::LR) in ExpandMI()
2106 case ARM::tBLXNS_CALL: { in ExpandMI()
2125 {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, in ExpandMI()
2126 ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, in ExpandMI()
2127 ARM::R10, ARM::R11, ARM::R12}, in ExpandMI()
2137 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), JumpReg) in ExpandMI()
2146 BuildMI(MBB, MBBI, DL, TII->get(ARM::tMOVi8), ScratchReg) in ExpandMI()
2150 BuildMI(MBB, MBBI, DL, TII->get(ARM::tBIC), JumpReg) in ExpandMI()
2151 .addReg(ARM::CPSR, RegState::Define) in ExpandMI()
2162 BuildMI(MBB, MBBI, DL, TII->get(ARM::tBLXNSr)) in ExpandMI()
2178 case ARM::VMOVHcc: in ExpandMI()
2179 case ARM::VMOVScc: in ExpandMI()
2180 case ARM::VMOVDcc: { in ExpandMI()
2181 unsigned newOpc = Opcode != ARM::VMOVDcc ? ARM::VMOVS : ARM::VMOVD; in ExpandMI()
2192 case ARM::t2MOVCCr: in ExpandMI()
2193 case ARM::MOVCCr: { in ExpandMI()
2194 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr; in ExpandMI()
2206 case ARM::MOVCCsi: { in ExpandMI()
2207 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), in ExpandMI()
2219 case ARM::MOVCCsr: { in ExpandMI()
2220 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr), in ExpandMI()
2233 case ARM::t2MOVCCi16: in ExpandMI()
2234 case ARM::MOVCCi16: { in ExpandMI()
2235 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16; in ExpandMI()
2245 case ARM::t2MOVCCi: in ExpandMI()
2246 case ARM::MOVCCi: { in ExpandMI()
2247 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi; in ExpandMI()
2259 case ARM::t2MVNCCi: in ExpandMI()
2260 case ARM::MVNCCi: { in ExpandMI()
2261 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi; in ExpandMI()
2273 case ARM::t2MOVCClsl: in ExpandMI()
2274 case ARM::t2MOVCClsr: in ExpandMI()
2275 case ARM::t2MOVCCasr: in ExpandMI()
2276 case ARM::t2MOVCCror: { in ExpandMI()
2279 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break; in ExpandMI()
2280 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break; in ExpandMI()
2281 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break; in ExpandMI()
2282 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break; in ExpandMI()
2296 case ARM::Int_eh_sjlj_dispatchsetup: { in ExpandMI()
2311 emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, in ExpandMI()
2314 emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, in ExpandMI()
2317 emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, in ExpandMI()
2332 ARM::t2BICri : ARM::BICri; in ExpandMI()
2333 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(bicOpc), ARM::R6) in ExpandMI()
2334 .addReg(ARM::R6, RegState::Kill) in ExpandMI()
2344 case ARM::MOVsrl_flag: in ExpandMI()
2345 case ARM::MOVsra_flag: { in ExpandMI()
2347 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), in ExpandMI()
2351 (Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr : ARM_AM::asr), 1)) in ExpandMI()
2353 .addReg(ARM::CPSR, RegState::Define); in ExpandMI()
2357 case ARM::RRX: { in ExpandMI()
2360 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), in ExpandMI()
2370 case ARM::tTPsoft: in ExpandMI()
2371 case ARM::TPsoft: { in ExpandMI()
2372 const bool Thumb = Opcode == ARM::tTPsoft; in ExpandMI()
2385 TII->get(Thumb ? ARM::tLDRpci : ARM::LDRi12), Reg) in ExpandMI()
2399 TII->get(Thumb ? ARM::tBL : ARM::BL)); in ExpandMI()
2413 case ARM::tLDRpci_pic: in ExpandMI()
2414 case ARM::t2LDRpci_pic: { in ExpandMI()
2415 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic) in ExpandMI()
2416 ? ARM::tLDRpci : ARM::t2LDRpci; in ExpandMI()
2425 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPICADD)) in ExpandMI()
2434 case ARM::LDRLIT_ga_abs: in ExpandMI()
2435 case ARM::LDRLIT_ga_pcrel: in ExpandMI()
2436 case ARM::LDRLIT_ga_pcrel_ldr: in ExpandMI()
2437 case ARM::tLDRLIT_ga_abs: in ExpandMI()
2438 case ARM::tLDRLIT_ga_pcrel: { in ExpandMI()
2445 Opcode != ARM::tLDRLIT_ga_pcrel && Opcode != ARM::tLDRLIT_ga_abs; in ExpandMI()
2447 Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs; in ExpandMI()
2448 unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci; in ExpandMI()
2451 ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) in ExpandMI()
2452 : ARM::tPICADD; in ExpandMI()
2492 case ARM::MOV_ga_pcrel: in ExpandMI()
2493 case ARM::MOV_ga_pcrel_ldr: in ExpandMI()
2494 case ARM::t2MOV_ga_pcrel: { in ExpandMI()
2502 bool isARM = Opcode != ARM::t2MOV_ga_pcrel; in ExpandMI()
2503 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel; in ExpandMI()
2504 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel; in ExpandMI()
2508 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) in ExpandMI()
2509 : ARM::tPICADD; in ExpandMI()
2526 if (Opcode == ARM::MOV_ga_pcrel_ldr) in ExpandMI()
2534 case ARM::MOVi32imm: in ExpandMI()
2535 case ARM::MOVCCi32imm: in ExpandMI()
2536 case ARM::t2MOVi32imm: in ExpandMI()
2537 case ARM::t2MOVCCi32imm: in ExpandMI()
2541 case ARM::SUBS_PC_LR: { in ExpandMI()
2543 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC) in ExpandMI()
2544 .addReg(ARM::LR) in ExpandMI()
2548 .addReg(ARM::CPSR, RegState::Undef); in ExpandMI()
2553 case ARM::VLDMQIA: { in ExpandMI()
2554 unsigned NewOpc = ARM::VLDMDIA; in ExpandMI()
2571 Register D0 = TRI->getSubReg(DstReg, ARM::dsub_0); in ExpandMI()
2572 Register D1 = TRI->getSubReg(DstReg, ARM::dsub_1); in ExpandMI()
2584 case ARM::VSTMQIA: { in ExpandMI()
2585 unsigned NewOpc = ARM::VSTMDIA; in ExpandMI()
2603 Register D0 = TRI->getSubReg(SrcReg, ARM::dsub_0); in ExpandMI()
2604 Register D1 = TRI->getSubReg(SrcReg, ARM::dsub_1); in ExpandMI()
2617 case ARM::VLD2q8Pseudo: in ExpandMI()
2618 case ARM::VLD2q16Pseudo: in ExpandMI()
2619 case ARM::VLD2q32Pseudo: in ExpandMI()
2620 case ARM::VLD2q8PseudoWB_fixed: in ExpandMI()
2621 case ARM::VLD2q16PseudoWB_fixed: in ExpandMI()
2622 case ARM::VLD2q32PseudoWB_fixed: in ExpandMI()
2623 case ARM::VLD2q8PseudoWB_register: in ExpandMI()
2624 case ARM::VLD2q16PseudoWB_register: in ExpandMI()
2625 case ARM::VLD2q32PseudoWB_register: in ExpandMI()
2626 case ARM::VLD3d8Pseudo: in ExpandMI()
2627 case ARM::VLD3d16Pseudo: in ExpandMI()
2628 case ARM::VLD3d32Pseudo: in ExpandMI()
2629 case ARM::VLD1d8TPseudo: in ExpandMI()
2630 case ARM::VLD1d8TPseudoWB_fixed: in ExpandMI()
2631 case ARM::VLD1d8TPseudoWB_register: in ExpandMI()
2632 case ARM::VLD1d16TPseudo: in ExpandMI()
2633 case ARM::VLD1d16TPseudoWB_fixed: in ExpandMI()
2634 case ARM::VLD1d16TPseudoWB_register: in ExpandMI()
2635 case ARM::VLD1d32TPseudo: in ExpandMI()
2636 case ARM::VLD1d32TPseudoWB_fixed: in ExpandMI()
2637 case ARM::VLD1d32TPseudoWB_register: in ExpandMI()
2638 case ARM::VLD1d64TPseudo: in ExpandMI()
2639 case ARM::VLD1d64TPseudoWB_fixed: in ExpandMI()
2640 case ARM::VLD1d64TPseudoWB_register: in ExpandMI()
2641 case ARM::VLD3d8Pseudo_UPD: in ExpandMI()
2642 case ARM::VLD3d16Pseudo_UPD: in ExpandMI()
2643 case ARM::VLD3d32Pseudo_UPD: in ExpandMI()
2644 case ARM::VLD3q8Pseudo_UPD: in ExpandMI()
2645 case ARM::VLD3q16Pseudo_UPD: in ExpandMI()
2646 case ARM::VLD3q32Pseudo_UPD: in ExpandMI()
2647 case ARM::VLD3q8oddPseudo: in ExpandMI()
2648 case ARM::VLD3q16oddPseudo: in ExpandMI()
2649 case ARM::VLD3q32oddPseudo: in ExpandMI()
2650 case ARM::VLD3q8oddPseudo_UPD: in ExpandMI()
2651 case ARM::VLD3q16oddPseudo_UPD: in ExpandMI()
2652 case ARM::VLD3q32oddPseudo_UPD: in ExpandMI()
2653 case ARM::VLD4d8Pseudo: in ExpandMI()
2654 case ARM::VLD4d16Pseudo: in ExpandMI()
2655 case ARM::VLD4d32Pseudo: in ExpandMI()
2656 case ARM::VLD1d8QPseudo: in ExpandMI()
2657 case ARM::VLD1d8QPseudoWB_fixed: in ExpandMI()
2658 case ARM::VLD1d8QPseudoWB_register: in ExpandMI()
2659 case ARM::VLD1d16QPseudo: in ExpandMI()
2660 case ARM::VLD1d16QPseudoWB_fixed: in ExpandMI()
2661 case ARM::VLD1d16QPseudoWB_register: in ExpandMI()
2662 case ARM::VLD1d32QPseudo: in ExpandMI()
2663 case ARM::VLD1d32QPseudoWB_fixed: in ExpandMI()
2664 case ARM::VLD1d32QPseudoWB_register: in ExpandMI()
2665 case ARM::VLD1d64QPseudo: in ExpandMI()
2666 case ARM::VLD1d64QPseudoWB_fixed: in ExpandMI()
2667 case ARM::VLD1d64QPseudoWB_register: in ExpandMI()
2668 case ARM::VLD1q8HighQPseudo: in ExpandMI()
2669 case ARM::VLD1q8HighQPseudo_UPD: in ExpandMI()
2670 case ARM::VLD1q8LowQPseudo_UPD: in ExpandMI()
2671 case ARM::VLD1q8HighTPseudo: in ExpandMI()
2672 case ARM::VLD1q8HighTPseudo_UPD: in ExpandMI()
2673 case ARM::VLD1q8LowTPseudo_UPD: in ExpandMI()
2674 case ARM::VLD1q16HighQPseudo: in ExpandMI()
2675 case ARM::VLD1q16HighQPseudo_UPD: in ExpandMI()
2676 case ARM::VLD1q16LowQPseudo_UPD: in ExpandMI()
2677 case ARM::VLD1q16HighTPseudo: in ExpandMI()
2678 case ARM::VLD1q16HighTPseudo_UPD: in ExpandMI()
2679 case ARM::VLD1q16LowTPseudo_UPD: in ExpandMI()
2680 case ARM::VLD1q32HighQPseudo: in ExpandMI()
2681 case ARM::VLD1q32HighQPseudo_UPD: in ExpandMI()
2682 case ARM::VLD1q32LowQPseudo_UPD: in ExpandMI()
2683 case ARM::VLD1q32HighTPseudo: in ExpandMI()
2684 case ARM::VLD1q32HighTPseudo_UPD: in ExpandMI()
2685 case ARM::VLD1q32LowTPseudo_UPD: in ExpandMI()
2686 case ARM::VLD1q64HighQPseudo: in ExpandMI()
2687 case ARM::VLD1q64HighQPseudo_UPD: in ExpandMI()
2688 case ARM::VLD1q64LowQPseudo_UPD: in ExpandMI()
2689 case ARM::VLD1q64HighTPseudo: in ExpandMI()
2690 case ARM::VLD1q64HighTPseudo_UPD: in ExpandMI()
2691 case ARM::VLD1q64LowTPseudo_UPD: in ExpandMI()
2692 case ARM::VLD4d8Pseudo_UPD: in ExpandMI()
2693 case ARM::VLD4d16Pseudo_UPD: in ExpandMI()
2694 case ARM::VLD4d32Pseudo_UPD: in ExpandMI()
2695 case ARM::VLD4q8Pseudo_UPD: in ExpandMI()
2696 case ARM::VLD4q16Pseudo_UPD: in ExpandMI()
2697 case ARM::VLD4q32Pseudo_UPD: in ExpandMI()
2698 case ARM::VLD4q8oddPseudo: in ExpandMI()
2699 case ARM::VLD4q16oddPseudo: in ExpandMI()
2700 case ARM::VLD4q32oddPseudo: in ExpandMI()
2701 case ARM::VLD4q8oddPseudo_UPD: in ExpandMI()
2702 case ARM::VLD4q16oddPseudo_UPD: in ExpandMI()
2703 case ARM::VLD4q32oddPseudo_UPD: in ExpandMI()
2704 case ARM::VLD3DUPd8Pseudo: in ExpandMI()
2705 case ARM::VLD3DUPd16Pseudo: in ExpandMI()
2706 case ARM::VLD3DUPd32Pseudo: in ExpandMI()
2707 case ARM::VLD3DUPd8Pseudo_UPD: in ExpandMI()
2708 case ARM::VLD3DUPd16Pseudo_UPD: in ExpandMI()
2709 case ARM::VLD3DUPd32Pseudo_UPD: in ExpandMI()
2710 case ARM::VLD4DUPd8Pseudo: in ExpandMI()
2711 case ARM::VLD4DUPd16Pseudo: in ExpandMI()
2712 case ARM::VLD4DUPd32Pseudo: in ExpandMI()
2713 case ARM::VLD4DUPd8Pseudo_UPD: in ExpandMI()
2714 case ARM::VLD4DUPd16Pseudo_UPD: in ExpandMI()
2715 case ARM::VLD4DUPd32Pseudo_UPD: in ExpandMI()
2716 case ARM::VLD2DUPq8EvenPseudo: in ExpandMI()
2717 case ARM::VLD2DUPq8OddPseudo: in ExpandMI()
2718 case ARM::VLD2DUPq16EvenPseudo: in ExpandMI()
2719 case ARM::VLD2DUPq16OddPseudo: in ExpandMI()
2720 case ARM::VLD2DUPq32EvenPseudo: in ExpandMI()
2721 case ARM::VLD2DUPq32OddPseudo: in ExpandMI()
2722 case ARM::VLD2DUPq8OddPseudoWB_fixed: in ExpandMI()
2723 case ARM::VLD2DUPq8OddPseudoWB_register: in ExpandMI()
2724 case ARM::VLD2DUPq16OddPseudoWB_fixed: in ExpandMI()
2725 case ARM::VLD2DUPq16OddPseudoWB_register: in ExpandMI()
2726 case ARM::VLD2DUPq32OddPseudoWB_fixed: in ExpandMI()
2727 case ARM::VLD2DUPq32OddPseudoWB_register: in ExpandMI()
2728 case ARM::VLD3DUPq8EvenPseudo: in ExpandMI()
2729 case ARM::VLD3DUPq8OddPseudo: in ExpandMI()
2730 case ARM::VLD3DUPq16EvenPseudo: in ExpandMI()
2731 case ARM::VLD3DUPq16OddPseudo: in ExpandMI()
2732 case ARM::VLD3DUPq32EvenPseudo: in ExpandMI()
2733 case ARM::VLD3DUPq32OddPseudo: in ExpandMI()
2734 case ARM::VLD3DUPq8OddPseudo_UPD: in ExpandMI()
2735 case ARM::VLD3DUPq16OddPseudo_UPD: in ExpandMI()
2736 case ARM::VLD3DUPq32OddPseudo_UPD: in ExpandMI()
2737 case ARM::VLD4DUPq8EvenPseudo: in ExpandMI()
2738 case ARM::VLD4DUPq8OddPseudo: in ExpandMI()
2739 case ARM::VLD4DUPq16EvenPseudo: in ExpandMI()
2740 case ARM::VLD4DUPq16OddPseudo: in ExpandMI()
2741 case ARM::VLD4DUPq32EvenPseudo: in ExpandMI()
2742 case ARM::VLD4DUPq32OddPseudo: in ExpandMI()
2743 case ARM::VLD4DUPq8OddPseudo_UPD: in ExpandMI()
2744 case ARM::VLD4DUPq16OddPseudo_UPD: in ExpandMI()
2745 case ARM::VLD4DUPq32OddPseudo_UPD: in ExpandMI()
2749 case ARM::VST2q8Pseudo: in ExpandMI()
2750 case ARM::VST2q16Pseudo: in ExpandMI()
2751 case ARM::VST2q32Pseudo: in ExpandMI()
2752 case ARM::VST2q8PseudoWB_fixed: in ExpandMI()
2753 case ARM::VST2q16PseudoWB_fixed: in ExpandMI()
2754 case ARM::VST2q32PseudoWB_fixed: in ExpandMI()
2755 case ARM::VST2q8PseudoWB_register: in ExpandMI()
2756 case ARM::VST2q16PseudoWB_register: in ExpandMI()
2757 case ARM::VST2q32PseudoWB_register: in ExpandMI()
2758 case ARM::VST3d8Pseudo: in ExpandMI()
2759 case ARM::VST3d16Pseudo: in ExpandMI()
2760 case ARM::VST3d32Pseudo: in ExpandMI()
2761 case ARM::VST1d8TPseudo: in ExpandMI()
2762 case ARM::VST1d8TPseudoWB_fixed: in ExpandMI()
2763 case ARM::VST1d8TPseudoWB_register: in ExpandMI()
2764 case ARM::VST1d16TPseudo: in ExpandMI()
2765 case ARM::VST1d16TPseudoWB_fixed: in ExpandMI()
2766 case ARM::VST1d16TPseudoWB_register: in ExpandMI()
2767 case ARM::VST1d32TPseudo: in ExpandMI()
2768 case ARM::VST1d32TPseudoWB_fixed: in ExpandMI()
2769 case ARM::VST1d32TPseudoWB_register: in ExpandMI()
2770 case ARM::VST1d64TPseudo: in ExpandMI()
2771 case ARM::VST1d64TPseudoWB_fixed: in ExpandMI()
2772 case ARM::VST1d64TPseudoWB_register: in ExpandMI()
2773 case ARM::VST3d8Pseudo_UPD: in ExpandMI()
2774 case ARM::VST3d16Pseudo_UPD: in ExpandMI()
2775 case ARM::VST3d32Pseudo_UPD: in ExpandMI()
2776 case ARM::VST3q8Pseudo_UPD: in ExpandMI()
2777 case ARM::VST3q16Pseudo_UPD: in ExpandMI()
2778 case ARM::VST3q32Pseudo_UPD: in ExpandMI()
2779 case ARM::VST3q8oddPseudo: in ExpandMI()
2780 case ARM::VST3q16oddPseudo: in ExpandMI()
2781 case ARM::VST3q32oddPseudo: in ExpandMI()
2782 case ARM::VST3q8oddPseudo_UPD: in ExpandMI()
2783 case ARM::VST3q16oddPseudo_UPD: in ExpandMI()
2784 case ARM::VST3q32oddPseudo_UPD: in ExpandMI()
2785 case ARM::VST4d8Pseudo: in ExpandMI()
2786 case ARM::VST4d16Pseudo: in ExpandMI()
2787 case ARM::VST4d32Pseudo: in ExpandMI()
2788 case ARM::VST1d8QPseudo: in ExpandMI()
2789 case ARM::VST1d8QPseudoWB_fixed: in ExpandMI()
2790 case ARM::VST1d8QPseudoWB_register: in ExpandMI()
2791 case ARM::VST1d16QPseudo: in ExpandMI()
2792 case ARM::VST1d16QPseudoWB_fixed: in ExpandMI()
2793 case ARM::VST1d16QPseudoWB_register: in ExpandMI()
2794 case ARM::VST1d32QPseudo: in ExpandMI()
2795 case ARM::VST1d32QPseudoWB_fixed: in ExpandMI()
2796 case ARM::VST1d32QPseudoWB_register: in ExpandMI()
2797 case ARM::VST1d64QPseudo: in ExpandMI()
2798 case ARM::VST1d64QPseudoWB_fixed: in ExpandMI()
2799 case ARM::VST1d64QPseudoWB_register: in ExpandMI()
2800 case ARM::VST4d8Pseudo_UPD: in ExpandMI()
2801 case ARM::VST4d16Pseudo_UPD: in ExpandMI()
2802 case ARM::VST4d32Pseudo_UPD: in ExpandMI()
2803 case ARM::VST1q8HighQPseudo: in ExpandMI()
2804 case ARM::VST1q8LowQPseudo_UPD: in ExpandMI()
2805 case ARM::VST1q8HighTPseudo: in ExpandMI()
2806 case ARM::VST1q8LowTPseudo_UPD: in ExpandMI()
2807 case ARM::VST1q16HighQPseudo: in ExpandMI()
2808 case ARM::VST1q16LowQPseudo_UPD: in ExpandMI()
2809 case ARM::VST1q16HighTPseudo: in ExpandMI()
2810 case ARM::VST1q16LowTPseudo_UPD: in ExpandMI()
2811 case ARM::VST1q32HighQPseudo: in ExpandMI()
2812 case ARM::VST1q32LowQPseudo_UPD: in ExpandMI()
2813 case ARM::VST1q32HighTPseudo: in ExpandMI()
2814 case ARM::VST1q32LowTPseudo_UPD: in ExpandMI()
2815 case ARM::VST1q64HighQPseudo: in ExpandMI()
2816 case ARM::VST1q64LowQPseudo_UPD: in ExpandMI()
2817 case ARM::VST1q64HighTPseudo: in ExpandMI()
2818 case ARM::VST1q64LowTPseudo_UPD: in ExpandMI()
2819 case ARM::VST1q8HighTPseudo_UPD: in ExpandMI()
2820 case ARM::VST1q16HighTPseudo_UPD: in ExpandMI()
2821 case ARM::VST1q32HighTPseudo_UPD: in ExpandMI()
2822 case ARM::VST1q64HighTPseudo_UPD: in ExpandMI()
2823 case ARM::VST1q8HighQPseudo_UPD: in ExpandMI()
2824 case ARM::VST1q16HighQPseudo_UPD: in ExpandMI()
2825 case ARM::VST1q32HighQPseudo_UPD: in ExpandMI()
2826 case ARM::VST1q64HighQPseudo_UPD: in ExpandMI()
2827 case ARM::VST4q8Pseudo_UPD: in ExpandMI()
2828 case ARM::VST4q16Pseudo_UPD: in ExpandMI()
2829 case ARM::VST4q32Pseudo_UPD: in ExpandMI()
2830 case ARM::VST4q8oddPseudo: in ExpandMI()
2831 case ARM::VST4q16oddPseudo: in ExpandMI()
2832 case ARM::VST4q32oddPseudo: in ExpandMI()
2833 case ARM::VST4q8oddPseudo_UPD: in ExpandMI()
2834 case ARM::VST4q16oddPseudo_UPD: in ExpandMI()
2835 case ARM::VST4q32oddPseudo_UPD: in ExpandMI()
2839 case ARM::VLD1LNq8Pseudo: in ExpandMI()
2840 case ARM::VLD1LNq16Pseudo: in ExpandMI()
2841 case ARM::VLD1LNq32Pseudo: in ExpandMI()
2842 case ARM::VLD1LNq8Pseudo_UPD: in ExpandMI()
2843 case ARM::VLD1LNq16Pseudo_UPD: in ExpandMI()
2844 case ARM::VLD1LNq32Pseudo_UPD: in ExpandMI()
2845 case ARM::VLD2LNd8Pseudo: in ExpandMI()
2846 case ARM::VLD2LNd16Pseudo: in ExpandMI()
2847 case ARM::VLD2LNd32Pseudo: in ExpandMI()
2848 case ARM::VLD2LNq16Pseudo: in ExpandMI()
2849 case ARM::VLD2LNq32Pseudo: in ExpandMI()
2850 case ARM::VLD2LNd8Pseudo_UPD: in ExpandMI()
2851 case ARM::VLD2LNd16Pseudo_UPD: in ExpandMI()
2852 case ARM::VLD2LNd32Pseudo_UPD: in ExpandMI()
2853 case ARM::VLD2LNq16Pseudo_UPD: in ExpandMI()
2854 case ARM::VLD2LNq32Pseudo_UPD: in ExpandMI()
2855 case ARM::VLD3LNd8Pseudo: in ExpandMI()
2856 case ARM::VLD3LNd16Pseudo: in ExpandMI()
2857 case ARM::VLD3LNd32Pseudo: in ExpandMI()
2858 case ARM::VLD3LNq16Pseudo: in ExpandMI()
2859 case ARM::VLD3LNq32Pseudo: in ExpandMI()
2860 case ARM::VLD3LNd8Pseudo_UPD: in ExpandMI()
2861 case ARM::VLD3LNd16Pseudo_UPD: in ExpandMI()
2862 case ARM::VLD3LNd32Pseudo_UPD: in ExpandMI()
2863 case ARM::VLD3LNq16Pseudo_UPD: in ExpandMI()
2864 case ARM::VLD3LNq32Pseudo_UPD: in ExpandMI()
2865 case ARM::VLD4LNd8Pseudo: in ExpandMI()
2866 case ARM::VLD4LNd16Pseudo: in ExpandMI()
2867 case ARM::VLD4LNd32Pseudo: in ExpandMI()
2868 case ARM::VLD4LNq16Pseudo: in ExpandMI()
2869 case ARM::VLD4LNq32Pseudo: in ExpandMI()
2870 case ARM::VLD4LNd8Pseudo_UPD: in ExpandMI()
2871 case ARM::VLD4LNd16Pseudo_UPD: in ExpandMI()
2872 case ARM::VLD4LNd32Pseudo_UPD: in ExpandMI()
2873 case ARM::VLD4LNq16Pseudo_UPD: in ExpandMI()
2874 case ARM::VLD4LNq32Pseudo_UPD: in ExpandMI()
2875 case ARM::VST1LNq8Pseudo: in ExpandMI()
2876 case ARM::VST1LNq16Pseudo: in ExpandMI()
2877 case ARM::VST1LNq32Pseudo: in ExpandMI()
2878 case ARM::VST1LNq8Pseudo_UPD: in ExpandMI()
2879 case ARM::VST1LNq16Pseudo_UPD: in ExpandMI()
2880 case ARM::VST1LNq32Pseudo_UPD: in ExpandMI()
2881 case ARM::VST2LNd8Pseudo: in ExpandMI()
2882 case ARM::VST2LNd16Pseudo: in ExpandMI()
2883 case ARM::VST2LNd32Pseudo: in ExpandMI()
2884 case ARM::VST2LNq16Pseudo: in ExpandMI()
2885 case ARM::VST2LNq32Pseudo: in ExpandMI()
2886 case ARM::VST2LNd8Pseudo_UPD: in ExpandMI()
2887 case ARM::VST2LNd16Pseudo_UPD: in ExpandMI()
2888 case ARM::VST2LNd32Pseudo_UPD: in ExpandMI()
2889 case ARM::VST2LNq16Pseudo_UPD: in ExpandMI()
2890 case ARM::VST2LNq32Pseudo_UPD: in ExpandMI()
2891 case ARM::VST3LNd8Pseudo: in ExpandMI()
2892 case ARM::VST3LNd16Pseudo: in ExpandMI()
2893 case ARM::VST3LNd32Pseudo: in ExpandMI()
2894 case ARM::VST3LNq16Pseudo: in ExpandMI()
2895 case ARM::VST3LNq32Pseudo: in ExpandMI()
2896 case ARM::VST3LNd8Pseudo_UPD: in ExpandMI()
2897 case ARM::VST3LNd16Pseudo_UPD: in ExpandMI()
2898 case ARM::VST3LNd32Pseudo_UPD: in ExpandMI()
2899 case ARM::VST3LNq16Pseudo_UPD: in ExpandMI()
2900 case ARM::VST3LNq32Pseudo_UPD: in ExpandMI()
2901 case ARM::VST4LNd8Pseudo: in ExpandMI()
2902 case ARM::VST4LNd16Pseudo: in ExpandMI()
2903 case ARM::VST4LNd32Pseudo: in ExpandMI()
2904 case ARM::VST4LNq16Pseudo: in ExpandMI()
2905 case ARM::VST4LNq32Pseudo: in ExpandMI()
2906 case ARM::VST4LNd8Pseudo_UPD: in ExpandMI()
2907 case ARM::VST4LNd16Pseudo_UPD: in ExpandMI()
2908 case ARM::VST4LNd32Pseudo_UPD: in ExpandMI()
2909 case ARM::VST4LNq16Pseudo_UPD: in ExpandMI()
2910 case ARM::VST4LNq32Pseudo_UPD: in ExpandMI()
2914 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true; in ExpandMI()
2915 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true; in ExpandMI()
2916 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true; in ExpandMI()
2917 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true; in ExpandMI()
2919 case ARM::tCMP_SWAP_8: in ExpandMI()
2921 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXB, ARM::t2STREXB, ARM::tUXTB, in ExpandMI()
2923 case ARM::tCMP_SWAP_16: in ExpandMI()
2925 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXH, ARM::t2STREXH, ARM::tUXTH, in ExpandMI()
2928 case ARM::CMP_SWAP_8: in ExpandMI()
2930 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXB, ARM::STREXB, ARM::UXTB, in ExpandMI()
2932 case ARM::CMP_SWAP_16: in ExpandMI()
2934 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXH, ARM::STREXH, ARM::UXTH, in ExpandMI()
2936 case ARM::CMP_SWAP_32: in ExpandMI()
2938 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREX, ARM::t2STREX, 0, in ExpandMI()
2941 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI); in ExpandMI()
2943 case ARM::CMP_SWAP_64: in ExpandMI()
2946 case ARM::tBL_PUSHLR: in ExpandMI()
2947 case ARM::BL_PUSHLR: { in ExpandMI()
2948 const bool Thumb = Opcode == ARM::tBL_PUSHLR; in ExpandMI()
2950 assert(Reg == ARM::LR && "expect LR register!"); in ExpandMI()
2954 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPUSH)) in ExpandMI()
2959 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tBL)); in ExpandMI()
2962 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::STMDB_UPD)) in ExpandMI()
2963 .addReg(ARM::SP, RegState::Define) in ExpandMI()
2964 .addReg(ARM::SP) in ExpandMI()
2969 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::BL)); in ExpandMI()
2976 case ARM::LOADDUAL: in ExpandMI()
2977 case ARM::STOREDUAL: { in ExpandMI()
2982 TII->get(Opcode == ARM::LOADDUAL ? ARM::LDRD : ARM::STRD)) in ExpandMI()
2983 .addReg(TRI->getSubReg(PairReg, ARM::gsub_0), in ExpandMI()
2984 Opcode == ARM::LOADDUAL ? RegState::Define : 0) in ExpandMI()
2985 .addReg(TRI->getSubReg(PairReg, ARM::gsub_1), in ExpandMI()
2986 Opcode == ARM::LOADDUAL ? RegState::Define : 0); in ExpandMI()