Lines Matching refs:ARM
120 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {} in UnwindContext()
179 FPReg = ARM::SP; in reset()
303 ITInst.setOpcode(ARM::t2IT); in flushPendingInstructions()
360 return MRI->getSubReg(QReg, ARM::dsub_0); in getDRegFromQReg()
510 return getSTI().getFeatureBits()[ARM::ModeThumb]; in isThumb()
514 return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2]; in isThumbOne()
518 return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2]; in isThumbTwo()
522 return getSTI().getFeatureBits()[ARM::HasV4TOps]; in hasThumb()
526 return getSTI().getFeatureBits()[ARM::FeatureThumb2]; in hasThumb2()
530 return getSTI().getFeatureBits()[ARM::HasV6Ops]; in hasV6Ops()
534 return getSTI().getFeatureBits()[ARM::HasV6T2Ops]; in hasV6T2Ops()
538 return getSTI().getFeatureBits()[ARM::HasV6MOps]; in hasV6MOps()
542 return getSTI().getFeatureBits()[ARM::HasV7Ops]; in hasV7Ops()
546 return getSTI().getFeatureBits()[ARM::HasV8Ops]; in hasV8Ops()
550 return getSTI().getFeatureBits()[ARM::HasV8MBaselineOps]; in hasV8MBaseline()
554 return getSTI().getFeatureBits()[ARM::HasV8MMainlineOps]; in hasV8MMainline()
557 return getSTI().getFeatureBits()[ARM::HasV8_1MMainlineOps]; in hasV8_1MMainline()
560 return getSTI().getFeatureBits()[ARM::HasMVEIntegerOps]; in hasMVE()
563 return getSTI().getFeatureBits()[ARM::HasMVEFloatOps]; in hasMVEFloat()
566 return getSTI().getFeatureBits()[ARM::HasCDEOps]; in hasCDE()
569 return getSTI().getFeatureBits()[ARM::Feature8MSecExt]; in has8MSecExt()
573 return !getSTI().getFeatureBits()[ARM::FeatureNoARM]; in hasARM()
577 return getSTI().getFeatureBits()[ARM::FeatureDSP]; in hasDSP()
581 return getSTI().getFeatureBits()[ARM::FeatureD32]; in hasD32()
585 return getSTI().getFeatureBits()[ARM::HasV8_1aOps]; in hasV8_1aOps()
589 return getSTI().getFeatureBits()[ARM::FeatureRAS]; in hasRAS()
594 auto FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); in SwitchMode()
601 return getSTI().getFeatureBits()[ARM::FeatureMClass]; in isMClass()
1109 if(Memory.BaseRegNum != ARM::PC) return false; in isThumbMemPC()
1363 !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum) && in isMVEMem()
1364 !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Memory.BaseRegNum)) in isMVEMem()
1367 !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( in isMVEMem()
1376 !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum)) in isGPRMem()
1379 !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.OffsetRegNum)) in isGPRMem()
1386 ARMMCRegisterClasses[ARM::GPRRegClassID].contains( in isRegShiftedReg()
1388 ARMMCRegisterClasses[ARM::GPRRegClassID].contains( in isRegShiftedReg()
1393 ARMMCRegisterClasses[ARM::GPRRegClassID].contains( in isRegShiftedImm()
1446 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(PostIdxReg.RegNum); in isPostIdxRegShifted()
1462 if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains( in isMemNoOffsetT2()
1474 if (!ARMMCRegisterClasses[ARM::rGPRRegClassID].contains( in isMemNoOffsetT2NoSp()
1486 if (!ARMMCRegisterClasses[ARM::tGPRRegClassID].contains( in isMemNoOffsetT()
1498 if (Memory.BaseRegNum != ARM::PC) in isMemPCRelImm12()
1705 Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC) in isT2MemRegOffset()
1766 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) in isMemThumbSPI()
1803 !ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains( in isMemImm7s4Offset()
1832 if (Memory.BaseRegNum == ARM::PC) return false; in isMemImm8Offset()
1878 if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains( in isMemRegRQOffset()
1881 if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( in isMemRegRQOffset()
1899 if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( in isMemRegQOffset()
1939 if (Memory.BaseRegNum == ARM::PC) return false; in isMemNegImm8Offset()
2028 ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( in isVecListTwoMQ()
2034 return (ARMMCRegisterClasses[ARM::DPairRegClassID] in isVecListDPair()
2051 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] in isVecListDPairSpaced()
2067 ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( in isVecListFourMQ()
2086 return (ARMMCRegisterClasses[ARM::DPairRegClassID] in isVecListDPairAllLanes()
2476 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands()
2483 unsigned RegNum = getVPTPred() == ARMVCC::None ? 0: ARM::P0; in addVPTPredNOperands()
3352 const MCRegisterClass *RC_in = &ARMMCRegisterClasses[ARM::MQPRRegClassID]; in addMVEVecListOperands()
3354 &ARMMCRegisterClasses[ARM::QQPRRegClassID] : in addMVEVecListOperands()
3355 &ARMMCRegisterClasses[ARM::QQQQPRRegClassID]; in addMVEVecListOperands()
3449 assert((Inst.getOpcode() == ARM::VMOVv8i8 || in addNEONi8ReplicateOperands()
3450 Inst.getOpcode() == ARM::VMOVv16i8) && in addNEONi8ReplicateOperands()
3492 assert((Inst.getOpcode() == ARM::VMOVv4i16 || in addNEONvmovi16ReplicateOperands()
3493 Inst.getOpcode() == ARM::VMOVv8i16 || in addNEONvmovi16ReplicateOperands()
3494 Inst.getOpcode() == ARM::VMVNv4i16 || in addNEONvmovi16ReplicateOperands()
3495 Inst.getOpcode() == ARM::VMVNv8i16) && in addNEONvmovi16ReplicateOperands()
3516 assert((Inst.getOpcode() == ARM::VMOVv2i32 || in addNEONvmovi32ReplicateOperands()
3517 Inst.getOpcode() == ARM::VMOVv4i32 || in addNEONvmovi32ReplicateOperands()
3518 Inst.getOpcode() == ARM::VMVNv2i32 || in addNEONvmovi32ReplicateOperands()
3519 Inst.getOpcode() == ARM::VMVNv4i32) && in addNEONvmovi32ReplicateOperands()
3718 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains( in CreateRegList()
3720 if (Regs.back().second == ARM::VPR) in CreateRegList()
3724 } else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains( in CreateRegList()
3726 if (Regs.back().second == ARM::VPR) in CreateRegList()
3732 if (Kind == k_RegisterList && Regs.back().second == ARM::APSR) in CreateRegList()
4085 .Case("r13", ARM::SP) in tryParseRegister()
4086 .Case("r14", ARM::LR) in tryParseRegister()
4087 .Case("r15", ARM::PC) in tryParseRegister()
4088 .Case("ip", ARM::R12) in tryParseRegister()
4090 .Case("a1", ARM::R0) in tryParseRegister()
4091 .Case("a2", ARM::R1) in tryParseRegister()
4092 .Case("a3", ARM::R2) in tryParseRegister()
4093 .Case("a4", ARM::R3) in tryParseRegister()
4094 .Case("v1", ARM::R4) in tryParseRegister()
4095 .Case("v2", ARM::R5) in tryParseRegister()
4096 .Case("v3", ARM::R6) in tryParseRegister()
4097 .Case("v4", ARM::R7) in tryParseRegister()
4098 .Case("v5", ARM::R8) in tryParseRegister()
4099 .Case("v6", ARM::R9) in tryParseRegister()
4100 .Case("v7", ARM::R10) in tryParseRegister()
4101 .Case("v8", ARM::R11) in tryParseRegister()
4102 .Case("sb", ARM::R9) in tryParseRegister()
4103 .Case("sl", ARM::R10) in tryParseRegister()
4104 .Case("fp", ARM::R11) in tryParseRegister()
4120 if (!hasD32() && RegNum >= ARM::D16 && RegNum <= ARM::D31) in tryParseRegister()
4432 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) in getNextRegister()
4436 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; in getNextRegister()
4437 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; in getNextRegister()
4438 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; in getNextRegister()
4439 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; in getNextRegister()
4440 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; in getNextRegister()
4441 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; in getNextRegister()
4442 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; in getNextRegister()
4443 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; in getNextRegister()
4487 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { in parseRegisterList()
4494 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) in parseRegisterList()
4495 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; in parseRegisterList()
4496 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) in parseRegisterList()
4497 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; in parseRegisterList()
4498 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) in parseRegisterList()
4499 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; in parseRegisterList()
4500 else if (ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) in parseRegisterList()
4501 RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID]; in parseRegisterList()
4521 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) in parseRegisterList()
4555 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { in parseRegisterList()
4560 RC->getID() == ARMMCRegisterClasses[ARM::GPRRegClassID].getID() && in parseRegisterList()
4561 ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) { in parseRegisterList()
4564 RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID]; in parseRegisterList()
4566 if (Reg == ARM::VPR && in parseRegisterList()
4567 (RC == &ARMMCRegisterClasses[ARM::SPRRegClassID] || in parseRegisterList()
4568 RC == &ARMMCRegisterClasses[ARM::DPRRegClassID] || in parseRegisterList()
4569 RC == &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID])) { in parseRegisterList()
4570 RC = &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID]; in parseRegisterList()
4587 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) in parseRegisterList()
4589 else if (!ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) in parseRegisterList()
4593 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && in parseRegisterList()
4594 RC != &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID] && in parseRegisterList()
4692 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { in parseVectorList()
4712 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { in parseVectorList()
4719 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, in parseVectorList()
4720 &ARMMCRegisterClasses[ARM::DPairRegClassID]); in parseVectorList()
4724 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, in parseVectorList()
4725 &ARMMCRegisterClasses[ARM::DPairRegClassID]); in parseVectorList()
4756 if (hasMVE() && !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) { in parseVectorList()
4762 else if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { in parseVectorList()
4792 if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) in parseVectorList()
4800 !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(EndReg)) || in parseVectorList()
4802 !ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg))) { in parseVectorList()
4837 if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) { in parseVectorList()
4849 else if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { in parseVectorList()
4915 &ARMMCRegisterClasses[ARM::DPairRegClassID] : in parseVectorList()
4916 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; in parseVectorList()
4917 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); in parseVectorList()
5756 case ARM::tB: in cvtThumbBranches()
5757 case ARM::tBcc: CondOp = 1; ImmOp = 2; break; in cvtThumbBranches()
5759 case ARM::t2B: in cvtThumbBranches()
5760 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break; in cvtThumbBranches()
5770 case ARM::tBcc: Inst.setOpcode(ARM::tB); break; in cvtThumbBranches()
5771 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break; in cvtThumbBranches()
5778 case ARM::tB: in cvtThumbBranches()
5779 case ARM::tBcc: in cvtThumbBranches()
5780 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc); in cvtThumbBranches()
5782 case ARM::t2B: in cvtThumbBranches()
5783 case ARM::t2Bcc: in cvtThumbBranches()
5784 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc); in cvtThumbBranches()
5792 case ARM::tB: { in cvtThumbBranches()
5795 Inst.setOpcode(ARM::t2B); in cvtThumbBranches()
5799 case ARM::tBcc: { in cvtThumbBranches()
5802 Inst.setOpcode(ARM::t2Bcc); in cvtThumbBranches()
6639 bool TryTransform = Op3Reg == ARM::PC || Op4Reg == ARM::PC || in tryConvertingToTwoOperandForm()
6640 (Op5.isReg() && Op5.getReg() == ARM::PC); in tryConvertingToTwoOperandForm()
6642 TryTransform = (Op3Reg == ARM::SP || Op4Reg == ARM::SP || in tryConvertingToTwoOperandForm()
6643 (Op5.isReg() && Op5.getReg() == ARM::SP)) && in tryConvertingToTwoOperandForm()
6644 !(Op3Reg == ARM::SP && Op4Reg == ARM::SP && in tryConvertingToTwoOperandForm()
6669 ((Mnemonic == "add" && Op4Reg != ARM::SP) || in tryConvertingToTwoOperandForm()
6733 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP && in shouldOmitCCOutOperand()
6758 if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC && in shouldOmitCCOutOperand()
6811 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP && in shouldOmitCCOutOperand()
6827 static_cast<ARMOperand &>(*Operands[3]).getReg() != ARM::SP && in shouldOmitCCOutOperand()
6828 static_cast<ARMOperand &>(*Operands[3]).getReg() != ARM::PC && in shouldOmitCCOutOperand()
6860 (ARMMCRegisterClasses[ARM::DPRRegClassID].contains( in shouldOmitPredicateOperand()
6862 ARMMCRegisterClasses[ARM::QPRRegClassID].contains( in shouldOmitPredicateOperand()
6887 (ARMMCRegisterClasses[ARM::SPRRegClassID].contains( in shouldOmitVectorPredicateOperand()
6889 ARMMCRegisterClasses[ARM::DPRRegClassID].contains( in shouldOmitVectorPredicateOperand()
6902 (ARMMCRegisterClasses[ARM::QPRRegClassID].contains( in shouldOmitVectorPredicateOperand()
6953 const MCRegisterClass &GPR = MRI->getRegClass(ARM::GPRRegClassID); in fixupGNULDRDAlias()
6963 if (Op2.getReg() == ARM::PC) in fixupGNULDRDAlias()
6966 if (!PairedReg || PairedReg == ARM::PC || in fixupGNULDRDAlias()
6967 (PairedReg == ARM::SP && !hasV8Ops())) in fixupGNULDRDAlias()
7002 case ARM::R0: in CDEConvertDualRegOperand()
7003 RNext = ARM::R1; in CDEConvertDualRegOperand()
7004 RPair = ARM::R0_R1; in CDEConvertDualRegOperand()
7006 case ARM::R2: in CDEConvertDualRegOperand()
7007 RNext = ARM::R3; in CDEConvertDualRegOperand()
7008 RPair = ARM::R2_R3; in CDEConvertDualRegOperand()
7010 case ARM::R4: in CDEConvertDualRegOperand()
7011 RNext = ARM::R5; in CDEConvertDualRegOperand()
7012 RPair = ARM::R4_R5; in CDEConvertDualRegOperand()
7014 case ARM::R6: in CDEConvertDualRegOperand()
7015 RNext = ARM::R7; in CDEConvertDualRegOperand()
7016 RPair = ARM::R6_R7; in CDEConvertDualRegOperand()
7018 case ARM::R8: in CDEConvertDualRegOperand()
7019 RNext = ARM::R9; in CDEConvertDualRegOperand()
7020 RPair = ARM::R8_R9; in CDEConvertDualRegOperand()
7022 case ARM::R10: in CDEConvertDualRegOperand()
7023 RNext = ARM::R11; in CDEConvertDualRegOperand()
7024 RPair = ARM::R10_R11; in CDEConvertDualRegOperand()
7153 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, in ParseInstruction()
7410 const MCRegisterClass &MRC = MRI->getRegClass(ARM::GPRRegClassID); in ParseInstruction()
7426 Reg1, ARM::gsub_0, &(MRI->getRegClass(ARM::GPRPairRegClassID))); in ParseInstruction()
7443 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC && in ParseInstruction()
7445 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR && in ParseInstruction()
7487 return Inst.getOpcode() == ARM::tBKPT || in instIsBreakpoint()
7488 Inst.getOpcode() == ARM::BKPT || in instIsBreakpoint()
7489 Inst.getOpcode() == ARM::tHLT || in instIsBreakpoint()
7490 Inst.getOpcode() == ARM::HLT; in instIsBreakpoint()
7499 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP); in validatetLDMRegList()
7500 bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR); in validatetLDMRegList()
7501 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC); in validatetLDMRegList()
7518 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP); in validatetSTMRegList()
7519 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC); in validatetSTMRegList()
7593 if (ARM::isVpred(MCID.OpInfo[i].OperandType)) in findFirstVectorPredOperandIdx()
7632 ARMCC::AL && Inst.getOpcode() != ARM::tBcc && in validateInstruction()
7633 Inst.getOpcode() != ARM::t2Bcc && in validateInstruction()
7634 Inst.getOpcode() != ARM::t2BFic) { in validateInstruction()
7684 case ARM::t2IT: { in validateInstruction()
7698 case ARM::LDRD: in validateInstruction()
7703 case ARM::LDRD_PRE: in validateInstruction()
7704 case ARM::LDRD_POST: in validateInstruction()
7709 case ARM::t2LDRDi8: in validateInstruction()
7714 case ARM::t2LDRD_PRE: in validateInstruction()
7715 case ARM::t2LDRD_POST: in validateInstruction()
7720 case ARM::t2BXJ: { in validateInstruction()
7723 if (RmReg == ARM::SP && !hasV8Ops()) in validateInstruction()
7728 case ARM::STRD: in validateInstruction()
7733 case ARM::STRD_PRE: in validateInstruction()
7734 case ARM::STRD_POST: in validateInstruction()
7739 case ARM::t2STRD_PRE: in validateInstruction()
7740 case ARM::t2STRD_POST: in validateInstruction()
7745 case ARM::STR_PRE_IMM: in validateInstruction()
7746 case ARM::STR_PRE_REG: in validateInstruction()
7747 case ARM::t2STR_PRE: in validateInstruction()
7748 case ARM::STR_POST_IMM: in validateInstruction()
7749 case ARM::STR_POST_REG: in validateInstruction()
7750 case ARM::t2STR_POST: in validateInstruction()
7751 case ARM::STRH_PRE: in validateInstruction()
7752 case ARM::t2STRH_PRE: in validateInstruction()
7753 case ARM::STRH_POST: in validateInstruction()
7754 case ARM::t2STRH_POST: in validateInstruction()
7755 case ARM::STRB_PRE_IMM: in validateInstruction()
7756 case ARM::STRB_PRE_REG: in validateInstruction()
7757 case ARM::t2STRB_PRE: in validateInstruction()
7758 case ARM::STRB_POST_IMM: in validateInstruction()
7759 case ARM::STRB_POST_REG: in validateInstruction()
7760 case ARM::t2STRB_POST: { in validateInstruction()
7770 case ARM::t2LDR_PRE_imm: in validateInstruction()
7771 case ARM::t2LDR_POST_imm: in validateInstruction()
7772 case ARM::t2STR_PRE_imm: in validateInstruction()
7773 case ARM::t2STR_POST_imm: { in validateInstruction()
7781 if (Inst.getOpcode() == ARM::t2LDR_POST_imm || in validateInstruction()
7782 Inst.getOpcode() == ARM::t2STR_POST_imm) { in validateInstruction()
7788 if (Inst.getOpcode() == ARM::t2STR_PRE_imm || in validateInstruction()
7789 Inst.getOpcode() == ARM::t2STR_POST_imm) { in validateInstruction()
7790 if (Inst.getOperand(0).getReg() == ARM::PC) { in validateInstruction()
7797 case ARM::LDR_PRE_IMM: in validateInstruction()
7798 case ARM::LDR_PRE_REG: in validateInstruction()
7799 case ARM::t2LDR_PRE: in validateInstruction()
7800 case ARM::LDR_POST_IMM: in validateInstruction()
7801 case ARM::LDR_POST_REG: in validateInstruction()
7802 case ARM::t2LDR_POST: in validateInstruction()
7803 case ARM::LDRH_PRE: in validateInstruction()
7804 case ARM::t2LDRH_PRE: in validateInstruction()
7805 case ARM::LDRH_POST: in validateInstruction()
7806 case ARM::t2LDRH_POST: in validateInstruction()
7807 case ARM::LDRSH_PRE: in validateInstruction()
7808 case ARM::t2LDRSH_PRE: in validateInstruction()
7809 case ARM::LDRSH_POST: in validateInstruction()
7810 case ARM::t2LDRSH_POST: in validateInstruction()
7811 case ARM::LDRB_PRE_IMM: in validateInstruction()
7812 case ARM::LDRB_PRE_REG: in validateInstruction()
7813 case ARM::t2LDRB_PRE: in validateInstruction()
7814 case ARM::LDRB_POST_IMM: in validateInstruction()
7815 case ARM::LDRB_POST_REG: in validateInstruction()
7816 case ARM::t2LDRB_POST: in validateInstruction()
7817 case ARM::LDRSB_PRE: in validateInstruction()
7818 case ARM::t2LDRSB_PRE: in validateInstruction()
7819 case ARM::LDRSB_POST: in validateInstruction()
7820 case ARM::t2LDRSB_POST: { in validateInstruction()
7831 case ARM::MVE_VLDRBU8_rq: in validateInstruction()
7832 case ARM::MVE_VLDRBU16_rq: in validateInstruction()
7833 case ARM::MVE_VLDRBS16_rq: in validateInstruction()
7834 case ARM::MVE_VLDRBU32_rq: in validateInstruction()
7835 case ARM::MVE_VLDRBS32_rq: in validateInstruction()
7836 case ARM::MVE_VLDRHU16_rq: in validateInstruction()
7837 case ARM::MVE_VLDRHU16_rq_u: in validateInstruction()
7838 case ARM::MVE_VLDRHU32_rq: in validateInstruction()
7839 case ARM::MVE_VLDRHU32_rq_u: in validateInstruction()
7840 case ARM::MVE_VLDRHS32_rq: in validateInstruction()
7841 case ARM::MVE_VLDRHS32_rq_u: in validateInstruction()
7842 case ARM::MVE_VLDRWU32_rq: in validateInstruction()
7843 case ARM::MVE_VLDRWU32_rq_u: in validateInstruction()
7844 case ARM::MVE_VLDRDU64_rq: in validateInstruction()
7845 case ARM::MVE_VLDRDU64_rq_u: in validateInstruction()
7846 case ARM::MVE_VLDRWU32_qi: in validateInstruction()
7847 case ARM::MVE_VLDRWU32_qi_pre: in validateInstruction()
7848 case ARM::MVE_VLDRDU64_qi: in validateInstruction()
7849 case ARM::MVE_VLDRDU64_qi_pre: { in validateInstruction()
7854 case ARM::MVE_VLDRWU32_qi: in validateInstruction()
7855 case ARM::MVE_VLDRDU64_qi: in validateInstruction()
7859 case ARM::MVE_VLDRWU32_qi_pre: in validateInstruction()
7860 case ARM::MVE_VLDRDU64_qi_pre: in validateInstruction()
7878 case ARM::SBFX: in validateInstruction()
7879 case ARM::t2SBFX: in validateInstruction()
7880 case ARM::UBFX: in validateInstruction()
7881 case ARM::t2UBFX: { in validateInstruction()
7891 case ARM::tLDMIA: { in validateInstruction()
7921 case ARM::LDMIA_UPD: in validateInstruction()
7922 case ARM::LDMDB_UPD: in validateInstruction()
7923 case ARM::LDMIB_UPD: in validateInstruction()
7924 case ARM::LDMDA_UPD: in validateInstruction()
7933 case ARM::t2LDMIA: in validateInstruction()
7934 case ARM::t2LDMDB: in validateInstruction()
7938 case ARM::t2STMIA: in validateInstruction()
7939 case ARM::t2STMDB: in validateInstruction()
7943 case ARM::t2LDMIA_UPD: in validateInstruction()
7944 case ARM::t2LDMDB_UPD: in validateInstruction()
7945 case ARM::t2STMIA_UPD: in validateInstruction()
7946 case ARM::t2STMDB_UPD: in validateInstruction()
7951 if (Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) { in validateInstruction()
7960 case ARM::sysLDMIA_UPD: in validateInstruction()
7961 case ARM::sysLDMDA_UPD: in validateInstruction()
7962 case ARM::sysLDMDB_UPD: in validateInstruction()
7963 case ARM::sysLDMIB_UPD: in validateInstruction()
7964 if (!listContainsReg(Inst, 3, ARM::PC)) in validateInstruction()
7969 case ARM::sysSTMIA_UPD: in validateInstruction()
7970 case ARM::sysSTMDA_UPD: in validateInstruction()
7971 case ARM::sysSTMDB_UPD: in validateInstruction()
7972 case ARM::sysSTMIB_UPD: in validateInstruction()
7975 case ARM::tMUL: in validateInstruction()
7996 case ARM::tPOP: { in validateInstruction()
7998 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) && in validateInstruction()
8006 case ARM::tPUSH: { in validateInstruction()
8008 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) && in validateInstruction()
8016 case ARM::tSTMIA_UPD: { in validateInstruction()
8035 case ARM::tADDrSP: in validateInstruction()
8045 case ARM::t2ADDrr: in validateInstruction()
8046 case ARM::t2ADDrs: in validateInstruction()
8047 case ARM::t2SUBrr: in validateInstruction()
8048 case ARM::t2SUBrs: in validateInstruction()
8049 if (Inst.getOperand(0).getReg() == ARM::SP && in validateInstruction()
8050 Inst.getOperand(1).getReg() != ARM::SP) in validateInstruction()
8056 case ARM::tB: in validateInstruction()
8060 case ARM::t2B: { in validateInstruction()
8070 case ARM::tBcc: in validateInstruction()
8074 case ARM::t2Bcc: { in validateInstruction()
8080 case ARM::tCBZ: in validateInstruction()
8081 case ARM::tCBNZ: { in validateInstruction()
8086 case ARM::MOVi16: in validateInstruction()
8087 case ARM::MOVTi16: in validateInstruction()
8088 case ARM::t2MOVi16: in validateInstruction()
8089 case ARM::t2MOVTi16: in validateInstruction()
8111 case ARM::HINT: in validateInstruction()
8112 case ARM::t2HINT: { in validateInstruction()
8127 case ARM::t2BFi: in validateInstruction()
8128 case ARM::t2BFr: in validateInstruction()
8129 case ARM::t2BFLi: in validateInstruction()
8130 case ARM::t2BFLr: { in validateInstruction()
8136 if (Opcode == ARM::t2BFi) { in validateInstruction()
8140 } else if (Opcode == ARM::t2BFLi) { in validateInstruction()
8147 case ARM::t2BFic: { in validateInstruction()
8170 case ARM::t2CLRM: { in validateInstruction()
8173 !ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains( in validateInstruction()
8182 case ARM::DSB: in validateInstruction()
8183 case ARM::t2DSB: { in validateInstruction()
8202 case ARM::VMOVRRS: { in validateInstruction()
8211 case ARM::VMOVSRR: { in validateInstruction()
8220 case ARM::VLDMDIA: in validateInstruction()
8221 case ARM::VSTMDIA: { in validateInstruction()
8229 case ARM::MVE_VQDMULLs32bh: in validateInstruction()
8230 case ARM::MVE_VQDMULLs32th: in validateInstruction()
8231 case ARM::MVE_VCMULf32: in validateInstruction()
8232 case ARM::MVE_VMULLBs32: in validateInstruction()
8233 case ARM::MVE_VMULLTs32: in validateInstruction()
8234 case ARM::MVE_VMULLBu32: in validateInstruction()
8235 case ARM::MVE_VMULLTu32: { in validateInstruction()
8246 case ARM::MVE_VMOV_rr_q: { in validateInstruction()
8254 case ARM::MVE_VMOV_q_rr: { in validateInstruction()
8262 case ARM::UMAAL: in validateInstruction()
8263 case ARM::UMLAL: in validateInstruction()
8264 case ARM::UMULL: in validateInstruction()
8265 case ARM::t2UMAAL: in validateInstruction()
8266 case ARM::t2UMLAL: in validateInstruction()
8267 case ARM::t2UMULL: in validateInstruction()
8268 case ARM::SMLAL: in validateInstruction()
8269 case ARM::SMLALBB: in validateInstruction()
8270 case ARM::SMLALBT: in validateInstruction()
8271 case ARM::SMLALD: in validateInstruction()
8272 case ARM::SMLALDX: in validateInstruction()
8273 case ARM::SMLALTB: in validateInstruction()
8274 case ARM::SMLALTT: in validateInstruction()
8275 case ARM::SMLSLD: in validateInstruction()
8276 case ARM::SMLSLDX: in validateInstruction()
8277 case ARM::SMULL: in validateInstruction()
8278 case ARM::t2SMLAL: in validateInstruction()
8279 case ARM::t2SMLALBB: in validateInstruction()
8280 case ARM::t2SMLALBT: in validateInstruction()
8281 case ARM::t2SMLALD: in validateInstruction()
8282 case ARM::t2SMLALDX: in validateInstruction()
8283 case ARM::t2SMLALTB: in validateInstruction()
8284 case ARM::t2SMLALTT: in validateInstruction()
8285 case ARM::t2SMLSLD: in validateInstruction()
8286 case ARM::t2SMLSLDX: in validateInstruction()
8287 case ARM::t2SMULL: { in validateInstruction()
8297 case ARM::CDE_CX1: in validateInstruction()
8298 case ARM::CDE_CX1A: in validateInstruction()
8299 case ARM::CDE_CX1D: in validateInstruction()
8300 case ARM::CDE_CX1DA: in validateInstruction()
8301 case ARM::CDE_CX2: in validateInstruction()
8302 case ARM::CDE_CX2A: in validateInstruction()
8303 case ARM::CDE_CX2D: in validateInstruction()
8304 case ARM::CDE_CX2DA: in validateInstruction()
8305 case ARM::CDE_CX3: in validateInstruction()
8306 case ARM::CDE_CX3A: in validateInstruction()
8307 case ARM::CDE_CX3D: in validateInstruction()
8308 case ARM::CDE_CX3DA: in validateInstruction()
8309 case ARM::CDE_VCX1_vec: in validateInstruction()
8310 case ARM::CDE_VCX1_fpsp: in validateInstruction()
8311 case ARM::CDE_VCX1_fpdp: in validateInstruction()
8312 case ARM::CDE_VCX1A_vec: in validateInstruction()
8313 case ARM::CDE_VCX1A_fpsp: in validateInstruction()
8314 case ARM::CDE_VCX1A_fpdp: in validateInstruction()
8315 case ARM::CDE_VCX2_vec: in validateInstruction()
8316 case ARM::CDE_VCX2_fpsp: in validateInstruction()
8317 case ARM::CDE_VCX2_fpdp: in validateInstruction()
8318 case ARM::CDE_VCX2A_vec: in validateInstruction()
8319 case ARM::CDE_VCX2A_fpsp: in validateInstruction()
8320 case ARM::CDE_VCX2A_fpdp: in validateInstruction()
8321 case ARM::CDE_VCX3_vec: in validateInstruction()
8322 case ARM::CDE_VCX3_fpsp: in validateInstruction()
8323 case ARM::CDE_VCX3_fpdp: in validateInstruction()
8324 case ARM::CDE_VCX3A_vec: in validateInstruction()
8325 case ARM::CDE_VCX3A_fpsp: in validateInstruction()
8326 case ARM::CDE_VCX3A_fpdp: { in validateInstruction()
8330 if (Coproc < 8 && !ARM::isCDECoproc(Coproc, *STI)) in validateInstruction()
8339 case ARM::t2CDP: in validateInstruction()
8340 case ARM::t2CDP2: in validateInstruction()
8341 case ARM::t2LDC2L_OFFSET: in validateInstruction()
8342 case ARM::t2LDC2L_OPTION: in validateInstruction()
8343 case ARM::t2LDC2L_POST: in validateInstruction()
8344 case ARM::t2LDC2L_PRE: in validateInstruction()
8345 case ARM::t2LDC2_OFFSET: in validateInstruction()
8346 case ARM::t2LDC2_OPTION: in validateInstruction()
8347 case ARM::t2LDC2_POST: in validateInstruction()
8348 case ARM::t2LDC2_PRE: in validateInstruction()
8349 case ARM::t2LDCL_OFFSET: in validateInstruction()
8350 case ARM::t2LDCL_OPTION: in validateInstruction()
8351 case ARM::t2LDCL_POST: in validateInstruction()
8352 case ARM::t2LDCL_PRE: in validateInstruction()
8353 case ARM::t2LDC_OFFSET: in validateInstruction()
8354 case ARM::t2LDC_OPTION: in validateInstruction()
8355 case ARM::t2LDC_POST: in validateInstruction()
8356 case ARM::t2LDC_PRE: in validateInstruction()
8357 case ARM::t2MCR: in validateInstruction()
8358 case ARM::t2MCR2: in validateInstruction()
8359 case ARM::t2MCRR: in validateInstruction()
8360 case ARM::t2MCRR2: in validateInstruction()
8361 case ARM::t2MRC: in validateInstruction()
8362 case ARM::t2MRC2: in validateInstruction()
8363 case ARM::t2MRRC: in validateInstruction()
8364 case ARM::t2MRRC2: in validateInstruction()
8365 case ARM::t2STC2L_OFFSET: in validateInstruction()
8366 case ARM::t2STC2L_OPTION: in validateInstruction()
8367 case ARM::t2STC2L_POST: in validateInstruction()
8368 case ARM::t2STC2L_PRE: in validateInstruction()
8369 case ARM::t2STC2_OFFSET: in validateInstruction()
8370 case ARM::t2STC2_OPTION: in validateInstruction()
8371 case ARM::t2STC2_POST: in validateInstruction()
8372 case ARM::t2STC2_PRE: in validateInstruction()
8373 case ARM::t2STCL_OFFSET: in validateInstruction()
8374 case ARM::t2STCL_OPTION: in validateInstruction()
8375 case ARM::t2STCL_POST: in validateInstruction()
8376 case ARM::t2STCL_PRE: in validateInstruction()
8377 case ARM::t2STC_OFFSET: in validateInstruction()
8378 case ARM::t2STC_OPTION: in validateInstruction()
8379 case ARM::t2STC_POST: in validateInstruction()
8380 case ARM::t2STC_PRE: { in validateInstruction()
8385 if (Opcode == ARM::t2MRRC || Opcode == ARM::t2MRRC2) in validateInstruction()
8387 else if (Opcode == ARM::t2MRC || Opcode == ARM::t2MRC2) in validateInstruction()
8393 if (ARM::isCDECoproc(Coproc, *STI)) in validateInstruction()
8407 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; in getRealVSTOpcode()
8408 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; in getRealVSTOpcode()
8409 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; in getRealVSTOpcode()
8410 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; in getRealVSTOpcode()
8411 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; in getRealVSTOpcode()
8412 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; in getRealVSTOpcode()
8413 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8; in getRealVSTOpcode()
8414 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16; in getRealVSTOpcode()
8415 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32; in getRealVSTOpcode()
8418 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; in getRealVSTOpcode()
8419 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; in getRealVSTOpcode()
8420 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; in getRealVSTOpcode()
8421 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; in getRealVSTOpcode()
8422 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; in getRealVSTOpcode()
8424 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; in getRealVSTOpcode()
8425 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; in getRealVSTOpcode()
8426 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; in getRealVSTOpcode()
8427 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; in getRealVSTOpcode()
8428 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; in getRealVSTOpcode()
8430 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8; in getRealVSTOpcode()
8431 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16; in getRealVSTOpcode()
8432 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32; in getRealVSTOpcode()
8433 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16; in getRealVSTOpcode()
8434 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32; in getRealVSTOpcode()
8437 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; in getRealVSTOpcode()
8438 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; in getRealVSTOpcode()
8439 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; in getRealVSTOpcode()
8440 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD; in getRealVSTOpcode()
8441 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; in getRealVSTOpcode()
8442 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; in getRealVSTOpcode()
8443 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; in getRealVSTOpcode()
8444 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; in getRealVSTOpcode()
8445 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD; in getRealVSTOpcode()
8446 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; in getRealVSTOpcode()
8447 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8; in getRealVSTOpcode()
8448 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16; in getRealVSTOpcode()
8449 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32; in getRealVSTOpcode()
8450 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16; in getRealVSTOpcode()
8451 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32; in getRealVSTOpcode()
8454 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; in getRealVSTOpcode()
8455 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; in getRealVSTOpcode()
8456 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; in getRealVSTOpcode()
8457 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; in getRealVSTOpcode()
8458 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; in getRealVSTOpcode()
8459 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; in getRealVSTOpcode()
8460 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; in getRealVSTOpcode()
8461 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; in getRealVSTOpcode()
8462 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; in getRealVSTOpcode()
8463 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; in getRealVSTOpcode()
8464 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; in getRealVSTOpcode()
8465 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; in getRealVSTOpcode()
8466 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8; in getRealVSTOpcode()
8467 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16; in getRealVSTOpcode()
8468 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32; in getRealVSTOpcode()
8469 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8; in getRealVSTOpcode()
8470 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16; in getRealVSTOpcode()
8471 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32; in getRealVSTOpcode()
8474 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; in getRealVSTOpcode()
8475 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; in getRealVSTOpcode()
8476 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; in getRealVSTOpcode()
8477 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD; in getRealVSTOpcode()
8478 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; in getRealVSTOpcode()
8479 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; in getRealVSTOpcode()
8480 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; in getRealVSTOpcode()
8481 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; in getRealVSTOpcode()
8482 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD; in getRealVSTOpcode()
8483 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; in getRealVSTOpcode()
8484 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8; in getRealVSTOpcode()
8485 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16; in getRealVSTOpcode()
8486 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32; in getRealVSTOpcode()
8487 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16; in getRealVSTOpcode()
8488 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32; in getRealVSTOpcode()
8491 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; in getRealVSTOpcode()
8492 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; in getRealVSTOpcode()
8493 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; in getRealVSTOpcode()
8494 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; in getRealVSTOpcode()
8495 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; in getRealVSTOpcode()
8496 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; in getRealVSTOpcode()
8497 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; in getRealVSTOpcode()
8498 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; in getRealVSTOpcode()
8499 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; in getRealVSTOpcode()
8500 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; in getRealVSTOpcode()
8501 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; in getRealVSTOpcode()
8502 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; in getRealVSTOpcode()
8503 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8; in getRealVSTOpcode()
8504 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16; in getRealVSTOpcode()
8505 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32; in getRealVSTOpcode()
8506 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8; in getRealVSTOpcode()
8507 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16; in getRealVSTOpcode()
8508 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32; in getRealVSTOpcode()
8516 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; in getRealVLDOpcode()
8517 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; in getRealVLDOpcode()
8518 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; in getRealVLDOpcode()
8519 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; in getRealVLDOpcode()
8520 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; in getRealVLDOpcode()
8521 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; in getRealVLDOpcode()
8522 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8; in getRealVLDOpcode()
8523 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16; in getRealVLDOpcode()
8524 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32; in getRealVLDOpcode()
8527 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; in getRealVLDOpcode()
8528 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; in getRealVLDOpcode()
8529 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; in getRealVLDOpcode()
8530 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD; in getRealVLDOpcode()
8531 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; in getRealVLDOpcode()
8532 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; in getRealVLDOpcode()
8533 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; in getRealVLDOpcode()
8534 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; in getRealVLDOpcode()
8535 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD; in getRealVLDOpcode()
8536 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; in getRealVLDOpcode()
8537 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8; in getRealVLDOpcode()
8538 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16; in getRealVLDOpcode()
8539 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32; in getRealVLDOpcode()
8540 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16; in getRealVLDOpcode()
8541 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32; in getRealVLDOpcode()
8544 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; in getRealVLDOpcode()
8545 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; in getRealVLDOpcode()
8546 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; in getRealVLDOpcode()
8547 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD; in getRealVLDOpcode()
8548 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; in getRealVLDOpcode()
8549 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; in getRealVLDOpcode()
8550 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; in getRealVLDOpcode()
8551 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; in getRealVLDOpcode()
8552 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; in getRealVLDOpcode()
8553 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD; in getRealVLDOpcode()
8554 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; in getRealVLDOpcode()
8555 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; in getRealVLDOpcode()
8556 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8; in getRealVLDOpcode()
8557 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16; in getRealVLDOpcode()
8558 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32; in getRealVLDOpcode()
8559 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8; in getRealVLDOpcode()
8560 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16; in getRealVLDOpcode()
8561 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32; in getRealVLDOpcode()
8564 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; in getRealVLDOpcode()
8565 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; in getRealVLDOpcode()
8566 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; in getRealVLDOpcode()
8567 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD; in getRealVLDOpcode()
8568 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; in getRealVLDOpcode()
8569 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; in getRealVLDOpcode()
8570 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; in getRealVLDOpcode()
8571 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; in getRealVLDOpcode()
8572 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD; in getRealVLDOpcode()
8573 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; in getRealVLDOpcode()
8574 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8; in getRealVLDOpcode()
8575 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16; in getRealVLDOpcode()
8576 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32; in getRealVLDOpcode()
8577 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16; in getRealVLDOpcode()
8578 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32; in getRealVLDOpcode()
8581 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; in getRealVLDOpcode()
8582 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; in getRealVLDOpcode()
8583 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; in getRealVLDOpcode()
8584 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; in getRealVLDOpcode()
8585 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; in getRealVLDOpcode()
8586 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; in getRealVLDOpcode()
8587 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; in getRealVLDOpcode()
8588 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; in getRealVLDOpcode()
8589 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; in getRealVLDOpcode()
8590 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; in getRealVLDOpcode()
8591 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; in getRealVLDOpcode()
8592 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; in getRealVLDOpcode()
8593 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8; in getRealVLDOpcode()
8594 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16; in getRealVLDOpcode()
8595 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32; in getRealVLDOpcode()
8596 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8; in getRealVLDOpcode()
8597 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16; in getRealVLDOpcode()
8598 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32; in getRealVLDOpcode()
8601 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; in getRealVLDOpcode()
8602 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; in getRealVLDOpcode()
8603 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; in getRealVLDOpcode()
8604 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; in getRealVLDOpcode()
8605 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; in getRealVLDOpcode()
8606 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; in getRealVLDOpcode()
8607 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; in getRealVLDOpcode()
8608 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; in getRealVLDOpcode()
8609 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; in getRealVLDOpcode()
8610 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; in getRealVLDOpcode()
8611 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8; in getRealVLDOpcode()
8612 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16; in getRealVLDOpcode()
8613 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32; in getRealVLDOpcode()
8614 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16; in getRealVLDOpcode()
8615 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32; in getRealVLDOpcode()
8618 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; in getRealVLDOpcode()
8619 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; in getRealVLDOpcode()
8620 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; in getRealVLDOpcode()
8621 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD; in getRealVLDOpcode()
8622 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD; in getRealVLDOpcode()
8623 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; in getRealVLDOpcode()
8624 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; in getRealVLDOpcode()
8625 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; in getRealVLDOpcode()
8626 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; in getRealVLDOpcode()
8627 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD; in getRealVLDOpcode()
8628 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD; in getRealVLDOpcode()
8629 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; in getRealVLDOpcode()
8630 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8; in getRealVLDOpcode()
8631 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16; in getRealVLDOpcode()
8632 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32; in getRealVLDOpcode()
8633 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8; in getRealVLDOpcode()
8634 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16; in getRealVLDOpcode()
8635 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32; in getRealVLDOpcode()
8638 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; in getRealVLDOpcode()
8639 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; in getRealVLDOpcode()
8640 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; in getRealVLDOpcode()
8641 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; in getRealVLDOpcode()
8642 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; in getRealVLDOpcode()
8643 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; in getRealVLDOpcode()
8644 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; in getRealVLDOpcode()
8645 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; in getRealVLDOpcode()
8646 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; in getRealVLDOpcode()
8647 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; in getRealVLDOpcode()
8648 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; in getRealVLDOpcode()
8649 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; in getRealVLDOpcode()
8650 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8; in getRealVLDOpcode()
8651 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16; in getRealVLDOpcode()
8652 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32; in getRealVLDOpcode()
8653 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8; in getRealVLDOpcode()
8654 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16; in getRealVLDOpcode()
8655 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32; in getRealVLDOpcode()
8675 case ARM::LDRT_POST: in processInstruction()
8676 case ARM::LDRBT_POST: { in processInstruction()
8678 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM in processInstruction()
8679 : ARM::LDRBT_POST_IMM; in processInstruction()
8693 case ARM::LDRSBTii: in processInstruction()
8694 case ARM::LDRHTii: in processInstruction()
8695 case ARM::LDRSHTii: { in processInstruction()
8698 if (Inst.getOpcode() == ARM::LDRSBTii) in processInstruction()
8699 TmpInst.setOpcode(ARM::LDRSBTi); in processInstruction()
8700 else if (Inst.getOpcode() == ARM::LDRHTii) in processInstruction()
8701 TmpInst.setOpcode(ARM::LDRHTi); in processInstruction()
8702 else if (Inst.getOpcode() == ARM::LDRSHTii) in processInstruction()
8703 TmpInst.setOpcode(ARM::LDRSHTi); in processInstruction()
8713 case ARM::STRT_POST: in processInstruction()
8714 case ARM::STRBT_POST: { in processInstruction()
8716 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM in processInstruction()
8717 : ARM::STRBT_POST_IMM; in processInstruction()
8731 case ARM::ADDri: { in processInstruction()
8732 if (Inst.getOperand(1).getReg() != ARM::PC || in processInstruction()
8737 TmpInst.setOpcode(ARM::ADR); in processInstruction()
8768 case ARM::t2LDR_PRE_imm: in processInstruction()
8769 case ARM::t2LDR_POST_imm: { in processInstruction()
8771 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2LDR_PRE_imm ? ARM::t2LDR_PRE in processInstruction()
8772 : ARM::t2LDR_POST); in processInstruction()
8782 case ARM::t2STR_PRE_imm: in processInstruction()
8783 case ARM::t2STR_POST_imm: { in processInstruction()
8785 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2STR_PRE_imm ? ARM::t2STR_PRE in processInstruction()
8786 : ARM::t2STR_POST); in processInstruction()
8796 case ARM::t2LDRpcrel: in processInstruction()
8801 Inst.setOpcode(ARM::tLDRpci); in processInstruction()
8803 Inst.setOpcode(ARM::t2LDRpci); in processInstruction()
8805 case ARM::t2LDRBpcrel: in processInstruction()
8806 Inst.setOpcode(ARM::t2LDRBpci); in processInstruction()
8808 case ARM::t2LDRHpcrel: in processInstruction()
8809 Inst.setOpcode(ARM::t2LDRHpci); in processInstruction()
8811 case ARM::t2LDRSBpcrel: in processInstruction()
8812 Inst.setOpcode(ARM::t2LDRSBpci); in processInstruction()
8814 case ARM::t2LDRSHpcrel: in processInstruction()
8815 Inst.setOpcode(ARM::t2LDRSHpci); in processInstruction()
8817 case ARM::LDRConstPool: in processInstruction()
8818 case ARM::tLDRConstPool: in processInstruction()
8819 case ARM::t2LDRConstPool: { in processInstruction()
8824 if (Inst.getOpcode() == ARM::LDRConstPool) in processInstruction()
8825 TmpInst.setOpcode(ARM::LDRi12); in processInstruction()
8826 else if (Inst.getOpcode() == ARM::tLDRConstPool) in processInstruction()
8827 TmpInst.setOpcode(ARM::tLDRpci); in processInstruction()
8828 else if (Inst.getOpcode() == ARM::t2LDRConstPool) in processInstruction()
8829 TmpInst.setOpcode(ARM::t2LDRpci); in processInstruction()
8837 Inst.getOperand(0).getReg() != ARM::PC && in processInstruction()
8838 Inst.getOperand(0).getReg() != ARM::SP) { in processInstruction()
8843 if (Inst.getOpcode() == ARM::LDRConstPool) { in processInstruction()
8847 TmpInst.setOpcode(ARM::MOVi); in processInstruction()
8851 TmpInst.setOpcode(ARM::MVNi); in processInstruction()
8855 TmpInst.setOpcode(ARM::MOVi16); in processInstruction()
8865 TmpInst.setOpcode(ARM::t2MOVi); in processInstruction()
8868 TmpInst.setOpcode(ARM::t2MVNi); in processInstruction()
8873 TmpInst.setOpcode(ARM::t2MOVi16); in processInstruction()
8896 if (TmpInst.getOpcode() == ARM::LDRi12) in processInstruction()
8904 case ARM::VST1LNdWB_register_Asm_8: in processInstruction()
8905 case ARM::VST1LNdWB_register_Asm_16: in processInstruction()
8906 case ARM::VST1LNdWB_register_Asm_32: { in processInstruction()
8924 case ARM::VST2LNdWB_register_Asm_8: in processInstruction()
8925 case ARM::VST2LNdWB_register_Asm_16: in processInstruction()
8926 case ARM::VST2LNdWB_register_Asm_32: in processInstruction()
8927 case ARM::VST2LNqWB_register_Asm_16: in processInstruction()
8928 case ARM::VST2LNqWB_register_Asm_32: { in processInstruction()
8948 case ARM::VST3LNdWB_register_Asm_8: in processInstruction()
8949 case ARM::VST3LNdWB_register_Asm_16: in processInstruction()
8950 case ARM::VST3LNdWB_register_Asm_32: in processInstruction()
8951 case ARM::VST3LNqWB_register_Asm_16: in processInstruction()
8952 case ARM::VST3LNqWB_register_Asm_32: { in processInstruction()
8974 case ARM::VST4LNdWB_register_Asm_8: in processInstruction()
8975 case ARM::VST4LNdWB_register_Asm_16: in processInstruction()
8976 case ARM::VST4LNdWB_register_Asm_32: in processInstruction()
8977 case ARM::VST4LNqWB_register_Asm_16: in processInstruction()
8978 case ARM::VST4LNqWB_register_Asm_32: { in processInstruction()
9002 case ARM::VST1LNdWB_fixed_Asm_8: in processInstruction()
9003 case ARM::VST1LNdWB_fixed_Asm_16: in processInstruction()
9004 case ARM::VST1LNdWB_fixed_Asm_32: { in processInstruction()
9022 case ARM::VST2LNdWB_fixed_Asm_8: in processInstruction()
9023 case ARM::VST2LNdWB_fixed_Asm_16: in processInstruction()
9024 case ARM::VST2LNdWB_fixed_Asm_32: in processInstruction()
9025 case ARM::VST2LNqWB_fixed_Asm_16: in processInstruction()
9026 case ARM::VST2LNqWB_fixed_Asm_32: { in processInstruction()
9046 case ARM::VST3LNdWB_fixed_Asm_8: in processInstruction()
9047 case ARM::VST3LNdWB_fixed_Asm_16: in processInstruction()
9048 case ARM::VST3LNdWB_fixed_Asm_32: in processInstruction()
9049 case ARM::VST3LNqWB_fixed_Asm_16: in processInstruction()
9050 case ARM::VST3LNqWB_fixed_Asm_32: { in processInstruction()
9072 case ARM::VST4LNdWB_fixed_Asm_8: in processInstruction()
9073 case ARM::VST4LNdWB_fixed_Asm_16: in processInstruction()
9074 case ARM::VST4LNdWB_fixed_Asm_32: in processInstruction()
9075 case ARM::VST4LNqWB_fixed_Asm_16: in processInstruction()
9076 case ARM::VST4LNqWB_fixed_Asm_32: { in processInstruction()
9100 case ARM::VST1LNdAsm_8: in processInstruction()
9101 case ARM::VST1LNdAsm_16: in processInstruction()
9102 case ARM::VST1LNdAsm_32: { in processInstruction()
9118 case ARM::VST2LNdAsm_8: in processInstruction()
9119 case ARM::VST2LNdAsm_16: in processInstruction()
9120 case ARM::VST2LNdAsm_32: in processInstruction()
9121 case ARM::VST2LNqAsm_16: in processInstruction()
9122 case ARM::VST2LNqAsm_32: { in processInstruction()
9140 case ARM::VST3LNdAsm_8: in processInstruction()
9141 case ARM::VST3LNdAsm_16: in processInstruction()
9142 case ARM::VST3LNdAsm_32: in processInstruction()
9143 case ARM::VST3LNqAsm_16: in processInstruction()
9144 case ARM::VST3LNqAsm_32: { in processInstruction()
9164 case ARM::VST4LNdAsm_8: in processInstruction()
9165 case ARM::VST4LNdAsm_16: in processInstruction()
9166 case ARM::VST4LNdAsm_32: in processInstruction()
9167 case ARM::VST4LNqAsm_16: in processInstruction()
9168 case ARM::VST4LNqAsm_32: { in processInstruction()
9191 case ARM::VLD1LNdWB_register_Asm_8: in processInstruction()
9192 case ARM::VLD1LNdWB_register_Asm_16: in processInstruction()
9193 case ARM::VLD1LNdWB_register_Asm_32: { in processInstruction()
9212 case ARM::VLD2LNdWB_register_Asm_8: in processInstruction()
9213 case ARM::VLD2LNdWB_register_Asm_16: in processInstruction()
9214 case ARM::VLD2LNdWB_register_Asm_32: in processInstruction()
9215 case ARM::VLD2LNqWB_register_Asm_16: in processInstruction()
9216 case ARM::VLD2LNqWB_register_Asm_32: { in processInstruction()
9239 case ARM::VLD3LNdWB_register_Asm_8: in processInstruction()
9240 case ARM::VLD3LNdWB_register_Asm_16: in processInstruction()
9241 case ARM::VLD3LNdWB_register_Asm_32: in processInstruction()
9242 case ARM::VLD3LNqWB_register_Asm_16: in processInstruction()
9243 case ARM::VLD3LNqWB_register_Asm_32: { in processInstruction()
9270 case ARM::VLD4LNdWB_register_Asm_8: in processInstruction()
9271 case ARM::VLD4LNdWB_register_Asm_16: in processInstruction()
9272 case ARM::VLD4LNdWB_register_Asm_32: in processInstruction()
9273 case ARM::VLD4LNqWB_register_Asm_16: in processInstruction()
9274 case ARM::VLD4LNqWB_register_Asm_32: { in processInstruction()
9305 case ARM::VLD1LNdWB_fixed_Asm_8: in processInstruction()
9306 case ARM::VLD1LNdWB_fixed_Asm_16: in processInstruction()
9307 case ARM::VLD1LNdWB_fixed_Asm_32: { in processInstruction()
9326 case ARM::VLD2LNdWB_fixed_Asm_8: in processInstruction()
9327 case ARM::VLD2LNdWB_fixed_Asm_16: in processInstruction()
9328 case ARM::VLD2LNdWB_fixed_Asm_32: in processInstruction()
9329 case ARM::VLD2LNqWB_fixed_Asm_16: in processInstruction()
9330 case ARM::VLD2LNqWB_fixed_Asm_32: { in processInstruction()
9353 case ARM::VLD3LNdWB_fixed_Asm_8: in processInstruction()
9354 case ARM::VLD3LNdWB_fixed_Asm_16: in processInstruction()
9355 case ARM::VLD3LNdWB_fixed_Asm_32: in processInstruction()
9356 case ARM::VLD3LNqWB_fixed_Asm_16: in processInstruction()
9357 case ARM::VLD3LNqWB_fixed_Asm_32: { in processInstruction()
9384 case ARM::VLD4LNdWB_fixed_Asm_8: in processInstruction()
9385 case ARM::VLD4LNdWB_fixed_Asm_16: in processInstruction()
9386 case ARM::VLD4LNdWB_fixed_Asm_32: in processInstruction()
9387 case ARM::VLD4LNqWB_fixed_Asm_16: in processInstruction()
9388 case ARM::VLD4LNqWB_fixed_Asm_32: { in processInstruction()
9419 case ARM::VLD1LNdAsm_8: in processInstruction()
9420 case ARM::VLD1LNdAsm_16: in processInstruction()
9421 case ARM::VLD1LNdAsm_32: { in processInstruction()
9438 case ARM::VLD2LNdAsm_8: in processInstruction()
9439 case ARM::VLD2LNdAsm_16: in processInstruction()
9440 case ARM::VLD2LNdAsm_32: in processInstruction()
9441 case ARM::VLD2LNqAsm_16: in processInstruction()
9442 case ARM::VLD2LNqAsm_32: { in processInstruction()
9463 case ARM::VLD3LNdAsm_8: in processInstruction()
9464 case ARM::VLD3LNdAsm_16: in processInstruction()
9465 case ARM::VLD3LNdAsm_32: in processInstruction()
9466 case ARM::VLD3LNqAsm_16: in processInstruction()
9467 case ARM::VLD3LNqAsm_32: { in processInstruction()
9492 case ARM::VLD4LNdAsm_8: in processInstruction()
9493 case ARM::VLD4LNdAsm_16: in processInstruction()
9494 case ARM::VLD4LNdAsm_32: in processInstruction()
9495 case ARM::VLD4LNqAsm_16: in processInstruction()
9496 case ARM::VLD4LNqAsm_32: { in processInstruction()
9526 case ARM::VLD3DUPdAsm_8: in processInstruction()
9527 case ARM::VLD3DUPdAsm_16: in processInstruction()
9528 case ARM::VLD3DUPdAsm_32: in processInstruction()
9529 case ARM::VLD3DUPqAsm_8: in processInstruction()
9530 case ARM::VLD3DUPqAsm_16: in processInstruction()
9531 case ARM::VLD3DUPqAsm_32: { in processInstruction()
9548 case ARM::VLD3DUPdWB_fixed_Asm_8: in processInstruction()
9549 case ARM::VLD3DUPdWB_fixed_Asm_16: in processInstruction()
9550 case ARM::VLD3DUPdWB_fixed_Asm_32: in processInstruction()
9551 case ARM::VLD3DUPqWB_fixed_Asm_8: in processInstruction()
9552 case ARM::VLD3DUPqWB_fixed_Asm_16: in processInstruction()
9553 case ARM::VLD3DUPqWB_fixed_Asm_32: { in processInstruction()
9572 case ARM::VLD3DUPdWB_register_Asm_8: in processInstruction()
9573 case ARM::VLD3DUPdWB_register_Asm_16: in processInstruction()
9574 case ARM::VLD3DUPdWB_register_Asm_32: in processInstruction()
9575 case ARM::VLD3DUPqWB_register_Asm_8: in processInstruction()
9576 case ARM::VLD3DUPqWB_register_Asm_16: in processInstruction()
9577 case ARM::VLD3DUPqWB_register_Asm_32: { in processInstruction()
9597 case ARM::VLD3dAsm_8: in processInstruction()
9598 case ARM::VLD3dAsm_16: in processInstruction()
9599 case ARM::VLD3dAsm_32: in processInstruction()
9600 case ARM::VLD3qAsm_8: in processInstruction()
9601 case ARM::VLD3qAsm_16: in processInstruction()
9602 case ARM::VLD3qAsm_32: { in processInstruction()
9619 case ARM::VLD3dWB_fixed_Asm_8: in processInstruction()
9620 case ARM::VLD3dWB_fixed_Asm_16: in processInstruction()
9621 case ARM::VLD3dWB_fixed_Asm_32: in processInstruction()
9622 case ARM::VLD3qWB_fixed_Asm_8: in processInstruction()
9623 case ARM::VLD3qWB_fixed_Asm_16: in processInstruction()
9624 case ARM::VLD3qWB_fixed_Asm_32: { in processInstruction()
9643 case ARM::VLD3dWB_register_Asm_8: in processInstruction()
9644 case ARM::VLD3dWB_register_Asm_16: in processInstruction()
9645 case ARM::VLD3dWB_register_Asm_32: in processInstruction()
9646 case ARM::VLD3qWB_register_Asm_8: in processInstruction()
9647 case ARM::VLD3qWB_register_Asm_16: in processInstruction()
9648 case ARM::VLD3qWB_register_Asm_32: { in processInstruction()
9668 case ARM::VLD4DUPdAsm_8: in processInstruction()
9669 case ARM::VLD4DUPdAsm_16: in processInstruction()
9670 case ARM::VLD4DUPdAsm_32: in processInstruction()
9671 case ARM::VLD4DUPqAsm_8: in processInstruction()
9672 case ARM::VLD4DUPqAsm_16: in processInstruction()
9673 case ARM::VLD4DUPqAsm_32: { in processInstruction()
9692 case ARM::VLD4DUPdWB_fixed_Asm_8: in processInstruction()
9693 case ARM::VLD4DUPdWB_fixed_Asm_16: in processInstruction()
9694 case ARM::VLD4DUPdWB_fixed_Asm_32: in processInstruction()
9695 case ARM::VLD4DUPqWB_fixed_Asm_8: in processInstruction()
9696 case ARM::VLD4DUPqWB_fixed_Asm_16: in processInstruction()
9697 case ARM::VLD4DUPqWB_fixed_Asm_32: { in processInstruction()
9718 case ARM::VLD4DUPdWB_register_Asm_8: in processInstruction()
9719 case ARM::VLD4DUPdWB_register_Asm_16: in processInstruction()
9720 case ARM::VLD4DUPdWB_register_Asm_32: in processInstruction()
9721 case ARM::VLD4DUPqWB_register_Asm_8: in processInstruction()
9722 case ARM::VLD4DUPqWB_register_Asm_16: in processInstruction()
9723 case ARM::VLD4DUPqWB_register_Asm_32: { in processInstruction()
9745 case ARM::VLD4dAsm_8: in processInstruction()
9746 case ARM::VLD4dAsm_16: in processInstruction()
9747 case ARM::VLD4dAsm_32: in processInstruction()
9748 case ARM::VLD4qAsm_8: in processInstruction()
9749 case ARM::VLD4qAsm_16: in processInstruction()
9750 case ARM::VLD4qAsm_32: { in processInstruction()
9769 case ARM::VLD4dWB_fixed_Asm_8: in processInstruction()
9770 case ARM::VLD4dWB_fixed_Asm_16: in processInstruction()
9771 case ARM::VLD4dWB_fixed_Asm_32: in processInstruction()
9772 case ARM::VLD4qWB_fixed_Asm_8: in processInstruction()
9773 case ARM::VLD4qWB_fixed_Asm_16: in processInstruction()
9774 case ARM::VLD4qWB_fixed_Asm_32: { in processInstruction()
9795 case ARM::VLD4dWB_register_Asm_8: in processInstruction()
9796 case ARM::VLD4dWB_register_Asm_16: in processInstruction()
9797 case ARM::VLD4dWB_register_Asm_32: in processInstruction()
9798 case ARM::VLD4qWB_register_Asm_8: in processInstruction()
9799 case ARM::VLD4qWB_register_Asm_16: in processInstruction()
9800 case ARM::VLD4qWB_register_Asm_32: { in processInstruction()
9822 case ARM::VST3dAsm_8: in processInstruction()
9823 case ARM::VST3dAsm_16: in processInstruction()
9824 case ARM::VST3dAsm_32: in processInstruction()
9825 case ARM::VST3qAsm_8: in processInstruction()
9826 case ARM::VST3qAsm_16: in processInstruction()
9827 case ARM::VST3qAsm_32: { in processInstruction()
9844 case ARM::VST3dWB_fixed_Asm_8: in processInstruction()
9845 case ARM::VST3dWB_fixed_Asm_16: in processInstruction()
9846 case ARM::VST3dWB_fixed_Asm_32: in processInstruction()
9847 case ARM::VST3qWB_fixed_Asm_8: in processInstruction()
9848 case ARM::VST3qWB_fixed_Asm_16: in processInstruction()
9849 case ARM::VST3qWB_fixed_Asm_32: { in processInstruction()
9868 case ARM::VST3dWB_register_Asm_8: in processInstruction()
9869 case ARM::VST3dWB_register_Asm_16: in processInstruction()
9870 case ARM::VST3dWB_register_Asm_32: in processInstruction()
9871 case ARM::VST3qWB_register_Asm_8: in processInstruction()
9872 case ARM::VST3qWB_register_Asm_16: in processInstruction()
9873 case ARM::VST3qWB_register_Asm_32: { in processInstruction()
9893 case ARM::VST4dAsm_8: in processInstruction()
9894 case ARM::VST4dAsm_16: in processInstruction()
9895 case ARM::VST4dAsm_32: in processInstruction()
9896 case ARM::VST4qAsm_8: in processInstruction()
9897 case ARM::VST4qAsm_16: in processInstruction()
9898 case ARM::VST4qAsm_32: { in processInstruction()
9917 case ARM::VST4dWB_fixed_Asm_8: in processInstruction()
9918 case ARM::VST4dWB_fixed_Asm_16: in processInstruction()
9919 case ARM::VST4dWB_fixed_Asm_32: in processInstruction()
9920 case ARM::VST4qWB_fixed_Asm_8: in processInstruction()
9921 case ARM::VST4qWB_fixed_Asm_16: in processInstruction()
9922 case ARM::VST4qWB_fixed_Asm_32: { in processInstruction()
9943 case ARM::VST4dWB_register_Asm_8: in processInstruction()
9944 case ARM::VST4dWB_register_Asm_16: in processInstruction()
9945 case ARM::VST4dWB_register_Asm_32: in processInstruction()
9946 case ARM::VST4qWB_register_Asm_8: in processInstruction()
9947 case ARM::VST4qWB_register_Asm_16: in processInstruction()
9948 case ARM::VST4qWB_register_Asm_32: { in processInstruction()
9970 case ARM::t2LSLri: in processInstruction()
9971 case ARM::t2LSRri: in processInstruction()
9972 case ARM::t2ASRri: in processInstruction()
9975 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && in processInstruction()
9980 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break; in processInstruction()
9981 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break; in processInstruction()
9982 case ARM::t2ASRri: NewOpc = ARM::tASRri; break; in processInstruction()
9999 case ARM::t2MOVsr: in processInstruction()
10000 case ARM::t2MOVSsr: { in processInstruction()
10009 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr) && in processInstruction()
10016 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break; in processInstruction()
10017 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break; in processInstruction()
10018 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break; in processInstruction()
10019 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break; in processInstruction()
10025 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); in processInstruction()
10032 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); in processInstruction()
10036 case ARM::t2MOVsi: in processInstruction()
10037 case ARM::t2MOVSsi: { in processInstruction()
10044 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi) && in processInstruction()
10062 newOpc = isNarrow ? ARM::tMOVSr : ARM::t2MOVr; in processInstruction()
10066 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break; in processInstruction()
10067 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break; in processInstruction()
10068 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break; in processInstruction()
10069 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break; in processInstruction()
10070 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break; in processInstruction()
10078 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); in processInstruction()
10080 if (newOpc != ARM::t2RRX && !isMov) in processInstruction()
10086 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); in processInstruction()
10091 case ARM::ASRr: in processInstruction()
10092 case ARM::LSRr: in processInstruction()
10093 case ARM::LSLr: in processInstruction()
10094 case ARM::RORr: { in processInstruction()
10098 case ARM::ASRr: ShiftTy = ARM_AM::asr; break; in processInstruction()
10099 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break; in processInstruction()
10100 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break; in processInstruction()
10101 case ARM::RORr: ShiftTy = ARM_AM::ror; break; in processInstruction()
10105 TmpInst.setOpcode(ARM::MOVsr); in processInstruction()
10116 case ARM::ASRi: in processInstruction()
10117 case ARM::LSRi: in processInstruction()
10118 case ARM::LSLi: in processInstruction()
10119 case ARM::RORi: { in processInstruction()
10123 case ARM::ASRi: ShiftTy = ARM_AM::asr; break; in processInstruction()
10124 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break; in processInstruction()
10125 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break; in processInstruction()
10126 case ARM::RORi: ShiftTy = ARM_AM::ror; break; in processInstruction()
10130 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi; in processInstruction()
10139 if (Opc == ARM::MOVsi) in processInstruction()
10147 case ARM::RRXi: { in processInstruction()
10150 TmpInst.setOpcode(ARM::MOVsi); in processInstruction()
10160 case ARM::t2LDMIA_UPD: { in processInstruction()
10166 TmpInst.setOpcode(ARM::t2LDR_POST); in processInstruction()
10176 case ARM::t2STMDB_UPD: { in processInstruction()
10182 TmpInst.setOpcode(ARM::t2STR_PRE); in processInstruction()
10192 case ARM::LDMIA_UPD: in processInstruction()
10198 TmpInst.setOpcode(ARM::LDR_POST_IMM); in processInstruction()
10210 case ARM::STMDB_UPD: in processInstruction()
10216 TmpInst.setOpcode(ARM::STR_PRE_IMM); in processInstruction()
10226 case ARM::t2ADDri12: in processInstruction()
10227 case ARM::t2SUBri12: in processInstruction()
10228 case ARM::t2ADDspImm12: in processInstruction()
10229 case ARM::t2SUBspImm12: { in processInstruction()
10237 case ARM::t2ADDri12: in processInstruction()
10238 Inst.setOpcode(ARM::t2ADDri); in processInstruction()
10240 case ARM::t2SUBri12: in processInstruction()
10241 Inst.setOpcode(ARM::t2SUBri); in processInstruction()
10243 case ARM::t2ADDspImm12: in processInstruction()
10244 Inst.setOpcode(ARM::t2ADDspImm); in processInstruction()
10246 case ARM::t2SUBspImm12: in processInstruction()
10247 Inst.setOpcode(ARM::t2SUBspImm); in processInstruction()
10254 case ARM::tADDi8: in processInstruction()
10260 Inst.setOpcode(ARM::tADDi3); in processInstruction()
10264 case ARM::tSUBi8: in processInstruction()
10270 Inst.setOpcode(ARM::tSUBi3); in processInstruction()
10274 case ARM::t2ADDri: in processInstruction()
10275 case ARM::t2SUBri: { in processInstruction()
10284 Inst.getOperand(5).getReg() != (inITBlock() ? 0 : ARM::CPSR) || in processInstruction()
10288 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ? in processInstruction()
10289 ARM::tADDi8 : ARM::tSUBi8); in processInstruction()
10299 case ARM::t2ADDspImm: in processInstruction()
10300 case ARM::t2SUBspImm: { in processInstruction()
10308 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDspImm ? ARM::tADDspi in processInstruction()
10309 : ARM::tSUBspi); in processInstruction()
10310 TmpInst.addOperand(MCOperand::createReg(ARM::SP)); // destination reg in processInstruction()
10311 TmpInst.addOperand(MCOperand::createReg(ARM::SP)); // source reg in processInstruction()
10318 case ARM::t2ADDrr: { in processInstruction()
10336 TmpInst.setOpcode(ARM::tADDhirr); in processInstruction()
10345 case ARM::tADDrSP: in processInstruction()
10349 Inst.setOpcode(ARM::t2ADDrr); in processInstruction()
10354 case ARM::tB: in processInstruction()
10357 Inst.setOpcode(ARM::tBcc); in processInstruction()
10361 case ARM::t2B: in processInstruction()
10364 Inst.setOpcode(ARM::t2Bcc); in processInstruction()
10368 case ARM::t2Bcc: in processInstruction()
10371 Inst.setOpcode(ARM::t2B); in processInstruction()
10375 case ARM::tBcc: in processInstruction()
10378 Inst.setOpcode(ARM::tB); in processInstruction()
10382 case ARM::tLDMIA: { in processInstruction()
10397 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA); in processInstruction()
10407 case ARM::tSTMIA_UPD: { in processInstruction()
10416 Inst.setOpcode(ARM::t2STMIA_UPD); in processInstruction()
10421 case ARM::tPOP: { in processInstruction()
10426 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase)) in processInstruction()
10429 Inst.setOpcode(ARM::t2LDMIA_UPD); in processInstruction()
10431 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); in processInstruction()
10432 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); in processInstruction()
10435 case ARM::tPUSH: { in processInstruction()
10437 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase)) in processInstruction()
10440 Inst.setOpcode(ARM::t2STMDB_UPD); in processInstruction()
10442 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); in processInstruction()
10443 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); in processInstruction()
10446 case ARM::t2MOVi: in processInstruction()
10452 Inst.getOperand(4).getReg() == (inITBlock() ? 0 : ARM::CPSR) && in processInstruction()
10456 TmpInst.setOpcode(ARM::tMOVi8); in processInstruction()
10467 case ARM::t2MOVr: in processInstruction()
10473 Inst.getOperand(4).getReg() == ARM::CPSR && in processInstruction()
10477 unsigned Op = Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr; in processInstruction()
10481 if (Op == ARM::tMOVr) { in processInstruction()
10490 case ARM::t2SXTH: in processInstruction()
10491 case ARM::t2SXTB: in processInstruction()
10492 case ARM::t2UXTH: in processInstruction()
10493 case ARM::t2UXTB: in processInstruction()
10503 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; in processInstruction()
10504 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; in processInstruction()
10505 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; in processInstruction()
10506 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break; in processInstruction()
10520 case ARM::MOVsi: { in processInstruction()
10528 TmpInst.setOpcode(ARM::MOVr); in processInstruction()
10539 case ARM::ANDrsi: in processInstruction()
10540 case ARM::ORRrsi: in processInstruction()
10541 case ARM::EORrsi: in processInstruction()
10542 case ARM::BICrsi: in processInstruction()
10543 case ARM::SUBrsi: in processInstruction()
10544 case ARM::ADDrsi: { in processInstruction()
10550 case ARM::ANDrsi: newOpc = ARM::ANDrr; break; in processInstruction()
10551 case ARM::ORRrsi: newOpc = ARM::ORRrr; break; in processInstruction()
10552 case ARM::EORrsi: newOpc = ARM::EORrr; break; in processInstruction()
10553 case ARM::BICrsi: newOpc = ARM::BICrr; break; in processInstruction()
10554 case ARM::SUBrsi: newOpc = ARM::SUBrr; break; in processInstruction()
10555 case ARM::ADDrsi: newOpc = ARM::ADDrr; break; in processInstruction()
10574 case ARM::ITasm: in processInstruction()
10575 case ARM::t2IT: { in processInstruction()
10583 case ARM::t2LSLrr: in processInstruction()
10584 case ARM::t2LSRrr: in processInstruction()
10585 case ARM::t2ASRrr: in processInstruction()
10586 case ARM::t2SBCrr: in processInstruction()
10587 case ARM::t2RORrr: in processInstruction()
10588 case ARM::t2BICrr: in processInstruction()
10593 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && in processInstruction()
10598 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break; in processInstruction()
10599 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break; in processInstruction()
10600 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break; in processInstruction()
10601 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break; in processInstruction()
10602 case ARM::t2RORrr: NewOpc = ARM::tROR; break; in processInstruction()
10603 case ARM::t2BICrr: NewOpc = ARM::tBIC; break; in processInstruction()
10618 case ARM::t2ANDrr: in processInstruction()
10619 case ARM::t2EORrr: in processInstruction()
10620 case ARM::t2ADCrr: in processInstruction()
10621 case ARM::t2ORRrr: in processInstruction()
10629 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && in processInstruction()
10634 case ARM::t2ADCrr: NewOpc = ARM::tADC; break; in processInstruction()
10635 case ARM::t2ANDrr: NewOpc = ARM::tAND; break; in processInstruction()
10636 case ARM::t2EORrr: NewOpc = ARM::tEOR; break; in processInstruction()
10637 case ARM::t2ORRrr: NewOpc = ARM::tORR; break; in processInstruction()
10656 case ARM::MVE_VPST: in processInstruction()
10657 case ARM::MVE_VPTv16i8: in processInstruction()
10658 case ARM::MVE_VPTv8i16: in processInstruction()
10659 case ARM::MVE_VPTv4i32: in processInstruction()
10660 case ARM::MVE_VPTv16u8: in processInstruction()
10661 case ARM::MVE_VPTv8u16: in processInstruction()
10662 case ARM::MVE_VPTv4u32: in processInstruction()
10663 case ARM::MVE_VPTv16s8: in processInstruction()
10664 case ARM::MVE_VPTv8s16: in processInstruction()
10665 case ARM::MVE_VPTv4s32: in processInstruction()
10666 case ARM::MVE_VPTv4f32: in processInstruction()
10667 case ARM::MVE_VPTv8f16: in processInstruction()
10668 case ARM::MVE_VPTv16i8r: in processInstruction()
10669 case ARM::MVE_VPTv8i16r: in processInstruction()
10670 case ARM::MVE_VPTv4i32r: in processInstruction()
10671 case ARM::MVE_VPTv16u8r: in processInstruction()
10672 case ARM::MVE_VPTv8u16r: in processInstruction()
10673 case ARM::MVE_VPTv4u32r: in processInstruction()
10674 case ARM::MVE_VPTv16s8r: in processInstruction()
10675 case ARM::MVE_VPTv8s16r: in processInstruction()
10676 case ARM::MVE_VPTv4s32r: in processInstruction()
10677 case ARM::MVE_VPTv4f32r: in processInstruction()
10678 case ARM::MVE_VPTv8f16r: { in processInstruction()
10706 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) in checkTargetMatchPredicate()
10710 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && in checkTargetMatchPredicate()
10713 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && in checkTargetMatchPredicate()
10717 if (Opc == ARM::tLSLri && Inst.getOperand(3).getImm() == 0 && inITBlock()) in checkTargetMatchPredicate()
10722 if (Opc == ARM::tADDhirr && !hasV6MOps() && in checkTargetMatchPredicate()
10727 else if (Opc == ARM::tMOVr && !hasV6Ops() && in checkTargetMatchPredicate()
10736 if (Opc == ARM::t2MOVr && !hasV8Ops()) in checkTargetMatchPredicate()
10739 if (Inst.getOperand(0).getReg() == ARM::SP && in checkTargetMatchPredicate()
10740 Inst.getOperand(1).getReg() == ARM::SP) in checkTargetMatchPredicate()
10743 if (Inst.getOperand(4).getReg() == ARM::CPSR && in checkTargetMatchPredicate()
10744 (Inst.getOperand(0).getReg() == ARM::SP || in checkTargetMatchPredicate()
10745 Inst.getOperand(1).getReg() == ARM::SP)) in checkTargetMatchPredicate()
10750 case ARM::VMRS: in checkTargetMatchPredicate()
10751 case ARM::VMSR: in checkTargetMatchPredicate()
10752 case ARM::VMRS_FPCXTS: in checkTargetMatchPredicate()
10753 case ARM::VMRS_FPCXTNS: in checkTargetMatchPredicate()
10754 case ARM::VMSR_FPCXTS: in checkTargetMatchPredicate()
10755 case ARM::VMSR_FPCXTNS: in checkTargetMatchPredicate()
10756 case ARM::VMRS_FPSCR_NZCVQC: in checkTargetMatchPredicate()
10757 case ARM::VMSR_FPSCR_NZCVQC: in checkTargetMatchPredicate()
10758 case ARM::FMSTAT: in checkTargetMatchPredicate()
10759 case ARM::VMRS_VPR: in checkTargetMatchPredicate()
10760 case ARM::VMRS_P0: in checkTargetMatchPredicate()
10761 case ARM::VMSR_VPR: in checkTargetMatchPredicate()
10762 case ARM::VMSR_P0: in checkTargetMatchPredicate()
10765 if (Inst.getOperand(0).isReg() && Inst.getOperand(0).getReg() == ARM::SP && in checkTargetMatchPredicate()
10769 case ARM::t2TBB: in checkTargetMatchPredicate()
10770 case ARM::t2TBH: in checkTargetMatchPredicate()
10772 if (!hasV8Ops() && (Inst.getOperand(0).getReg() == ARM::SP)) in checkTargetMatchPredicate()
10780 if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) { in checkTargetMatchPredicate()
10796 if ((Reg == ARM::SP) && !hasV8Ops()) in checkTargetMatchPredicate()
10798 else if (Reg == ARM::PC) in checkTargetMatchPredicate()
10820 if (MCID.isTerminator() || (MCID.isCall() && Inst.getOpcode() != ARM::tSVC) || in isITBlockTerminator()
10826 if (MCID.hasDefOfPhysReg(Inst, ARM::PC, *MRI)) in isITBlockTerminator()
10880 if (Inst.getOpcode() == ARM::tBcc || Inst.getOpcode() == ARM::t2Bcc) { in MatchInstruction()
10976 if (Inst.getOpcode() == ARM::ITasm) in MatchAndEmitInstruction()
11302 ARM::ArchKind ID = ARM::parseArch(Arch); in parseDirectiveArch()
11304 if (ID == ARM::ArchKind::INVALID) in parseDirectiveArch()
11311 ("+" + ARM::getArchName(ID)).str()); in parseDirectiveArch()
11437 unsigned ID = ARM::parseFPU(FPU); in parseDirectiveFPU()
11439 if (!ARM::getFPUFeatures(ID, Features)) in parseDirectiveFPU()
11602 check(SPReg != ARM::SP && SPReg != UC.getFPReg(), SPRegLoc, in parseDirectiveSetFP()
11831 if (CE->getValue() < 0 || CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) in parseDirectivePersonalityIndex()
11918 if (UC.getFPReg() != ARM::SP) in parseDirectiveMovSP()
11925 if (SPReg == ARM::SP || SPReg == ARM::PC) in parseDirectiveMovSP()
11967 ARM::ArchKind ID = ARM::parseArch(Arch); in parseDirectiveObjectArch()
11969 if (ID == ARM::ArchKind::INVALID) in parseDirectiveObjectArch()
12244 {ARM::AEK_CRC, {Feature_HasV8Bit}, {ARM::FeatureCRC}}, in enableArchExtFeature()
12245 {ARM::AEK_AES, in enableArchExtFeature()
12247 {ARM::FeatureAES, ARM::FeatureNEON, ARM::FeatureFPARMv8}}, in enableArchExtFeature()
12248 {ARM::AEK_SHA2, in enableArchExtFeature()
12250 {ARM::FeatureSHA2, ARM::FeatureNEON, ARM::FeatureFPARMv8}}, in enableArchExtFeature()
12251 {ARM::AEK_CRYPTO, in enableArchExtFeature()
12253 {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8}}, in enableArchExtFeature()
12254 {ARM::AEK_FP, in enableArchExtFeature()
12256 {ARM::FeatureVFP2_SP, ARM::FeatureFPARMv8}}, in enableArchExtFeature()
12257 {(ARM::AEK_HWDIVTHUMB | ARM::AEK_HWDIVARM), in enableArchExtFeature()
12259 {ARM::FeatureHWDivThumb, ARM::FeatureHWDivARM}}, in enableArchExtFeature()
12260 {ARM::AEK_MP, in enableArchExtFeature()
12262 {ARM::FeatureMP}}, in enableArchExtFeature()
12263 {ARM::AEK_SIMD, in enableArchExtFeature()
12265 {ARM::FeatureNEON, ARM::FeatureVFP2_SP, ARM::FeatureFPARMv8}}, in enableArchExtFeature()
12266 {ARM::AEK_SEC, {Feature_HasV6KBit}, {ARM::FeatureTrustZone}}, in enableArchExtFeature()
12268 {ARM::AEK_VIRT, {Feature_HasV7Bit}, {ARM::FeatureVirtualization}}, in enableArchExtFeature()
12269 {ARM::AEK_FP16, in enableArchExtFeature()
12271 {ARM::FeatureFPARMv8, ARM::FeatureFullFP16}}, in enableArchExtFeature()
12272 {ARM::AEK_RAS, {Feature_HasV8Bit}, {ARM::FeatureRAS}}, in enableArchExtFeature()
12273 {ARM::AEK_LOB, {Feature_HasV8_1MMainlineBit}, {ARM::FeatureLOB}}, in enableArchExtFeature()
12275 {ARM::AEK_OS, {}, {}}, in enableArchExtFeature()
12276 {ARM::AEK_IWMMXT, {}, {}}, in enableArchExtFeature()
12277 {ARM::AEK_IWMMXT2, {}, {}}, in enableArchExtFeature()
12278 {ARM::AEK_MAVERICK, {}, {}}, in enableArchExtFeature()
12279 {ARM::AEK_XSCALE, {}, {}}, in enableArchExtFeature()
12286 uint64_t FeatureKind = ARM::parseArchExt(Name); in enableArchExtFeature()
12287 if (FeatureKind == ARM::AEK_INVALID) in enableArchExtFeature()
12383 if (hasV8Ops() && Op.isReg() && Op.getReg() == ARM::SP) in validateTargetOperandClass()
12388 MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg())) in validateTargetOperandClass()