86       ProduceSB ? (ST->isThumb() ? ARM::t2SpeculationBarrierSBEndBB  in insertSpeculationBarrier()
87                                  : ARM::SpeculationBarrierSBEndBB)  in insertSpeculationBarrier()
88                 : (ST->isThumb() ? ARM::t2SpeculationBarrierISBDSBEndBB  in insertSpeculationBarrier()
89                                  : ARM::SpeculationBarrierISBDSBEndBB);  in insertSpeculationBarrier()
134     {"__llvm_slsblr_thunk_arm_r0", ARM::R0, false},
135     {"__llvm_slsblr_thunk_arm_r1", ARM::R1, false},
136     {"__llvm_slsblr_thunk_arm_r2", ARM::R2, false},
137     {"__llvm_slsblr_thunk_arm_r3", ARM::R3, false},
138     {"__llvm_slsblr_thunk_arm_r4", ARM::R4, false},
139     {"__llvm_slsblr_thunk_arm_r5", ARM::R5, false},
140     {"__llvm_slsblr_thunk_arm_r6", ARM::R6, false},
141     {"__llvm_slsblr_thunk_arm_r7", ARM::R7, false},
142     {"__llvm_slsblr_thunk_arm_r8", ARM::R8, false},
143     {"__llvm_slsblr_thunk_arm_r9", ARM::R9, false},
144     {"__llvm_slsblr_thunk_arm_r10", ARM::R10, false},
145     {"__llvm_slsblr_thunk_arm_r11", ARM::R11, false},
146     {"__llvm_slsblr_thunk_arm_sp", ARM::SP, false},
147     {"__llvm_slsblr_thunk_arm_pc", ARM::PC, false},
148     {"__llvm_slsblr_thunk_thumb_r0", ARM::R0, true},
149     {"__llvm_slsblr_thunk_thumb_r1", ARM::R1, true},
150     {"__llvm_slsblr_thunk_thumb_r2", ARM::R2, true},
151     {"__llvm_slsblr_thunk_thumb_r3", ARM::R3, true},
152     {"__llvm_slsblr_thunk_thumb_r4", ARM::R4, true},
153     {"__llvm_slsblr_thunk_thumb_r5", ARM::R5, true},
154     {"__llvm_slsblr_thunk_thumb_r6", ARM::R6, true},
155     {"__llvm_slsblr_thunk_thumb_r7", ARM::R7, true},
156     {"__llvm_slsblr_thunk_thumb_r8", ARM::R8, true},
157     {"__llvm_slsblr_thunk_thumb_r9", ARM::R9, true},
158     {"__llvm_slsblr_thunk_thumb_r10", ARM::R10, true},
159     {"__llvm_slsblr_thunk_thumb_r11", ARM::R11, true},
160     {"__llvm_slsblr_thunk_thumb_sp", ARM::SP, true},
161     {"__llvm_slsblr_thunk_thumb_pc", ARM::PC, true},
209     BuildMI(Entry, DebugLoc(), TII->get(ARM::tBX))  in populateThunk()
213     BuildMI(Entry, DebugLoc(), TII->get(ARM::BX))  in populateThunk()
260   case ARM::BLX:   // !isThumb2  in ConvertIndirectCallToIndirectJump()
261   case ARM::BLX_noip:   // !isThumb2  in ConvertIndirectCallToIndirectJump()
265   case ARM::tBLXr:      // isThumb2  in ConvertIndirectCallToIndirectJump()
266   case ARM::tBLXr_noip: // isThumb2  in ConvertIndirectCallToIndirectJump()
281   assert(Reg != ARM::R12 && Reg != ARM::LR);  in ConvertIndirectCallToIndirectJump()
295       isThumb ? BuildMI(MBB, MBBI, DL, TII->get(ARM::tBL))  in ConvertIndirectCallToIndirectJump()
299               : BuildMI(MBB, MBBI, DL, TII->get(ARM::BL)).addGlobalAddress(GV);  in ConvertIndirectCallToIndirectJump()
316     if (Op.getReg() == ARM::LR && Op.isDef())  in ConvertIndirectCallToIndirectJump()
318     if (Op.getReg() == ARM::SP && !Op.isDef())  in ConvertIndirectCallToIndirectJump()