Lines Matching refs:ARM
251 IsTailCallReturn = RetOpcode == ARM::TCRETURNdi || in getArgumentStackToRestore()
252 RetOpcode == ARM::TCRETURNri; in getArgumentStackToRestore()
294 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes, in emitSPUpdate()
301 case ARM::VSTMDDB_UPD: in sizeOfSPAdjustment()
304 case ARM::STMDB_UPD: in sizeOfSPAdjustment()
305 case ARM::t2STMDB_UPD: in sizeOfSPAdjustment()
308 case ARM::t2STR_PRE: in sizeOfSPAdjustment()
309 case ARM::STR_PRE_IMM: in sizeOfSPAdjustment()
412 BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg) in emitAligningInstructions()
417 BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg) in emitAligningInstructions()
427 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) in emitAligningInstructions()
432 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) in emitAligningInstructions()
442 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2BFC), Reg) in emitAligningInstructions()
530 case ARM::R8: in emitPrologue()
531 case ARM::R9: in emitPrologue()
532 case ARM::R10: in emitPrologue()
533 case ARM::R11: in emitPrologue()
534 case ARM::R12: in emitPrologue()
540 case ARM::R0: in emitPrologue()
541 case ARM::R1: in emitPrologue()
542 case ARM::R2: in emitPrologue()
543 case ARM::R3: in emitPrologue()
544 case ARM::R4: in emitPrologue()
545 case ARM::R5: in emitPrologue()
546 case ARM::R6: in emitPrologue()
547 case ARM::R7: in emitPrologue()
548 case ARM::LR: in emitPrologue()
553 case ARM::FPCXTNS: in emitPrologue()
558 if (Reg == ARM::D8) in emitPrologue()
560 if (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs()) in emitPrologue()
625 while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::VSTMDDB_UPD) { in emitPrologue()
646 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4) in emitPrologue()
651 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4) in emitPrologue()
661 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL)) in emitPrologue()
664 .addReg(ARM::R4, RegState::Implicit) in emitPrologue()
668 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12) in emitPrologue()
672 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr)) in emitPrologue()
674 .addReg(ARM::R12, RegState::Kill) in emitPrologue()
675 .addReg(ARM::R4, RegState::Implicit) in emitPrologue()
680 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), ARM::SP) in emitPrologue()
681 .addReg(ARM::SP, RegState::Kill) in emitPrologue()
682 .addReg(ARM::R4, RegState::Kill) in emitPrologue()
722 dl, TII, FramePtr, ARM::SP, in emitPrologue()
752 case ARM::R8: in emitPrologue()
753 case ARM::R9: in emitPrologue()
754 case ARM::R10: in emitPrologue()
755 case ARM::R11: in emitPrologue()
756 case ARM::R12: in emitPrologue()
760 case ARM::R0: in emitPrologue()
761 case ARM::R1: in emitPrologue()
762 case ARM::R2: in emitPrologue()
763 case ARM::R3: in emitPrologue()
764 case ARM::R4: in emitPrologue()
765 case ARM::R5: in emitPrologue()
766 case ARM::R6: in emitPrologue()
767 case ARM::R7: in emitPrologue()
768 case ARM::LR: in emitPrologue()
785 case ARM::R8: in emitPrologue()
786 case ARM::R9: in emitPrologue()
787 case ARM::R10: in emitPrologue()
788 case ARM::R11: in emitPrologue()
789 case ARM::R12: in emitPrologue()
811 if ((Reg >= ARM::D0 && Reg <= ARM::D31) && in emitPrologue()
812 (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())) { in emitPrologue()
848 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::SP, MaxAlign, in emitPrologue()
858 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4) in emitPrologue()
859 .addReg(ARM::SP, RegState::Kill) in emitPrologue()
861 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::R4, MaxAlign, in emitPrologue()
863 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitPrologue()
864 .addReg(ARM::R4, RegState::Kill) in emitPrologue()
878 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), RegInfo->getBaseRegister()) in emitPrologue()
879 .addReg(ARM::SP) in emitPrologue()
883 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), RegInfo->getBaseRegister()) in emitPrologue()
884 .addReg(ARM::SP) in emitPrologue()
954 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, in emitEpilogue()
965 assert(!MFI.getPristineRegs(MF).test(ARM::R4) && in emitEpilogue()
967 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes, in emitEpilogue()
969 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitEpilogue()
970 .addReg(ARM::R4) in emitEpilogue()
977 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP) in emitEpilogue()
983 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitEpilogue()
998 while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::VLDMDIA_UPD) in emitEpilogue()
1043 FrameReg = ARM::SP; in ResolveFrameIndexReference()
1138 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs) in emitPushInst()
1167 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP) in emitPushInst()
1168 .addReg(ARM::SP) in emitPushInst()
1174 BuildMI(MBB, MI, DL, TII.get(StrOpc), ARM::SP) in emitPushInst()
1176 .addReg(ARM::SP) in emitPushInst()
1210 isTailCall = (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri); in emitPopInst()
1212 RetOpcode == ARM::SUBS_PC_LR || RetOpcode == ARM::t2SUBS_PC_LR; in emitPopInst()
1214 RetOpcode == ARM::TRAP || RetOpcode == ARM::TRAPNaCl || in emitPopInst()
1215 RetOpcode == ARM::tTRAP; in emitPopInst()
1216 isCmseEntry = (RetOpcode == ARM::tBXNS || RetOpcode == ARM::tBXNS_RET); in emitPopInst()
1230 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs) in emitPopInst()
1232 if (Reg == ARM::LR && !isTailCall && !isVarArg && !isInterrupt && in emitPopInst()
1235 Reg = ARM::PC; in emitPopInst()
1238 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET; in emitPopInst()
1262 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP) in emitPopInst()
1263 .addReg(ARM::SP) in emitPopInst()
1278 if (Regs[0] == ARM::PC) in emitPopInst()
1279 Regs[0] = ARM::LR; in emitPopInst()
1282 .addReg(ARM::SP, RegState::Define) in emitPopInst()
1283 .addReg(ARM::SP) in emitPopInst()
1287 if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) { in emitPopInst()
1321 unsigned DNum = CSI[i].getReg() - ARM::D8; in emitAlignedDPRCS2Spills()
1352 unsigned Opc = isThumb ? ARM::t2SUBri : ARM::SUBri; in emitAlignedDPRCS2Spills()
1353 BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4) in emitAlignedDPRCS2Spills()
1354 .addReg(ARM::SP) in emitAlignedDPRCS2Spills()
1365 emitAligningInstructions(MF, AFI, TII, MBB, MI, DL, ARM::R4, MaxAlign, true); in emitAlignedDPRCS2Spills()
1371 Opc = isThumb ? ARM::tMOVr : ARM::MOVr; in emitAlignedDPRCS2Spills()
1372 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP) in emitAlignedDPRCS2Spills()
1373 .addReg(ARM::R4) in emitAlignedDPRCS2Spills()
1380 unsigned NextReg = ARM::D8; in emitAlignedDPRCS2Spills()
1385 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1386 &ARM::QQPRRegClass); in emitAlignedDPRCS2Spills()
1388 BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed), ARM::R4) in emitAlignedDPRCS2Spills()
1389 .addReg(ARM::R4, RegState::Kill) in emitAlignedDPRCS2Spills()
1404 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1405 &ARM::QQPRRegClass); in emitAlignedDPRCS2Spills()
1407 BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q)) in emitAlignedDPRCS2Spills()
1408 .addReg(ARM::R4) in emitAlignedDPRCS2Spills()
1419 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1420 &ARM::QPRRegClass); in emitAlignedDPRCS2Spills()
1422 BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64)) in emitAlignedDPRCS2Spills()
1423 .addReg(ARM::R4) in emitAlignedDPRCS2Spills()
1435 BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD)) in emitAlignedDPRCS2Spills()
1437 .addReg(ARM::R4) in emitAlignedDPRCS2Spills()
1443 std::prev(MI)->addRegisterKilled(ARM::R4, TRI); in emitAlignedDPRCS2Spills()
1470 assert(MI->killsRegister(ARM::R4) && "Missed kill flag"); in skipAlignedDPRCS2Spills()
1492 if (CSI[i].getReg() == ARM::D8) { in emitAlignedDPRCS2Restores()
1505 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri; in emitAlignedDPRCS2Restores()
1506 BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4) in emitAlignedDPRCS2Restores()
1513 unsigned NextReg = ARM::D8; in emitAlignedDPRCS2Restores()
1517 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Restores()
1518 &ARM::QQPRRegClass); in emitAlignedDPRCS2Restores()
1519 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg) in emitAlignedDPRCS2Restores()
1520 .addReg(ARM::R4, RegState::Define) in emitAlignedDPRCS2Restores()
1521 .addReg(ARM::R4, RegState::Kill) in emitAlignedDPRCS2Restores()
1535 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Restores()
1536 &ARM::QQPRRegClass); in emitAlignedDPRCS2Restores()
1537 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg) in emitAlignedDPRCS2Restores()
1538 .addReg(ARM::R4) in emitAlignedDPRCS2Restores()
1548 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Restores()
1549 &ARM::QPRRegClass); in emitAlignedDPRCS2Restores()
1550 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg) in emitAlignedDPRCS2Restores()
1551 .addReg(ARM::R4) in emitAlignedDPRCS2Restores()
1560 BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg) in emitAlignedDPRCS2Restores()
1561 .addReg(ARM::R4) in emitAlignedDPRCS2Restores()
1566 std::prev(MI)->addRegisterKilled(ARM::R4, TRI); in emitAlignedDPRCS2Restores()
1578 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD; in spillCalleeSavedRegisters()
1580 ARM::t2STR_PRE : ARM::STR_PRE_IMM; in spillCalleeSavedRegisters()
1581 unsigned FltOpc = ARM::VSTMDDB_UPD; in spillCalleeSavedRegisters()
1585 return C.getReg() == ARM::FPCXTNS; in spillCalleeSavedRegisters()
1587 BuildMI(MBB, MI, DebugLoc(), STI.getInstrInfo()->get(ARM::VSTR_FPCXTNS_pre), in spillCalleeSavedRegisters()
1588 ARM::SP) in spillCalleeSavedRegisters()
1589 .addReg(ARM::SP) in spillCalleeSavedRegisters()
1625 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD; in restoreCalleeSavedRegisters()
1626 unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST :ARM::LDR_POST_IMM; in restoreCalleeSavedRegisters()
1627 unsigned FltOpc = ARM::VLDMDIA_UPD; in restoreCalleeSavedRegisters()
1675 if (MI.getOpcode() == ARM::ADDri) { in estimateRSStackSizeLimit()
1681 if (MI.getOpcode() == ARM::t2ADDri || MI.getOpcode() == ARM::t2ADDri12) in estimateRSStackSizeLimit()
1686 if (RegClass && !RegClass->contains(ARM::SP)) in estimateRSStackSizeLimit()
1771 if (!SavedRegs.test(ARM::D8 + NumSpills)) in checkNumAlignedDPRCS2Regs()
1782 SavedRegs.set(ARM::R4); in checkNumAlignedDPRCS2Regs()
1828 SavedRegs.set(ARM::R4); in determineCalleeSaves()
1837 SavedRegs.set(ARM::R4); in determineCalleeSaves()
1838 SavedRegs.set(ARM::LR); in determineCalleeSaves()
1844 SavedRegs.set(ARM::LR); in determineCalleeSaves()
1854 SavedRegs.set(ARM::R4); in determineCalleeSaves()
1879 if (!ARM::GPRRegClass.contains(Reg)) { in determineCalleeSaves()
1881 if (ARM::SPRRegClass.contains(Reg)) in determineCalleeSaves()
1883 else if (ARM::DPRRegClass.contains(Reg)) in determineCalleeSaves()
1885 else if (ARM::QPRRegClass.contains(Reg)) in determineCalleeSaves()
1895 if (Reg == ARM::LR) in determineCalleeSaves()
1903 case ARM::LR: in determineCalleeSaves()
1906 case ARM::R0: case ARM::R1: in determineCalleeSaves()
1907 case ARM::R2: case ARM::R3: in determineCalleeSaves()
1908 case ARM::R4: case ARM::R5: in determineCalleeSaves()
1909 case ARM::R6: case ARM::R7: in determineCalleeSaves()
1922 case ARM::R0: case ARM::R1: in determineCalleeSaves()
1923 case ARM::R2: case ARM::R3: in determineCalleeSaves()
1924 case ARM::R4: case ARM::R5: in determineCalleeSaves()
1925 case ARM::R6: case ARM::R7: in determineCalleeSaves()
1926 case ARM::LR: in determineCalleeSaves()
2045 SavedRegs.set(ARM::LR); in determineCalleeSaves()
2048 auto LRPos = llvm::find(UnspilledCS1GPRs, ARM::LR); in determineCalleeSaves()
2056 if (FramePtr == ARM::R7) in determineCalleeSaves()
2089 for (unsigned Reg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) { in determineCalleeSaves()
2110 for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6}) { in determineCalleeSaves()
2127 if (SavedRegs.test(ARM::R7)) { in determineCalleeSaves()
2132 AvailableRegs.push_back(ARM::R7); in determineCalleeSaves()
2140 for (unsigned Reg : {ARM::R8, ARM::R9, ARM::R10, ARM::R11}) { in determineCalleeSaves()
2153 !(MF.getRegInfo().isLiveIn(ARM::LR) && in determineCalleeSaves()
2155 if (SavedRegs.test(ARM::LR)) { in determineCalleeSaves()
2160 AvailableRegs.push_back(ARM::LR); in determineCalleeSaves()
2179 if (Reg != ARM::LR && !MRI.isPhysRegUsed(Reg)) in determineCalleeSaves()
2182 if (Reg == ARM::LR) in determineCalleeSaves()
2196 SavedRegs.set(ARM::LR); in determineCalleeSaves()
2199 LRPos = llvm::find(UnspilledCS1GPRs, (unsigned)ARM::LR); in determineCalleeSaves()
2204 if (!MRI.isReserved(ARM::LR) && !MRI.isPhysRegUsed(ARM::LR) && in determineCalleeSaves()
2221 (STI.isTargetWindows() && Reg == ARM::R11) || in determineCalleeSaves()
2223 (Reg == ARM::LR && !ExpensiveLRRestore)) { in determineCalleeSaves()
2228 !(Reg == ARM::LR && AFI->isThumb1OnlyFunction())) in determineCalleeSaves()
2281 const TargetRegisterClass &RC = ARM::GPRRegClass; in determineCalleeSaves()
2291 SavedRegs.set(ARM::LR); in determineCalleeSaves()
2292 AFI->setLRIsSpilled(SavedRegs.test(ARM::LR)); in determineCalleeSaves()
2304 SavedRegs.set(ARM::R0); in getCalleeSaves()
2314 CSI.emplace_back(ARM::FPCXTNS); in assignCalleeSavedSpillSlots()
2323 static const SpillSlot FixedSpillOffsets[] = {{ARM::FPCXTNS, -4}}; in getCalleeSavedSpillSlots()
2364 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { in eliminateCallFramePseudoInstr()
2368 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); in eliminateCallFramePseudoInstr()
2478 unsigned ScratchReg0 = ARM::R4; in adjustForSegmentedStacks()
2479 unsigned ScratchReg1 = ARM::R5; in adjustForSegmentedStacks()
2546 BuildMI(PrevStackMBB, DL, TII.get(ARM::tPUSH)) in adjustForSegmentedStacks()
2551 BuildMI(PrevStackMBB, DL, TII.get(ARM::STMDB_UPD)) in adjustForSegmentedStacks()
2552 .addReg(ARM::SP, RegState::Define) in adjustForSegmentedStacks()
2553 .addReg(ARM::SP) in adjustForSegmentedStacks()
2575 BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), ScratchReg1) in adjustForSegmentedStacks()
2576 .addReg(ARM::SP) in adjustForSegmentedStacks()
2579 BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ScratchReg1) in adjustForSegmentedStacks()
2580 .addReg(ARM::SP) in adjustForSegmentedStacks()
2587 BuildMI(McrMBB, DL, TII.get(ARM::tSUBi8), ScratchReg1) in adjustForSegmentedStacks()
2593 BuildMI(McrMBB, DL, TII.get(ARM::SUBri), ScratchReg1) in adjustForSegmentedStacks()
2594 .addReg(ARM::SP) in adjustForSegmentedStacks()
2608 BuildMI(GetMBB, DL, TII.get(ARM::tLDRpci), ScratchReg0) in adjustForSegmentedStacks()
2613 BuildMI(GetMBB, DL, TII.get(ARM::tLDRi), ScratchReg0) in adjustForSegmentedStacks()
2620 BuildMI(McrMBB, DL, TII.get(Thumb ? ARM::t2MRC : ARM::MRC), in adjustForSegmentedStacks()
2635 BuildMI(GetMBB, DL, TII.get(Thumb ? ARM::t2LDRi12 : ARM::LDRi12), in adjustForSegmentedStacks()
2644 Opcode = Thumb ? ARM::tCMPr : ARM::CMPrr; in adjustForSegmentedStacks()
2651 Opcode = Thumb ? ARM::tBcc : ARM::Bcc; in adjustForSegmentedStacks()
2654 .addReg(ARM::CPSR); in adjustForSegmentedStacks()
2664 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg0) in adjustForSegmentedStacks()
2669 BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg0) in adjustForSegmentedStacks()
2677 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg1) in adjustForSegmentedStacks()
2682 BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg1) in adjustForSegmentedStacks()
2690 BuildMI(AllocMBB, DL, TII.get(ARM::tPUSH)) in adjustForSegmentedStacks()
2692 .addReg(ARM::LR); in adjustForSegmentedStacks()
2694 BuildMI(AllocMBB, DL, TII.get(ARM::STMDB_UPD)) in adjustForSegmentedStacks()
2695 .addReg(ARM::SP, RegState::Define) in adjustForSegmentedStacks()
2696 .addReg(ARM::SP) in adjustForSegmentedStacks()
2698 .addReg(ARM::LR); in adjustForSegmentedStacks()
2707 nullptr, MRI->getDwarfRegNum(ARM::LR, true), -12)); in adjustForSegmentedStacks()
2713 BuildMI(AllocMBB, DL, TII.get(ARM::tBL)) in adjustForSegmentedStacks()
2717 BuildMI(AllocMBB, DL, TII.get(ARM::BL)) in adjustForSegmentedStacks()
2724 BuildMI(AllocMBB, DL, TII.get(ARM::tPOP)) in adjustForSegmentedStacks()
2727 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVr), ARM::LR) in adjustForSegmentedStacks()
2731 BuildMI(AllocMBB, DL, TII.get(ARM::t2LDR_POST)) in adjustForSegmentedStacks()
2732 .addReg(ARM::LR, RegState::Define) in adjustForSegmentedStacks()
2733 .addReg(ARM::SP, RegState::Define) in adjustForSegmentedStacks()
2734 .addReg(ARM::SP) in adjustForSegmentedStacks()
2739 BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD)) in adjustForSegmentedStacks()
2740 .addReg(ARM::SP, RegState::Define) in adjustForSegmentedStacks()
2741 .addReg(ARM::SP) in adjustForSegmentedStacks()
2743 .addReg(ARM::LR); in adjustForSegmentedStacks()
2751 BuildMI(AllocMBB, DL, TII.get(ARM::tPOP)) in adjustForSegmentedStacks()
2756 BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD)) in adjustForSegmentedStacks()
2757 .addReg(ARM::SP, RegState::Define) in adjustForSegmentedStacks()
2758 .addReg(ARM::SP) in adjustForSegmentedStacks()
2775 BuildMI(PostStackMBB, DL, TII.get(ARM::tPOP)) in adjustForSegmentedStacks()
2780 BuildMI(PostStackMBB, DL, TII.get(ARM::LDMIA_UPD)) in adjustForSegmentedStacks()
2781 .addReg(ARM::SP, RegState::Define) in adjustForSegmentedStacks()
2782 .addReg(ARM::SP) in adjustForSegmentedStacks()