Lines Matching refs:ARM
79 if (ScratchReg == ARM::NoRegister) in emitPrologueEpilogueSPUpdate()
84 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ScratchReg) in emitPrologueEpilogueSPUpdate()
90 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDhirr), ARM::SP) in emitPrologueEpilogueSPUpdate()
91 .addReg(ARM::SP) in emitPrologueEpilogueSPUpdate()
99 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, in emitPrologueEpilogueSPUpdate()
109 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, in emitCallSPUpdate()
136 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { in eliminateCallFramePseudoInstr()
139 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); in eliminateCallFramePseudoInstr()
184 ARM::NoRegister, MachineInstr::FrameSetup); in emitPrologue()
197 ARM::NoRegister, MachineInstr::FrameSetup); in emitPrologue()
212 case ARM::R8: in emitPrologue()
213 case ARM::R9: in emitPrologue()
214 case ARM::R10: in emitPrologue()
215 case ARM::R11: in emitPrologue()
221 case ARM::R4: in emitPrologue()
222 case ARM::R5: in emitPrologue()
223 case ARM::R6: in emitPrologue()
224 case ARM::R7: in emitPrologue()
225 case ARM::LR: in emitPrologue()
235 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) { in emitPrologue()
274 case ARM::R8: in emitPrologue()
275 case ARM::R9: in emitPrologue()
276 case ARM::R10: in emitPrologue()
277 case ARM::R11: in emitPrologue()
278 case ARM::R12: in emitPrologue()
282 case ARM::R0: in emitPrologue()
283 case ARM::R1: in emitPrologue()
284 case ARM::R2: in emitPrologue()
285 case ARM::R3: in emitPrologue()
286 case ARM::R4: in emitPrologue()
287 case ARM::R5: in emitPrologue()
288 case ARM::R6: in emitPrologue()
289 case ARM::R7: in emitPrologue()
290 case ARM::LR: in emitPrologue()
304 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr) in emitPrologue()
305 .addReg(ARM::SP) in emitPrologue()
337 while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tMOVr) in emitPrologue()
339 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) { in emitPrologue()
355 case ARM::R8: in emitPrologue()
356 case ARM::R9: in emitPrologue()
357 case ARM::R10: in emitPrologue()
358 case ARM::R11: in emitPrologue()
359 case ARM::R12: { in emitPrologue()
378 unsigned ScratchRegister = ARM::NoRegister; in emitPrologue()
414 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4) in emitPrologue()
415 .addReg(ARM::SP, RegState::Kill) in emitPrologue()
418 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSRri), ARM::R4) in emitPrologue()
419 .addDef(ARM::CPSR) in emitPrologue()
420 .addReg(ARM::R4, RegState::Kill) in emitPrologue()
424 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSLri), ARM::R4) in emitPrologue()
425 .addDef(ARM::CPSR) in emitPrologue()
426 .addReg(ARM::R4, RegState::Kill) in emitPrologue()
430 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitPrologue()
431 .addReg(ARM::R4, RegState::Kill) in emitPrologue()
442 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr) in emitPrologue()
443 .addReg(ARM::SP) in emitPrologue()
458 if (MI.getOpcode() == ARM::tLDRspi && MI.getOperand(1).isFI() && in isCSRestore()
461 else if (MI.getOpcode() == ARM::tPOP) { in isCSRestore()
463 } else if (MI.getOpcode() == ARM::tMOVr) { in isCSRestore()
466 return ((ARM::tGPRRegClass.contains(Src) || Src == ARM::LR) && in isCSRestore()
467 ARM::hGPRRegClass.contains(Dst)); in isCSRestore()
493 NumBytes - ArgRegsSaveSize, ARM::NoRegister, in emitEpilogue()
517 assert(!MFI.getPristineRegs(MF).test(ARM::R4) && in emitEpilogue()
519 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes, in emitEpilogue()
521 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitEpilogue()
522 .addReg(ARM::R4) in emitEpilogue()
525 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitEpilogue()
532 unsigned ScratchRegister = ARM::NoRegister; in emitEpilogue()
541 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tBX_RET && in emitEpilogue()
542 &MBB.front() != &*MBBI && std::prev(MBBI)->getOpcode() == ARM::tPOP) { in emitEpilogue()
576 if (CSI.getReg() == ARM::LR) in needPopSpecialFixUp()
621 if (MBBI != MBB.end() && MBBI->getOpcode() != ARM::tB) in emitPopSpecialFixUp()
622 CanRestoreDirectly = (MBBI->getOpcode() == ARM::tBX_RET || in emitPopSpecialFixUp()
623 MBBI->getOpcode() == ARM::tPOP_RET); in emitPopSpecialFixUp()
627 assert(MBBI_prev->getOpcode() == ARM::tPOP); in emitPopSpecialFixUp()
629 if ((*MBB.succ_begin())->begin()->getOpcode() == ARM::tBX_RET) in emitPopSpecialFixUp()
637 if (!DoIt || MBBI->getOpcode() == ARM::tPOP_RET) in emitPopSpecialFixUp()
640 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP_RET)) in emitPopSpecialFixUp()
646 MIB.addReg(ARM::PC, RegState::Define); in emitPopSpecialFixUp()
680 TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::tGPRRegClassID)); in emitPopSpecialFixUp()
684 if (STI.getFramePointerReg() == ARM::R7) in emitPopSpecialFixUp()
685 PopFriendly.set(ARM::R7); in emitPopSpecialFixUp()
691 TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::hGPRRegClassID)); in emitPopSpecialFixUp()
693 GPRsNoLRSP.reset(ARM::LR); in emitPopSpecialFixUp()
694 GPRsNoLRSP.reset(ARM::SP); in emitPopSpecialFixUp()
695 GPRsNoLRSP.reset(ARM::PC); in emitPopSpecialFixUp()
705 if (PrevMBBI->getOpcode() == ARM::tPOP) { in emitPopSpecialFixUp()
723 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRspi)) in emitPopSpecialFixUp()
725 .addReg(ARM::SP) in emitPopSpecialFixUp()
729 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr)) in emitPopSpecialFixUp()
730 .addReg(ARM::LR, RegState::Define) in emitPopSpecialFixUp()
737 ArgRegsSaveSize + 4, ARM::NoRegister, in emitPopSpecialFixUp()
745 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr)) in emitPopSpecialFixUp()
751 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPOP_RET) { in emitPopSpecialFixUp()
755 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP)) in emitPopSpecialFixUp()
760 MO.getReg() != ARM::PC) { in emitPopSpecialFixUp()
770 MBBI = BuildMI(MBB, MBB.end(), dl, TII.get(ARM::tBX_RET)) in emitPopSpecialFixUp()
775 BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)) in emitPopSpecialFixUp()
780 ARM::NoRegister, MachineInstr::NoFlags); in emitPopSpecialFixUp()
782 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr)) in emitPopSpecialFixUp()
783 .addReg(ARM::LR, RegState::Define) in emitPopSpecialFixUp()
788 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr)) in emitPopSpecialFixUp()
796 using ARMRegSet = std::bitset<ARM::NUM_TARGET_REGS>;
829 if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) { in spillCalleeSavedRegisters()
831 } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) { in spillCalleeSavedRegisters()
837 if ((ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) && in spillCalleeSavedRegisters()
844 for (unsigned ArgReg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) in spillCalleeSavedRegisters()
852 BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL)); in spillCalleeSavedRegisters()
853 for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::LR}) { in spillCalleeSavedRegisters()
874 static const unsigned AllCopyRegs[] = {ARM::LR, ARM::R7, ARM::R6, in spillCalleeSavedRegisters()
875 ARM::R5, ARM::R4, ARM::R3, in spillCalleeSavedRegisters()
876 ARM::R2, ARM::R1, ARM::R0}; in spillCalleeSavedRegisters()
877 static const unsigned AllHighRegs[] = {ARM::R11, ARM::R10, ARM::R9, ARM::R8}; in spillCalleeSavedRegisters()
892 MachineInstrBuilder PushMIB = BuildMI(MF, DL, TII.get(ARM::tPUSH)) in spillCalleeSavedRegisters()
904 BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr)) in spillCalleeSavedRegisters()
953 if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) { in restoreCalleeSavedRegisters()
955 } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) { in restoreCalleeSavedRegisters()
963 if ((ARM::tGPRRegClass.contains(Reg)) && in restoreCalleeSavedRegisters()
971 if (Terminator != MBB.end() && Terminator->getOpcode() == ARM::tBX_RET) { in restoreCalleeSavedRegisters()
972 CopyRegs[ARM::R0] = true; in restoreCalleeSavedRegisters()
973 CopyRegs[ARM::R1] = true; in restoreCalleeSavedRegisters()
974 CopyRegs[ARM::R2] = true; in restoreCalleeSavedRegisters()
975 CopyRegs[ARM::R3] = true; in restoreCalleeSavedRegisters()
982 static const unsigned AllCopyRegs[] = {ARM::R0, ARM::R1, ARM::R2, ARM::R3, in restoreCalleeSavedRegisters()
983 ARM::R4, ARM::R5, ARM::R6, ARM::R7}; in restoreCalleeSavedRegisters()
984 static const unsigned AllHighRegs[] = {ARM::R8, ARM::R9, ARM::R10, ARM::R11}; in restoreCalleeSavedRegisters()
1001 BuildMI(MBB, MI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL)); in restoreCalleeSavedRegisters()
1008 BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr)) in restoreCalleeSavedRegisters()
1020 BuildMI(MF, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL)); in restoreCalleeSavedRegisters()
1028 if (!(ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR)) in restoreCalleeSavedRegisters()
1031 if (Reg == ARM::LR) { in restoreCalleeSavedRegisters()
1034 MI->getOpcode() == ARM::TCRETURNdi || in restoreCalleeSavedRegisters()
1035 MI->getOpcode() == ARM::TCRETURNri) in restoreCalleeSavedRegisters()
1055 Reg = ARM::PC; in restoreCalleeSavedRegisters()
1056 (*MIB).setDesc(TII.get(ARM::tPOP_RET)); in restoreCalleeSavedRegisters()