28   return MCInstBuilder(ARM::tMOVr)  in getNop()
29       .addReg(ARM::R8)  in getNop()
30       .addReg(ARM::R8)  in getNop()
47   assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&  in copyPhysReg()
50   if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg)  in copyPhysReg()
51       || !ARM::tGPRRegClass.contains(DestReg))  in copyPhysReg()
52     BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)  in copyPhysReg()
60     if (MBB.computeRegisterLiveness(RegInfo, ARM::CPSR, I)  in copyPhysReg()
62       BuildMI(MBB, I, DL, get(ARM::tMOVSr), DestReg)  in copyPhysReg()
64           ->addRegisterDead(ARM::CPSR, RegInfo);  in copyPhysReg()
69     BuildMI(MBB, I, DL, get(ARM::tPUSH))  in copyPhysReg()
72     BuildMI(MBB, I, DL, get(ARM::tPOP))  in copyPhysReg()
83   assert((RC == &ARM::tGPRRegClass ||  in storeRegToStackSlot()
87   if (RC == &ARM::tGPRRegClass ||  in storeRegToStackSlot()
97     BuildMI(MBB, I, DL, get(ARM::tSTRspi))  in storeRegToStackSlot()
112       (RC->hasSuperClassEq(&ARM::tGPRRegClass) ||  in loadRegFromStackSlot()
116   if (RC->hasSuperClassEq(&ARM::tGPRRegClass) ||  in loadRegFromStackSlot()
126     BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)  in loadRegFromStackSlot()
139     expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_pcrel, ARM::tLDRi);  in expandLoadStackGuard()
141     expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_abs, ARM::tLDRi);  in expandLoadStackGuard()
151   if (Opcode == ARM::tADCS || Opcode == ARM::tSBCS)  in canCopyGluedNodeDuringSchedule()