Lines Matching refs:ARM
184 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX) in runOnMachineFunction()
219 if(ARM::GPRPairRegClass.contains(Reg)) { in printOperand()
222 Reg = TRI->getSubReg(Reg, ARM::gsub_0); in printOperand()
293 if (!ARM::DPRRegClass.contains(*SR)) in PrintAsmOperand()
295 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg; in PrintAsmOperand()
320 if (ARM::GPRPairRegClass.contains(RegBegin)) { in PrintAsmOperand()
322 Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); in PrintAsmOperand()
324 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1); in PrintAsmOperand()
384 ARM::GPRPairRegClass.hasSubClassEq(TRI->getRegClass(RC))) { in PrintAsmOperand()
392 TRI->getSubReg(MO.getReg(), FirstHalf ? ARM::gsub_0 : ARM::gsub_1); in PrintAsmOperand()
414 if (!ARM::QPRRegClass.contains(Reg)) in PrintAsmOperand()
418 TRI->getSubReg(Reg, ExtraCode[0] == 'e' ? ARM::dsub_0 : ARM::dsub_1); in PrintAsmOperand()
433 if(!ARM::GPRPairRegClass.contains(Reg)) in PrintAsmOperand()
435 Reg = TRI->getSubReg(Reg, ARM::gsub_1); in PrintAsmOperand()
471 return STI.getFeatureBits()[ARM::ModeThumb]; in isThumb()
1022 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2B) in emitJumpTableInsts()
1098 case ARM::tPUSH: in EmitUnwindingInstruction()
1100 SrcReg = DstReg = ARM::SP; in EmitUnwindingInstruction()
1102 case ARM::tLDRpci: in EmitUnwindingInstruction()
1103 case ARM::t2MOVi16: in EmitUnwindingInstruction()
1104 case ARM::t2MOVTi16: in EmitUnwindingInstruction()
1122 assert(DstReg == ARM::SP && in EmitUnwindingInstruction()
1137 case ARM::tPUSH: in EmitUnwindingInstruction()
1141 case ARM::STMDB_UPD: in EmitUnwindingInstruction()
1142 case ARM::t2STMDB_UPD: in EmitUnwindingInstruction()
1143 case ARM::VSTMDDB_UPD: in EmitUnwindingInstruction()
1144 assert(SrcReg == ARM::SP && in EmitUnwindingInstruction()
1173 case ARM::STR_PRE_IMM: in EmitUnwindingInstruction()
1174 case ARM::STR_PRE_REG: in EmitUnwindingInstruction()
1175 case ARM::t2STR_PRE: in EmitUnwindingInstruction()
1176 assert(MI->getOperand(2).getReg() == ARM::SP && in EmitUnwindingInstruction()
1181 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) { in EmitUnwindingInstruction()
1182 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD); in EmitUnwindingInstruction()
1189 if (SrcReg == ARM::SP) { in EmitUnwindingInstruction()
1195 case ARM::MOVr: in EmitUnwindingInstruction()
1196 case ARM::tMOVr: in EmitUnwindingInstruction()
1199 case ARM::ADDri: in EmitUnwindingInstruction()
1200 case ARM::t2ADDri: in EmitUnwindingInstruction()
1201 case ARM::t2ADDri12: in EmitUnwindingInstruction()
1202 case ARM::t2ADDspImm: in EmitUnwindingInstruction()
1203 case ARM::t2ADDspImm12: in EmitUnwindingInstruction()
1206 case ARM::SUBri: in EmitUnwindingInstruction()
1207 case ARM::t2SUBri: in EmitUnwindingInstruction()
1208 case ARM::t2SUBri12: in EmitUnwindingInstruction()
1209 case ARM::t2SUBspImm: in EmitUnwindingInstruction()
1210 case ARM::t2SUBspImm12: in EmitUnwindingInstruction()
1213 case ARM::tSUBspi: in EmitUnwindingInstruction()
1216 case ARM::tADDspi: in EmitUnwindingInstruction()
1217 case ARM::tADDrSPi: in EmitUnwindingInstruction()
1220 case ARM::tADDhirr: in EmitUnwindingInstruction()
1226 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) { in EmitUnwindingInstruction()
1227 if (DstReg == FramePtr && FramePtr != ARM::SP) in EmitUnwindingInstruction()
1230 ATS.emitSetFP(FramePtr, ARM::SP, -Offset); in EmitUnwindingInstruction()
1231 else if (DstReg == ARM::SP) { in EmitUnwindingInstruction()
1241 } else if (DstReg == ARM::SP) { in EmitUnwindingInstruction()
1247 case ARM::tMOVr: in EmitUnwindingInstruction()
1253 case ARM::tLDRpci: { in EmitUnwindingInstruction()
1269 case ARM::t2MOVi16: in EmitUnwindingInstruction()
1273 case ARM::t2MOVTi16: in EmitUnwindingInstruction()
1298 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) { in emitInstruction()
1318 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass"); in emitInstruction()
1319 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing"); in emitInstruction()
1320 case ARM::LEApcrel: in emitInstruction()
1321 case ARM::tLEApcrel: in emitInstruction()
1322 case ARM::t2LEApcrel: { in emitInstruction()
1326 ARM::t2LEApcrel ? ARM::t2ADR in emitInstruction()
1327 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR in emitInstruction()
1328 : ARM::ADR)) in emitInstruction()
1336 case ARM::LEApcrelJT: in emitInstruction()
1337 case ARM::tLEApcrelJT: in emitInstruction()
1338 case ARM::t2LEApcrelJT: { in emitInstruction()
1342 ARM::t2LEApcrelJT ? ARM::t2ADR in emitInstruction()
1343 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR in emitInstruction()
1344 : ARM::ADR)) in emitInstruction()
1354 case ARM::BX_CALL: { in emitInstruction()
1355 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr) in emitInstruction()
1356 .addReg(ARM::LR) in emitInstruction()
1357 .addReg(ARM::PC) in emitInstruction()
1365 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX) in emitInstruction()
1369 case ARM::tBX_CALL: { in emitInstruction()
1394 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBL) in emitInstruction()
1400 case ARM::BMOVPCRX_CALL: { in emitInstruction()
1401 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr) in emitInstruction()
1402 .addReg(ARM::LR) in emitInstruction()
1403 .addReg(ARM::PC) in emitInstruction()
1410 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr) in emitInstruction()
1411 .addReg(ARM::PC) in emitInstruction()
1420 case ARM::BMOVPCB_CALL: { in emitInstruction()
1421 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr) in emitInstruction()
1422 .addReg(ARM::LR) in emitInstruction()
1423 .addReg(ARM::PC) in emitInstruction()
1435 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::Bcc) in emitInstruction()
1442 case ARM::MOVi16_ga_pcrel: in emitInstruction()
1443 case ARM::t2MOVi16_ga_pcrel: { in emitInstruction()
1445 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16); in emitInstruction()
1457 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4; in emitInstruction()
1473 case ARM::MOVTi16_ga_pcrel: in emitInstruction()
1474 case ARM::t2MOVTi16_ga_pcrel: { in emitInstruction()
1476 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel in emitInstruction()
1477 ? ARM::MOVTi16 : ARM::t2MOVTi16); in emitInstruction()
1490 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4; in emitInstruction()
1505 case ARM::t2BFi: in emitInstruction()
1506 case ARM::t2BFic: in emitInstruction()
1507 case ARM::t2BFLi: in emitInstruction()
1508 case ARM::t2BFr: in emitInstruction()
1509 case ARM::t2BFLr: { in emitInstruction()
1541 if (Opc == ARM::t2BFic) { in emitInstruction()
1556 case ARM::t2BF_LabelPseudo: { in emitInstruction()
1565 case ARM::tPICADD: { in emitInstruction()
1577 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr) in emitInstruction()
1580 .addReg(ARM::PC) in emitInstruction()
1586 case ARM::PICADD: { in emitInstruction()
1598 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr) in emitInstruction()
1600 .addReg(ARM::PC) in emitInstruction()
1609 case ARM::PICSTR: in emitInstruction()
1610 case ARM::PICSTRB: in emitInstruction()
1611 case ARM::PICSTRH: in emitInstruction()
1612 case ARM::PICLDR: in emitInstruction()
1613 case ARM::PICLDRB: in emitInstruction()
1614 case ARM::PICLDRH: in emitInstruction()
1615 case ARM::PICLDRSB: in emitInstruction()
1616 case ARM::PICLDRSH: { in emitInstruction()
1633 case ARM::PICSTR: Opcode = ARM::STRrs; break; in emitInstruction()
1634 case ARM::PICSTRB: Opcode = ARM::STRBrs; break; in emitInstruction()
1635 case ARM::PICSTRH: Opcode = ARM::STRH; break; in emitInstruction()
1636 case ARM::PICLDR: Opcode = ARM::LDRrs; break; in emitInstruction()
1637 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break; in emitInstruction()
1638 case ARM::PICLDRH: Opcode = ARM::LDRH; break; in emitInstruction()
1639 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break; in emitInstruction()
1640 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break; in emitInstruction()
1644 .addReg(ARM::PC) in emitInstruction()
1653 case ARM::CONSTPOOL_ENTRY: { in emitInstruction()
1680 case ARM::JUMPTABLE_ADDRS: in emitInstruction()
1683 case ARM::JUMPTABLE_INSTS: in emitInstruction()
1686 case ARM::JUMPTABLE_TBB: in emitInstruction()
1687 case ARM::JUMPTABLE_TBH: in emitInstruction()
1688 emitJumpTableTBInst(MI, MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2); in emitInstruction()
1690 case ARM::t2BR_JT: { in emitInstruction()
1691 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr) in emitInstruction()
1692 .addReg(ARM::PC) in emitInstruction()
1699 case ARM::t2TBB_JT: in emitInstruction()
1700 case ARM::t2TBH_JT: { in emitInstruction()
1701 unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH; in emitInstruction()
1712 case ARM::tTBB_JT: in emitInstruction()
1713 case ARM::tTBH_JT: { in emitInstruction()
1715 bool Is8Bit = MI->getOpcode() == ARM::tTBB_JT; in emitInstruction()
1722 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLSLri) in emitInstruction()
1724 .addReg(ARM::CPSR) in emitInstruction()
1731 if (Base == ARM::PC) { in emitInstruction()
1746 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr) in emitInstruction()
1754 unsigned Opc = Is8Bit ? ARM::tLDRBi : ARM::tLDRHi; in emitInstruction()
1768 unsigned Opc = Is8Bit ? ARM::tLDRBr : ARM::tLDRHr; in emitInstruction()
1778 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLSLri) in emitInstruction()
1780 .addReg(ARM::CPSR) in emitInstruction()
1788 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr) in emitInstruction()
1789 .addReg(ARM::PC) in emitInstruction()
1790 .addReg(ARM::PC) in emitInstruction()
1797 case ARM::tBR_JTr: in emitInstruction()
1798 case ARM::BR_JTr: { in emitInstruction()
1801 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ? in emitInstruction()
1802 ARM::MOVr : ARM::tMOVr; in emitInstruction()
1804 TmpInst.addOperand(MCOperand::createReg(ARM::PC)); in emitInstruction()
1810 if (Opc == ARM::MOVr) in emitInstruction()
1815 case ARM::BR_JTm_i12: { in emitInstruction()
1818 TmpInst.setOpcode(ARM::LDRi12); in emitInstruction()
1819 TmpInst.addOperand(MCOperand::createReg(ARM::PC)); in emitInstruction()
1828 case ARM::BR_JTm_rs: { in emitInstruction()
1831 TmpInst.setOpcode(ARM::LDRrs); in emitInstruction()
1832 TmpInst.addOperand(MCOperand::createReg(ARM::PC)); in emitInstruction()
1842 case ARM::BR_JTadd: { in emitInstruction()
1844 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr) in emitInstruction()
1845 .addReg(ARM::PC) in emitInstruction()
1855 case ARM::SPACE: in emitInstruction()
1858 case ARM::TRAP: { in emitInstruction()
1869 case ARM::TRAPNaCl: { in emitInstruction()
1875 case ARM::tTRAP: { in emitInstruction()
1886 case ARM::t2Int_eh_sjlj_setjmp: in emitInstruction()
1887 case ARM::t2Int_eh_sjlj_setjmp_nofp: in emitInstruction()
1888 case ARM::tInt_eh_sjlj_setjmp: { in emitInstruction()
1901 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr) in emitInstruction()
1903 .addReg(ARM::PC) in emitInstruction()
1908 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDi3) in emitInstruction()
1911 .addReg(ARM::CPSR) in emitInstruction()
1918 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tSTRi) in emitInstruction()
1928 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8) in emitInstruction()
1929 .addReg(ARM::R0) in emitInstruction()
1930 .addReg(ARM::CPSR) in emitInstruction()
1937 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tB) in emitInstruction()
1943 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8) in emitInstruction()
1944 .addReg(ARM::R0) in emitInstruction()
1945 .addReg(ARM::CPSR) in emitInstruction()
1955 case ARM::Int_eh_sjlj_setjmp_nofp: in emitInstruction()
1956 case ARM::Int_eh_sjlj_setjmp: { in emitInstruction()
1967 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri) in emitInstruction()
1969 .addReg(ARM::PC) in emitInstruction()
1977 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::STRi12) in emitInstruction()
1985 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi) in emitInstruction()
1986 .addReg(ARM::R0) in emitInstruction()
1994 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri) in emitInstruction()
1995 .addReg(ARM::PC) in emitInstruction()
1996 .addReg(ARM::PC) in emitInstruction()
2005 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi) in emitInstruction()
2006 .addReg(ARM::R0) in emitInstruction()
2015 case ARM::Int_eh_sjlj_longjmp: { in emitInstruction()
2022 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12) in emitInstruction()
2023 .addReg(ARM::SP) in emitInstruction()
2030 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12) in emitInstruction()
2040 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12) in emitInstruction()
2050 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12) in emitInstruction()
2051 .addReg(ARM::R7) in emitInstruction()
2057 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12) in emitInstruction()
2058 .addReg(ARM::R11) in emitInstruction()
2067 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX) in emitInstruction()
2074 case ARM::tInt_eh_sjlj_longjmp: { in emitInstruction()
2083 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi) in emitInstruction()
2093 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr) in emitInstruction()
2094 .addReg(ARM::SP) in emitInstruction()
2100 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi) in emitInstruction()
2110 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi) in emitInstruction()
2120 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi) in emitInstruction()
2121 .addReg(ARM::R7) in emitInstruction()
2127 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi) in emitInstruction()
2128 .addReg(ARM::R11) in emitInstruction()
2136 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX) in emitInstruction()
2143 case ARM::tInt_WIN_eh_sjlj_longjmp: { in emitInstruction()
2150 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12) in emitInstruction()
2151 .addReg(ARM::R11) in emitInstruction()
2157 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12) in emitInstruction()
2158 .addReg(ARM::SP) in emitInstruction()
2164 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12) in emitInstruction()
2165 .addReg(ARM::PC) in emitInstruction()
2173 case ARM::PATCHABLE_FUNCTION_ENTER: in emitInstruction()
2176 case ARM::PATCHABLE_FUNCTION_EXIT: in emitInstruction()
2179 case ARM::PATCHABLE_TAIL_CALL: in emitInstruction()
2182 case ARM::SpeculationBarrierISBDSBEndBB: { in emitInstruction()
2185 TmpInstDSB.setOpcode(ARM::DSB); in emitInstruction()
2189 TmpInstISB.setOpcode(ARM::ISB); in emitInstruction()
2194 case ARM::t2SpeculationBarrierISBDSBEndBB: { in emitInstruction()
2197 TmpInstDSB.setOpcode(ARM::t2DSB); in emitInstruction()
2203 TmpInstISB.setOpcode(ARM::t2ISB); in emitInstruction()
2210 case ARM::SpeculationBarrierSBEndBB: { in emitInstruction()
2213 TmpInstSB.setOpcode(ARM::SB); in emitInstruction()
2217 case ARM::t2SpeculationBarrierSBEndBB: { in emitInstruction()
2220 TmpInstSB.setOpcode(ARM::t2SB); in emitInstruction()