Lines Matching refs:ARM
93 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
94 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
95 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
96 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
97 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
98 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
99 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
100 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
103 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
104 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
105 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
106 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
107 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
108 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
109 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
110 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
114 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), in ARMBaseInstrInfo()
226 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) in convertToThreeAddress()
235 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg) in convertToThreeAddress()
244 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) in convertToThreeAddress()
257 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) in convertToThreeAddress()
264 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) in convertToThreeAddress()
371 I->getOpcode() == ARM::t2DoLoopStartTP){ in analyzeBranch()
487 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); in insertBranch()
489 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); in insertBranch()
596 MI.getOperand(1).getReg() != ARM::CPSR) && in PredicateInstruction()
598 MI.getOperand(1).setReg(ARM::NoRegister); in PredicateInstruction()
638 bool ClobbersCPSR = MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR); in ClobbersPredicate()
639 bool IsCPSR = MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR; in ClobbersPredicate()
659 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead()) in isCPSRDefined()
667 case ARM::tADC: // ADC (register) T1 in isEligibleForITBlock()
668 case ARM::tADDi3: // ADD (immediate) T1 in isEligibleForITBlock()
669 case ARM::tADDi8: // ADD (immediate) T2 in isEligibleForITBlock()
670 case ARM::tADDrr: // ADD (register) T1 in isEligibleForITBlock()
671 case ARM::tAND: // AND (register) T1 in isEligibleForITBlock()
672 case ARM::tASRri: // ASR (immediate) T1 in isEligibleForITBlock()
673 case ARM::tASRrr: // ASR (register) T1 in isEligibleForITBlock()
674 case ARM::tBIC: // BIC (register) T1 in isEligibleForITBlock()
675 case ARM::tEOR: // EOR (register) T1 in isEligibleForITBlock()
676 case ARM::tLSLri: // LSL (immediate) T1 in isEligibleForITBlock()
677 case ARM::tLSLrr: // LSL (register) T1 in isEligibleForITBlock()
678 case ARM::tLSRri: // LSR (immediate) T1 in isEligibleForITBlock()
679 case ARM::tLSRrr: // LSR (register) T1 in isEligibleForITBlock()
680 case ARM::tMUL: // MUL T1 in isEligibleForITBlock()
681 case ARM::tMVN: // MVN (register) T1 in isEligibleForITBlock()
682 case ARM::tORR: // ORR (register) T1 in isEligibleForITBlock()
683 case ARM::tROR: // ROR (register) T1 in isEligibleForITBlock()
684 case ARM::tRSB: // RSB (immediate) T1 in isEligibleForITBlock()
685 case ARM::tSBC: // SBC (register) T1 in isEligibleForITBlock()
686 case ARM::tSUBi3: // SUB (immediate) T1 in isEligibleForITBlock()
687 case ARM::tSUBi8: // SUB (immediate) T2 in isEligibleForITBlock()
688 case ARM::tSUBrr: // SUB (register) T1 in isEligibleForITBlock()
738 if (MO.getReg() != ARM::CPSR) in IsCPSRDead()
766 case ARM::MOVi16_ga_pcrel: in getInstSizeInBytes()
767 case ARM::MOVTi16_ga_pcrel: in getInstSizeInBytes()
768 case ARM::t2MOVi16_ga_pcrel: in getInstSizeInBytes()
769 case ARM::t2MOVTi16_ga_pcrel: in getInstSizeInBytes()
771 case ARM::MOVi32imm: in getInstSizeInBytes()
772 case ARM::t2MOVi32imm: in getInstSizeInBytes()
774 case ARM::CONSTPOOL_ENTRY: in getInstSizeInBytes()
775 case ARM::JUMPTABLE_INSTS: in getInstSizeInBytes()
776 case ARM::JUMPTABLE_ADDRS: in getInstSizeInBytes()
777 case ARM::JUMPTABLE_TBB: in getInstSizeInBytes()
778 case ARM::JUMPTABLE_TBH: in getInstSizeInBytes()
782 case ARM::Int_eh_sjlj_longjmp: in getInstSizeInBytes()
784 case ARM::tInt_eh_sjlj_longjmp: in getInstSizeInBytes()
786 case ARM::tInt_WIN_eh_sjlj_longjmp: in getInstSizeInBytes()
788 case ARM::Int_eh_sjlj_setjmp: in getInstSizeInBytes()
789 case ARM::Int_eh_sjlj_setjmp_nofp: in getInstSizeInBytes()
791 case ARM::tInt_eh_sjlj_setjmp: in getInstSizeInBytes()
792 case ARM::t2Int_eh_sjlj_setjmp: in getInstSizeInBytes()
793 case ARM::t2Int_eh_sjlj_setjmp_nofp: in getInstSizeInBytes()
795 case ARM::SPACE: in getInstSizeInBytes()
797 case ARM::INLINEASM: in getInstSizeInBytes()
798 case ARM::INLINEASM_BR: { in getInstSizeInBytes()
805 case ARM::SpeculationBarrierISBDSBEndBB: in getInstSizeInBytes()
806 case ARM::t2SpeculationBarrierISBDSBEndBB: in getInstSizeInBytes()
809 case ARM::SpeculationBarrierSBEndBB: in getInstSizeInBytes()
810 case ARM::t2SpeculationBarrierSBEndBB: in getInstSizeInBytes()
832 ? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR) in copyFromCPSR()
833 : ARM::MRS; in copyFromCPSR()
844 .addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc)); in copyFromCPSR()
852 ? (Subtarget.isMClass() ? ARM::t2MSR_M : ARM::t2MSR_AR) in copyToCPSR()
853 : ARM::MSR; in copyToCPSR()
864 .addReg(ARM::CPSR, RegState::Implicit | RegState::Define); in copyToCPSR()
880 MIB.addReg(ARM::VPR, RegState::Implicit); in addPredicatedMveVpredNOp()
893 bool GPRDest = ARM::GPRRegClass.contains(DestReg); in copyPhysReg()
894 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); in copyPhysReg()
897 BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) in copyPhysReg()
904 bool SPRDest = ARM::SPRRegClass.contains(DestReg); in copyPhysReg()
905 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); in copyPhysReg()
909 Opc = ARM::VMOVS; in copyPhysReg()
911 Opc = ARM::VMOVRS; in copyPhysReg()
913 Opc = ARM::VMOVSR; in copyPhysReg()
914 else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && Subtarget.hasFP64()) in copyPhysReg()
915 Opc = ARM::VMOVD; in copyPhysReg()
916 else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
917 Opc = Subtarget.hasNEON() ? ARM::VORRq : ARM::MVE_VORR; in copyPhysReg()
922 if (Opc == ARM::VORRq || Opc == ARM::MVE_VORR) in copyPhysReg()
924 if (Opc == ARM::MVE_VORR) in copyPhysReg()
937 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
938 Opc = Subtarget.hasNEON() ? ARM::VORRq : ARM::MVE_VORR; in copyPhysReg()
939 BeginIdx = ARM::qsub_0; in copyPhysReg()
941 } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
942 Opc = Subtarget.hasNEON() ? ARM::VORRq : ARM::MVE_VORR; in copyPhysReg()
943 BeginIdx = ARM::qsub_0; in copyPhysReg()
946 } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
947 Opc = ARM::VMOVD; in copyPhysReg()
948 BeginIdx = ARM::dsub_0; in copyPhysReg()
950 } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
951 Opc = ARM::VMOVD; in copyPhysReg()
952 BeginIdx = ARM::dsub_0; in copyPhysReg()
954 } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
955 Opc = ARM::VMOVD; in copyPhysReg()
956 BeginIdx = ARM::dsub_0; in copyPhysReg()
958 } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
959 Opc = Subtarget.isThumb2() ? ARM::tMOVr : ARM::MOVr; in copyPhysReg()
960 BeginIdx = ARM::gsub_0; in copyPhysReg()
962 } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
963 Opc = ARM::VMOVD; in copyPhysReg()
964 BeginIdx = ARM::dsub_0; in copyPhysReg()
967 } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
968 Opc = ARM::VMOVD; in copyPhysReg()
969 BeginIdx = ARM::dsub_0; in copyPhysReg()
972 } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
973 Opc = ARM::VMOVD; in copyPhysReg()
974 BeginIdx = ARM::dsub_0; in copyPhysReg()
977 } else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && in copyPhysReg()
979 Opc = ARM::VMOVS; in copyPhysReg()
980 BeginIdx = ARM::ssub_0; in copyPhysReg()
982 } else if (SrcReg == ARM::CPSR) { in copyPhysReg()
985 } else if (DestReg == ARM::CPSR) { in copyPhysReg()
988 } else if (DestReg == ARM::VPR) { in copyPhysReg()
989 assert(ARM::GPRRegClass.contains(SrcReg)); in copyPhysReg()
990 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMSR_P0), DestReg) in copyPhysReg()
994 } else if (SrcReg == ARM::VPR) { in copyPhysReg()
995 assert(ARM::GPRRegClass.contains(DestReg)); in copyPhysReg()
996 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMRS_P0), DestReg) in copyPhysReg()
1000 } else if (DestReg == ARM::FPSCR_NZCV) { in copyPhysReg()
1001 assert(ARM::GPRRegClass.contains(SrcReg)); in copyPhysReg()
1002 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMSR_FPSCR_NZCVQC), DestReg) in copyPhysReg()
1006 } else if (SrcReg == ARM::FPSCR_NZCV) { in copyPhysReg()
1007 assert(ARM::GPRRegClass.contains(DestReg)); in copyPhysReg()
1008 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMRS_FPSCR_NZCVQC), DestReg) in copyPhysReg()
1037 if (Opc == ARM::VORRq || Opc == ARM::MVE_VORR) { in copyPhysReg()
1041 if (Opc == ARM::MVE_VORR) in copyPhysReg()
1046 if (Opc == ARM::MOVr) in copyPhysReg()
1065 (MI.getOpcode() == ARM::VORRq && in isCopyInstrImpl()
1128 if (ARM::HPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1129 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRH)) in storeRegToStackSlot()
1139 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1140 BuildMI(MBB, I, DebugLoc(), get(ARM::STRi12)) in storeRegToStackSlot()
1146 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1147 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRS)) in storeRegToStackSlot()
1153 } else if (ARM::VCCRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1154 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTR_P0_off)) in storeRegToStackSlot()
1164 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1165 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRD)) in storeRegToStackSlot()
1171 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1173 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STRD)); in storeRegToStackSlot()
1174 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
1175 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); in storeRegToStackSlot()
1181 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STMIA)) in storeRegToStackSlot()
1185 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
1186 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); in storeRegToStackSlot()
1192 if (ARM::DPairRegClass.hasSubClassEq(RC) && Subtarget.hasNEON()) { in storeRegToStackSlot()
1195 BuildMI(MBB, I, DebugLoc(), get(ARM::VST1q64)) in storeRegToStackSlot()
1202 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMQIA)) in storeRegToStackSlot()
1208 } else if (ARM::QPRRegClass.hasSubClassEq(RC) && in storeRegToStackSlot()
1210 auto MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::MVE_VSTRWU32)); in storeRegToStackSlot()
1220 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1224 BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64TPseudo)) in storeRegToStackSlot()
1232 get(ARM::VSTMDIA)) in storeRegToStackSlot()
1236 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
1237 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); in storeRegToStackSlot()
1238 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); in storeRegToStackSlot()
1244 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1249 BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64QPseudo)) in storeRegToStackSlot()
1257 get(ARM::VSTMDIA)) in storeRegToStackSlot()
1261 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
1262 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); in storeRegToStackSlot()
1263 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); in storeRegToStackSlot()
1264 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); in storeRegToStackSlot()
1270 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1271 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMDIA)) in storeRegToStackSlot()
1275 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
1276 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); in storeRegToStackSlot()
1277 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); in storeRegToStackSlot()
1278 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); in storeRegToStackSlot()
1279 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); in storeRegToStackSlot()
1280 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); in storeRegToStackSlot()
1281 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); in storeRegToStackSlot()
1282 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); in storeRegToStackSlot()
1295 case ARM::STRrs: in isStoreToStackSlot()
1296 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. in isStoreToStackSlot()
1304 case ARM::STRi12: in isStoreToStackSlot()
1305 case ARM::t2STRi12: in isStoreToStackSlot()
1306 case ARM::tSTRspi: in isStoreToStackSlot()
1307 case ARM::VSTRD: in isStoreToStackSlot()
1308 case ARM::VSTRS: in isStoreToStackSlot()
1309 case ARM::VSTR_P0_off: in isStoreToStackSlot()
1310 case ARM::MVE_VSTRWU32: in isStoreToStackSlot()
1317 case ARM::VST1q64: in isStoreToStackSlot()
1318 case ARM::VST1d64TPseudo: in isStoreToStackSlot()
1319 case ARM::VST1d64QPseudo: in isStoreToStackSlot()
1325 case ARM::VSTMQIA: in isStoreToStackSlot()
1365 if (ARM::HPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1366 BuildMI(MBB, I, DL, get(ARM::VLDRH), DestReg) in loadRegFromStackSlot()
1375 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1376 BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg) in loadRegFromStackSlot()
1381 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1382 BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) in loadRegFromStackSlot()
1387 } else if (ARM::VCCRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1388 BuildMI(MBB, I, DL, get(ARM::VLDR_P0_off), DestReg) in loadRegFromStackSlot()
1397 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1398 BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) in loadRegFromStackSlot()
1403 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1407 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD)); in loadRegFromStackSlot()
1408 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1409 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1415 MIB = BuildMI(MBB, I, DL, get(ARM::LDMIA)) in loadRegFromStackSlot()
1419 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1420 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1429 if (ARM::DPairRegClass.hasSubClassEq(RC) && Subtarget.hasNEON()) { in loadRegFromStackSlot()
1431 BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg) in loadRegFromStackSlot()
1437 BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg) in loadRegFromStackSlot()
1442 } else if (ARM::QPRRegClass.hasSubClassEq(RC) && in loadRegFromStackSlot()
1444 auto MIB = BuildMI(MBB, I, DL, get(ARM::MVE_VLDRWU32), DestReg); in loadRegFromStackSlot()
1453 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1456 BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg) in loadRegFromStackSlot()
1462 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) in loadRegFromStackSlot()
1466 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1467 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1468 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1476 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1479 BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) in loadRegFromStackSlot()
1485 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) in loadRegFromStackSlot()
1489 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1490 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1491 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1492 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1500 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1501 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) in loadRegFromStackSlot()
1505 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1506 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1507 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1508 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1509 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1510 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1511 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1512 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1527 case ARM::LDRrs: in isLoadFromStackSlot()
1528 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. in isLoadFromStackSlot()
1536 case ARM::LDRi12: in isLoadFromStackSlot()
1537 case ARM::t2LDRi12: in isLoadFromStackSlot()
1538 case ARM::tLDRspi: in isLoadFromStackSlot()
1539 case ARM::VLDRD: in isLoadFromStackSlot()
1540 case ARM::VLDRS: in isLoadFromStackSlot()
1541 case ARM::VLDR_P0_off: in isLoadFromStackSlot()
1542 case ARM::MVE_VLDRWU32: in isLoadFromStackSlot()
1549 case ARM::VLD1q64: in isLoadFromStackSlot()
1550 case ARM::VLD1d8TPseudo: in isLoadFromStackSlot()
1551 case ARM::VLD1d16TPseudo: in isLoadFromStackSlot()
1552 case ARM::VLD1d32TPseudo: in isLoadFromStackSlot()
1553 case ARM::VLD1d64TPseudo: in isLoadFromStackSlot()
1554 case ARM::VLD1d8QPseudo: in isLoadFromStackSlot()
1555 case ARM::VLD1d16QPseudo: in isLoadFromStackSlot()
1556 case ARM::VLD1d32QPseudo: in isLoadFromStackSlot()
1557 case ARM::VLD1d64QPseudo: in isLoadFromStackSlot()
1563 case ARM::VLDMQIA: in isLoadFromStackSlot()
1600 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA_UPD in expandMEMCPY()
1601 : isThumb1 ? ARM::tLDMIA_UPD in expandMEMCPY()
1602 : ARM::LDMIA_UPD)) in expandMEMCPY()
1605 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA : ARM::LDMIA)); in expandMEMCPY()
1610 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA_UPD in expandMEMCPY()
1611 : isThumb1 ? ARM::tSTMIA_UPD in expandMEMCPY()
1612 : ARM::STMIA_UPD)) in expandMEMCPY()
1615 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA : ARM::STMIA)); in expandMEMCPY()
1652 if (MI.getOpcode() == ARM::MEMCPY) { in expandPostRAPseudo()
1668 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS)) in expandPostRAPseudo()
1672 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0, in expandPostRAPseudo()
1673 &ARM::DPRRegClass); in expandPostRAPseudo()
1674 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0, in expandPostRAPseudo()
1675 &ARM::DPRRegClass); in expandPostRAPseudo()
1700 MI.setDesc(get(ARM::VMOVD)); in expandPostRAPseudo()
1781 case ARM::tLDRpci_pic: in reMaterialize()
1782 case ARM::t2LDRpci_pic: { in reMaterialize()
1803 case ARM::tLDRpci_pic: in duplicate()
1804 case ARM::t2LDRpci_pic: { in duplicate()
1824 if (Opcode == ARM::t2LDRpci || in produceSameValue()
1825 Opcode == ARM::t2LDRpci_pic || in produceSameValue()
1826 Opcode == ARM::tLDRpci || in produceSameValue()
1827 Opcode == ARM::tLDRpci_pic || in produceSameValue()
1828 Opcode == ARM::LDRLIT_ga_pcrel || in produceSameValue()
1829 Opcode == ARM::LDRLIT_ga_pcrel_ldr || in produceSameValue()
1830 Opcode == ARM::tLDRLIT_ga_pcrel || in produceSameValue()
1831 Opcode == ARM::MOV_ga_pcrel || in produceSameValue()
1832 Opcode == ARM::MOV_ga_pcrel_ldr || in produceSameValue()
1833 Opcode == ARM::t2MOV_ga_pcrel) { in produceSameValue()
1844 if (Opcode == ARM::LDRLIT_ga_pcrel || in produceSameValue()
1845 Opcode == ARM::LDRLIT_ga_pcrel_ldr || in produceSameValue()
1846 Opcode == ARM::tLDRLIT_ga_pcrel || in produceSameValue()
1847 Opcode == ARM::MOV_ga_pcrel || in produceSameValue()
1848 Opcode == ARM::MOV_ga_pcrel_ldr || in produceSameValue()
1849 Opcode == ARM::t2MOV_ga_pcrel) in produceSameValue()
1871 } else if (Opcode == ARM::PICLDR) { in produceSameValue()
1926 case ARM::LDRi12: in areLoadsFromSameBasePtr()
1927 case ARM::LDRBi12: in areLoadsFromSameBasePtr()
1928 case ARM::LDRD: in areLoadsFromSameBasePtr()
1929 case ARM::LDRH: in areLoadsFromSameBasePtr()
1930 case ARM::LDRSB: in areLoadsFromSameBasePtr()
1931 case ARM::LDRSH: in areLoadsFromSameBasePtr()
1932 case ARM::VLDRD: in areLoadsFromSameBasePtr()
1933 case ARM::VLDRS: in areLoadsFromSameBasePtr()
1934 case ARM::t2LDRi8: in areLoadsFromSameBasePtr()
1935 case ARM::t2LDRBi8: in areLoadsFromSameBasePtr()
1936 case ARM::t2LDRDi8: in areLoadsFromSameBasePtr()
1937 case ARM::t2LDRSHi8: in areLoadsFromSameBasePtr()
1938 case ARM::t2LDRi12: in areLoadsFromSameBasePtr()
1939 case ARM::t2LDRBi12: in areLoadsFromSameBasePtr()
1940 case ARM::t2LDRSHi12: in areLoadsFromSameBasePtr()
1947 case ARM::LDRi12: in areLoadsFromSameBasePtr()
1948 case ARM::LDRBi12: in areLoadsFromSameBasePtr()
1949 case ARM::LDRD: in areLoadsFromSameBasePtr()
1950 case ARM::LDRH: in areLoadsFromSameBasePtr()
1951 case ARM::LDRSB: in areLoadsFromSameBasePtr()
1952 case ARM::LDRSH: in areLoadsFromSameBasePtr()
1953 case ARM::VLDRD: in areLoadsFromSameBasePtr()
1954 case ARM::VLDRS: in areLoadsFromSameBasePtr()
1955 case ARM::t2LDRi8: in areLoadsFromSameBasePtr()
1956 case ARM::t2LDRBi8: in areLoadsFromSameBasePtr()
1957 case ARM::t2LDRSHi8: in areLoadsFromSameBasePtr()
1958 case ARM::t2LDRi12: in areLoadsFromSameBasePtr()
1959 case ARM::t2LDRBi12: in areLoadsFromSameBasePtr()
1960 case ARM::t2LDRSHi12: in areLoadsFromSameBasePtr()
2012 !((Load1->getMachineOpcode() == ARM::t2LDRBi8 && in shouldScheduleLoadsNear()
2013 Load2->getMachineOpcode() == ARM::t2LDRBi12) || in shouldScheduleLoadsNear()
2014 (Load1->getMachineOpcode() == ARM::t2LDRBi12 && in shouldScheduleLoadsNear()
2015 Load2->getMachineOpcode() == ARM::t2LDRBi8))) in shouldScheduleLoadsNear()
2055 if (I != MBB->end() && I->getOpcode() == ARM::t2IT) in isSchedulingBoundary()
2066 if (!MI.isCall() && MI.definesRegister(ARM::SP)) in isSchedulingBoundary()
2086 if (LastMI->getOpcode() == ARM::t2Bcc) { in isProfitableToIfCvt()
2181 if (MI.getOpcode() == ARM::t2Bcc && in predictBranchSizeForIfCvt()
2223 if (Opc == ARM::B) in getMatchingCondBranchOpcode()
2224 return ARM::Bcc; in getMatchingCondBranchOpcode()
2225 if (Opc == ARM::tB) in getMatchingCondBranchOpcode()
2226 return ARM::tBcc; in getMatchingCondBranchOpcode()
2227 if (Opc == ARM::t2B) in getMatchingCondBranchOpcode()
2228 return ARM::t2Bcc; in getMatchingCondBranchOpcode()
2238 case ARM::MOVCCr: in commuteInstructionImpl()
2239 case ARM::t2MOVCCr: { in commuteInstructionImpl()
2244 if (CC == ARMCC::AL || PredReg != ARM::CPSR) in commuteInstructionImpl()
2301 assert((MI.getOpcode() == ARM::MOVCCr || MI.getOpcode() == ARM::t2MOVCCr) && in analyzeSelect()
2322 assert((MI.getOpcode() == ARM::MOVCCr || MI.getOpcode() == ARM::t2MOVCCr) && in optimizeSelect()
2397 {ARM::ADDSri, ARM::ADDri},
2398 {ARM::ADDSrr, ARM::ADDrr},
2399 {ARM::ADDSrsi, ARM::ADDrsi},
2400 {ARM::ADDSrsr, ARM::ADDrsr},
2402 {ARM::SUBSri, ARM::SUBri},
2403 {ARM::SUBSrr, ARM::SUBrr},
2404 {ARM::SUBSrsi, ARM::SUBrsi},
2405 {ARM::SUBSrsr, ARM::SUBrsr},
2407 {ARM::RSBSri, ARM::RSBri},
2408 {ARM::RSBSrsi, ARM::RSBrsi},
2409 {ARM::RSBSrsr, ARM::RSBrsr},
2411 {ARM::tADDSi3, ARM::tADDi3},
2412 {ARM::tADDSi8, ARM::tADDi8},
2413 {ARM::tADDSrr, ARM::tADDrr},
2414 {ARM::tADCS, ARM::tADC},
2416 {ARM::tSUBSi3, ARM::tSUBi3},
2417 {ARM::tSUBSi8, ARM::tSUBi8},
2418 {ARM::tSUBSrr, ARM::tSUBrr},
2419 {ARM::tSBCS, ARM::tSBC},
2420 {ARM::tRSBS, ARM::tRSB},
2421 {ARM::tLSLSri, ARM::tLSLri},
2423 {ARM::t2ADDSri, ARM::t2ADDri},
2424 {ARM::t2ADDSrr, ARM::t2ADDrr},
2425 {ARM::t2ADDSrs, ARM::t2ADDrs},
2427 {ARM::t2SUBSri, ARM::t2SUBri},
2428 {ARM::t2SUBSrr, ARM::t2SUBrr},
2429 {ARM::t2SUBSrs, ARM::t2SUBrs},
2431 {ARM::t2RSBSri, ARM::t2RSBri},
2432 {ARM::t2RSBSrs, ARM::t2RSBrs},
2450 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg) in emitARMRegPlusImmediate()
2472 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; in emitARMRegPlusImmediate()
2499 bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD || in tryFoldSPUpdateIntoPushPop()
2500 MI->getOpcode() == ARM::VLDMDIA_UPD; in tryFoldSPUpdateIntoPushPop()
2501 bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH || in tryFoldSPUpdateIntoPushPop()
2502 MI->getOpcode() == ARM::tPOP || in tryFoldSPUpdateIntoPushPop()
2503 MI->getOpcode() == ARM::tPOP_RET; in tryFoldSPUpdateIntoPushPop()
2505 assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP && in tryFoldSPUpdateIntoPushPop()
2506 MI->getOperand(1).getReg() == ARM::SP)) && in tryFoldSPUpdateIntoPushPop()
2524 RegClass = &ARM::DPRRegClass; in tryFoldSPUpdateIntoPushPop()
2527 RegClass = &ARM::GPRRegClass; in tryFoldSPUpdateIntoPushPop()
2555 if (IsT1PushPop && CurRegEnc > TRI->getEncodingValue(ARM::R7)) in tryFoldSPUpdateIntoPushPop()
2614 if (Opcode == ARM::INLINEASM || Opcode == ARM::INLINEASM_BR) in rewriteARMFrameIndex()
2617 if (Opcode == ARM::ADDri) { in rewriteARMFrameIndex()
2621 MI.setDesc(TII.get(ARM::MOVr)); in rewriteARMFrameIndex()
2629 MI.setDesc(TII.get(ARM::SUBri)); in rewriteARMFrameIndex()
2767 case ARM::CMPri: in analyzeCompare()
2768 case ARM::t2CMPri: in analyzeCompare()
2769 case ARM::tCMPi8: in analyzeCompare()
2775 case ARM::CMPrr: in analyzeCompare()
2776 case ARM::t2CMPrr: in analyzeCompare()
2777 case ARM::tCMPr: in analyzeCompare()
2783 case ARM::TSTri: in analyzeCompare()
2784 case ARM::t2TSTri: in analyzeCompare()
2802 case ARM::ANDri: in isSuitableForMask()
2803 case ARM::t2ANDri: in isSuitableForMask()
2837 if ((CmpI->getOpcode() == ARM::CMPrr || CmpI->getOpcode() == ARM::t2CMPrr) && in isRedundantFlagInstr()
2838 (OI->getOpcode() == ARM::SUBrr || OI->getOpcode() == ARM::t2SUBrr) && in isRedundantFlagInstr()
2847 if (CmpI->getOpcode() == ARM::tCMPr && OI->getOpcode() == ARM::tSUBrr && in isRedundantFlagInstr()
2856 if ((CmpI->getOpcode() == ARM::CMPri || CmpI->getOpcode() == ARM::t2CMPri) && in isRedundantFlagInstr()
2857 (OI->getOpcode() == ARM::SUBri || OI->getOpcode() == ARM::t2SUBri) && in isRedundantFlagInstr()
2864 if (CmpI->getOpcode() == ARM::tCMPi8 && in isRedundantFlagInstr()
2865 (OI->getOpcode() == ARM::tSUBi8 || OI->getOpcode() == ARM::tSUBi3) && in isRedundantFlagInstr()
2872 if ((CmpI->getOpcode() == ARM::CMPrr || CmpI->getOpcode() == ARM::t2CMPrr) && in isRedundantFlagInstr()
2873 (OI->getOpcode() == ARM::ADDrr || OI->getOpcode() == ARM::t2ADDrr || in isRedundantFlagInstr()
2874 OI->getOpcode() == ARM::ADDri || OI->getOpcode() == ARM::t2ADDri) && in isRedundantFlagInstr()
2882 if (CmpI->getOpcode() == ARM::tCMPr && in isRedundantFlagInstr()
2883 (OI->getOpcode() == ARM::tADDi3 || OI->getOpcode() == ARM::tADDi8 || in isRedundantFlagInstr()
2884 OI->getOpcode() == ARM::tADDrr) && in isRedundantFlagInstr()
2897 case ARM::tLSLri: in isOptimizeCompareCandidate()
2898 case ARM::tLSRri: in isOptimizeCompareCandidate()
2899 case ARM::tLSLrr: in isOptimizeCompareCandidate()
2900 case ARM::tLSRrr: in isOptimizeCompareCandidate()
2901 case ARM::tSUBrr: in isOptimizeCompareCandidate()
2902 case ARM::tADDrr: in isOptimizeCompareCandidate()
2903 case ARM::tADDi3: in isOptimizeCompareCandidate()
2904 case ARM::tADDi8: in isOptimizeCompareCandidate()
2905 case ARM::tSUBi3: in isOptimizeCompareCandidate()
2906 case ARM::tSUBi8: in isOptimizeCompareCandidate()
2907 case ARM::tMUL: in isOptimizeCompareCandidate()
2908 case ARM::tADC: in isOptimizeCompareCandidate()
2909 case ARM::tSBC: in isOptimizeCompareCandidate()
2910 case ARM::tRSB: in isOptimizeCompareCandidate()
2911 case ARM::tAND: in isOptimizeCompareCandidate()
2912 case ARM::tORR: in isOptimizeCompareCandidate()
2913 case ARM::tEOR: in isOptimizeCompareCandidate()
2914 case ARM::tBIC: in isOptimizeCompareCandidate()
2915 case ARM::tMVN: in isOptimizeCompareCandidate()
2916 case ARM::tASRri: in isOptimizeCompareCandidate()
2917 case ARM::tASRrr: in isOptimizeCompareCandidate()
2918 case ARM::tROR: in isOptimizeCompareCandidate()
2921 case ARM::RSBrr: in isOptimizeCompareCandidate()
2922 case ARM::RSBri: in isOptimizeCompareCandidate()
2923 case ARM::RSCrr: in isOptimizeCompareCandidate()
2924 case ARM::RSCri: in isOptimizeCompareCandidate()
2925 case ARM::ADDrr: in isOptimizeCompareCandidate()
2926 case ARM::ADDri: in isOptimizeCompareCandidate()
2927 case ARM::ADCrr: in isOptimizeCompareCandidate()
2928 case ARM::ADCri: in isOptimizeCompareCandidate()
2929 case ARM::SUBrr: in isOptimizeCompareCandidate()
2930 case ARM::SUBri: in isOptimizeCompareCandidate()
2931 case ARM::SBCrr: in isOptimizeCompareCandidate()
2932 case ARM::SBCri: in isOptimizeCompareCandidate()
2933 case ARM::t2RSBri: in isOptimizeCompareCandidate()
2934 case ARM::t2ADDrr: in isOptimizeCompareCandidate()
2935 case ARM::t2ADDri: in isOptimizeCompareCandidate()
2936 case ARM::t2ADCrr: in isOptimizeCompareCandidate()
2937 case ARM::t2ADCri: in isOptimizeCompareCandidate()
2938 case ARM::t2SUBrr: in isOptimizeCompareCandidate()
2939 case ARM::t2SUBri: in isOptimizeCompareCandidate()
2940 case ARM::t2SBCrr: in isOptimizeCompareCandidate()
2941 case ARM::t2SBCri: in isOptimizeCompareCandidate()
2942 case ARM::ANDrr: in isOptimizeCompareCandidate()
2943 case ARM::ANDri: in isOptimizeCompareCandidate()
2944 case ARM::t2ANDrr: in isOptimizeCompareCandidate()
2945 case ARM::t2ANDri: in isOptimizeCompareCandidate()
2946 case ARM::ORRrr: in isOptimizeCompareCandidate()
2947 case ARM::ORRri: in isOptimizeCompareCandidate()
2948 case ARM::t2ORRrr: in isOptimizeCompareCandidate()
2949 case ARM::t2ORRri: in isOptimizeCompareCandidate()
2950 case ARM::EORrr: in isOptimizeCompareCandidate()
2951 case ARM::EORri: in isOptimizeCompareCandidate()
2952 case ARM::t2EORrr: in isOptimizeCompareCandidate()
2953 case ARM::t2EORri: in isOptimizeCompareCandidate()
2954 case ARM::t2LSRri: in isOptimizeCompareCandidate()
2955 case ARM::t2LSRrr: in isOptimizeCompareCandidate()
2956 case ARM::t2LSLri: in isOptimizeCompareCandidate()
2957 case ARM::t2LSLrr: in isOptimizeCompareCandidate()
3017 if (CmpInstr.getOpcode() == ARM::CMPri || in optimizeCompareInstr()
3018 CmpInstr.getOpcode() == ARM::t2CMPri || in optimizeCompareInstr()
3019 CmpInstr.getOpcode() == ARM::tCMPi8) in optimizeCompareInstr()
3044 if (I != E && !MI->readsRegister(ARM::CPSR, TRI)) { in optimizeCompareInstr()
3047 if (I->getOpcode() != ARM::tMOVi8) { in optimizeCompareInstr()
3079 if (Instr.modifiesRegister(ARM::CPSR, TRI) || in optimizeCompareInstr()
3080 Instr.readsRegister(ARM::CPSR, TRI)) in optimizeCompareInstr()
3125 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) { in optimizeCompareInstr()
3129 if (!MO.isReg() || MO.getReg() != ARM::CPSR) in optimizeCompareInstr()
3143 case ARM::VSELEQD: in optimizeCompareInstr()
3144 case ARM::VSELEQS: in optimizeCompareInstr()
3145 case ARM::VSELEQH: in optimizeCompareInstr()
3148 case ARM::VSELGTD: in optimizeCompareInstr()
3149 case ARM::VSELGTS: in optimizeCompareInstr()
3150 case ARM::VSELGTH: in optimizeCompareInstr()
3153 case ARM::VSELGED: in optimizeCompareInstr()
3154 case ARM::VSELGES: in optimizeCompareInstr()
3155 case ARM::VSELGEH: in optimizeCompareInstr()
3158 case ARM::VSELVSD: in optimizeCompareInstr()
3159 case ARM::VSELVSS: in optimizeCompareInstr()
3160 case ARM::VSELVSH: in optimizeCompareInstr()
3174 bool IsSub = Opc == ARM::SUBrr || Opc == ARM::t2SUBrr || in optimizeCompareInstr()
3175 Opc == ARM::SUBri || Opc == ARM::t2SUBri || in optimizeCompareInstr()
3176 Opc == ARM::tSUBrr || Opc == ARM::tSUBi3 || in optimizeCompareInstr()
3177 Opc == ARM::tSUBi8; in optimizeCompareInstr()
3178 unsigned OpI = Opc != ARM::tSUBrr ? 1 : 2; in optimizeCompareInstr()
3225 if ((*SI)->isLiveIn(ARM::CPSR)) in optimizeCompareInstr()
3232 MI->getOperand(5).setReg(ARM::CPSR); in optimizeCompareInstr()
3244 MI->clearRegisterDeads(ARM::CPSR); in optimizeCompareInstr()
3272 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm) in FoldImmediate()
3285 if (MO.getReg() == ARM::CPSR && !MO.isDead()) in FoldImmediate()
3294 if (UseMI.getOperand(NumOps - 1).getReg() == ARM::CPSR) in FoldImmediate()
3307 case ARM::SUBrr: in FoldImmediate()
3308 case ARM::ADDrr: in FoldImmediate()
3309 case ARM::ORRrr: in FoldImmediate()
3310 case ARM::EORrr: in FoldImmediate()
3311 case ARM::t2SUBrr: in FoldImmediate()
3312 case ARM::t2ADDrr: in FoldImmediate()
3313 case ARM::t2ORRrr: in FoldImmediate()
3314 case ARM::t2EORrr: { in FoldImmediate()
3318 case ARM::ADDrr: in FoldImmediate()
3319 case ARM::SUBrr: in FoldImmediate()
3320 if (UseOpc == ARM::SUBrr && Commute) in FoldImmediate()
3326 NewUseOpc = UseOpc == ARM::ADDrr ? ARM::ADDri : ARM::SUBri; in FoldImmediate()
3329 NewUseOpc = UseOpc == ARM::ADDrr ? ARM::SUBri : ARM::ADDri; in FoldImmediate()
3335 case ARM::ORRrr: in FoldImmediate()
3336 case ARM::EORrr: in FoldImmediate()
3343 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break; in FoldImmediate()
3344 case ARM::EORrr: NewUseOpc = ARM::EORri; break; in FoldImmediate()
3347 case ARM::t2ADDrr: in FoldImmediate()
3348 case ARM::t2SUBrr: { in FoldImmediate()
3349 if (UseOpc == ARM::t2SUBrr && Commute) in FoldImmediate()
3354 const bool ToSP = DefMI.getOperand(0).getReg() == ARM::SP; in FoldImmediate()
3355 const unsigned t2ADD = ToSP ? ARM::t2ADDspImm : ARM::t2ADDri; in FoldImmediate()
3356 const unsigned t2SUB = ToSP ? ARM::t2SUBspImm : ARM::t2SUBri; in FoldImmediate()
3358 NewUseOpc = UseOpc == ARM::t2ADDrr ? t2ADD : t2SUB; in FoldImmediate()
3361 NewUseOpc = UseOpc == ARM::t2ADDrr ? t2SUB : t2ADD; in FoldImmediate()
3368 case ARM::t2ORRrr: in FoldImmediate()
3369 case ARM::t2EORrr: in FoldImmediate()
3376 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break; in FoldImmediate()
3377 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break; in FoldImmediate()
3406 case ARM::t2ADDspImm: in FoldImmediate()
3407 case ARM::t2SUBspImm: in FoldImmediate()
3408 case ARM::t2ADDri: in FoldImmediate()
3409 case ARM::t2SUBri: in FoldImmediate()
3425 case ARM::LDRrs: in getNumMicroOpsSwiftLdSt()
3426 case ARM::LDRBrs: in getNumMicroOpsSwiftLdSt()
3427 case ARM::STRrs: in getNumMicroOpsSwiftLdSt()
3428 case ARM::STRBrs: { in getNumMicroOpsSwiftLdSt()
3440 case ARM::LDRH: in getNumMicroOpsSwiftLdSt()
3441 case ARM::STRH: { in getNumMicroOpsSwiftLdSt()
3456 case ARM::LDRSB: in getNumMicroOpsSwiftLdSt()
3457 case ARM::LDRSH: in getNumMicroOpsSwiftLdSt()
3460 case ARM::LDRSB_POST: in getNumMicroOpsSwiftLdSt()
3461 case ARM::LDRSH_POST: { in getNumMicroOpsSwiftLdSt()
3467 case ARM::LDR_PRE_REG: in getNumMicroOpsSwiftLdSt()
3468 case ARM::LDRB_PRE_REG: { in getNumMicroOpsSwiftLdSt()
3484 case ARM::STR_PRE_REG: in getNumMicroOpsSwiftLdSt()
3485 case ARM::STRB_PRE_REG: { in getNumMicroOpsSwiftLdSt()
3497 case ARM::LDRH_PRE: in getNumMicroOpsSwiftLdSt()
3498 case ARM::STRH_PRE: { in getNumMicroOpsSwiftLdSt()
3508 case ARM::LDR_POST_REG: in getNumMicroOpsSwiftLdSt()
3509 case ARM::LDRB_POST_REG: in getNumMicroOpsSwiftLdSt()
3510 case ARM::LDRH_POST: { in getNumMicroOpsSwiftLdSt()
3516 case ARM::LDR_PRE_IMM: in getNumMicroOpsSwiftLdSt()
3517 case ARM::LDRB_PRE_IMM: in getNumMicroOpsSwiftLdSt()
3518 case ARM::LDR_POST_IMM: in getNumMicroOpsSwiftLdSt()
3519 case ARM::LDRB_POST_IMM: in getNumMicroOpsSwiftLdSt()
3520 case ARM::STRB_POST_IMM: in getNumMicroOpsSwiftLdSt()
3521 case ARM::STRB_POST_REG: in getNumMicroOpsSwiftLdSt()
3522 case ARM::STRB_PRE_IMM: in getNumMicroOpsSwiftLdSt()
3523 case ARM::STRH_POST: in getNumMicroOpsSwiftLdSt()
3524 case ARM::STR_POST_IMM: in getNumMicroOpsSwiftLdSt()
3525 case ARM::STR_POST_REG: in getNumMicroOpsSwiftLdSt()
3526 case ARM::STR_PRE_IMM: in getNumMicroOpsSwiftLdSt()
3529 case ARM::LDRSB_PRE: in getNumMicroOpsSwiftLdSt()
3530 case ARM::LDRSH_PRE: { in getNumMicroOpsSwiftLdSt()
3548 case ARM::LDRD: { in getNumMicroOpsSwiftLdSt()
3558 case ARM::STRD: { in getNumMicroOpsSwiftLdSt()
3566 case ARM::LDRD_POST: in getNumMicroOpsSwiftLdSt()
3567 case ARM::t2LDRD_POST: in getNumMicroOpsSwiftLdSt()
3570 case ARM::STRD_POST: in getNumMicroOpsSwiftLdSt()
3571 case ARM::t2STRD_POST: in getNumMicroOpsSwiftLdSt()
3574 case ARM::LDRD_PRE: { in getNumMicroOpsSwiftLdSt()
3584 case ARM::t2LDRD_PRE: { in getNumMicroOpsSwiftLdSt()
3590 case ARM::STRD_PRE: { in getNumMicroOpsSwiftLdSt()
3598 case ARM::t2STRD_PRE: in getNumMicroOpsSwiftLdSt()
3601 case ARM::t2LDR_POST: in getNumMicroOpsSwiftLdSt()
3602 case ARM::t2LDRB_POST: in getNumMicroOpsSwiftLdSt()
3603 case ARM::t2LDRB_PRE: in getNumMicroOpsSwiftLdSt()
3604 case ARM::t2LDRSBi12: in getNumMicroOpsSwiftLdSt()
3605 case ARM::t2LDRSBi8: in getNumMicroOpsSwiftLdSt()
3606 case ARM::t2LDRSBpci: in getNumMicroOpsSwiftLdSt()
3607 case ARM::t2LDRSBs: in getNumMicroOpsSwiftLdSt()
3608 case ARM::t2LDRH_POST: in getNumMicroOpsSwiftLdSt()
3609 case ARM::t2LDRH_PRE: in getNumMicroOpsSwiftLdSt()
3610 case ARM::t2LDRSBT: in getNumMicroOpsSwiftLdSt()
3611 case ARM::t2LDRSB_POST: in getNumMicroOpsSwiftLdSt()
3612 case ARM::t2LDRSB_PRE: in getNumMicroOpsSwiftLdSt()
3613 case ARM::t2LDRSH_POST: in getNumMicroOpsSwiftLdSt()
3614 case ARM::t2LDRSH_PRE: in getNumMicroOpsSwiftLdSt()
3615 case ARM::t2LDRSHi12: in getNumMicroOpsSwiftLdSt()
3616 case ARM::t2LDRSHi8: in getNumMicroOpsSwiftLdSt()
3617 case ARM::t2LDRSHpci: in getNumMicroOpsSwiftLdSt()
3618 case ARM::t2LDRSHs: in getNumMicroOpsSwiftLdSt()
3621 case ARM::t2LDRDi8: { in getNumMicroOpsSwiftLdSt()
3627 case ARM::t2STRB_POST: in getNumMicroOpsSwiftLdSt()
3628 case ARM::t2STRB_PRE: in getNumMicroOpsSwiftLdSt()
3629 case ARM::t2STRBs: in getNumMicroOpsSwiftLdSt()
3630 case ARM::t2STRDi8: in getNumMicroOpsSwiftLdSt()
3631 case ARM::t2STRH_POST: in getNumMicroOpsSwiftLdSt()
3632 case ARM::t2STRH_PRE: in getNumMicroOpsSwiftLdSt()
3633 case ARM::t2STRHs: in getNumMicroOpsSwiftLdSt()
3634 case ARM::t2STR_POST: in getNumMicroOpsSwiftLdSt()
3635 case ARM::t2STR_PRE: in getNumMicroOpsSwiftLdSt()
3636 case ARM::t2STRs: in getNumMicroOpsSwiftLdSt()
3684 case ARM::VLDMDIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3685 case ARM::VLDMDDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3686 case ARM::VLDMSIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3687 case ARM::VLDMSDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3688 case ARM::VSTMDIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3689 case ARM::VSTMDDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3690 case ARM::VSTMSIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3691 case ARM::VSTMSDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3692 case ARM::LDMIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3693 case ARM::LDMDA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3694 case ARM::LDMDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3695 case ARM::LDMIB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3696 case ARM::STMIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3697 case ARM::STMDA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3698 case ARM::STMDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3699 case ARM::STMIB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3700 case ARM::tLDMIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3701 case ARM::tSTMIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3702 case ARM::t2LDMIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3703 case ARM::t2LDMDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3704 case ARM::t2STMIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3705 case ARM::t2STMDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3708 case ARM::LDMIA_RET: in getNumMicroOpsSingleIssuePlusExtras()
3709 case ARM::tPOP_RET: in getNumMicroOpsSingleIssuePlusExtras()
3710 case ARM::t2LDMIA_RET: in getNumMicroOpsSingleIssuePlusExtras()
3736 case ARM::VLDMQIA: in getNumMicroOps()
3737 case ARM::VSTMQIA: in getNumMicroOps()
3750 case ARM::VLDMDIA: in getNumMicroOps()
3751 case ARM::VLDMDIA_UPD: in getNumMicroOps()
3752 case ARM::VLDMDDB_UPD: in getNumMicroOps()
3753 case ARM::VLDMSIA: in getNumMicroOps()
3754 case ARM::VLDMSIA_UPD: in getNumMicroOps()
3755 case ARM::VLDMSDB_UPD: in getNumMicroOps()
3756 case ARM::VSTMDIA: in getNumMicroOps()
3757 case ARM::VSTMDIA_UPD: in getNumMicroOps()
3758 case ARM::VSTMDDB_UPD: in getNumMicroOps()
3759 case ARM::VSTMSIA: in getNumMicroOps()
3760 case ARM::VSTMSIA_UPD: in getNumMicroOps()
3761 case ARM::VSTMSDB_UPD: { in getNumMicroOps()
3766 case ARM::LDMIA_RET: in getNumMicroOps()
3767 case ARM::LDMIA: in getNumMicroOps()
3768 case ARM::LDMDA: in getNumMicroOps()
3769 case ARM::LDMDB: in getNumMicroOps()
3770 case ARM::LDMIB: in getNumMicroOps()
3771 case ARM::LDMIA_UPD: in getNumMicroOps()
3772 case ARM::LDMDA_UPD: in getNumMicroOps()
3773 case ARM::LDMDB_UPD: in getNumMicroOps()
3774 case ARM::LDMIB_UPD: in getNumMicroOps()
3775 case ARM::STMIA: in getNumMicroOps()
3776 case ARM::STMDA: in getNumMicroOps()
3777 case ARM::STMDB: in getNumMicroOps()
3778 case ARM::STMIB: in getNumMicroOps()
3779 case ARM::STMIA_UPD: in getNumMicroOps()
3780 case ARM::STMDA_UPD: in getNumMicroOps()
3781 case ARM::STMDB_UPD: in getNumMicroOps()
3782 case ARM::STMIB_UPD: in getNumMicroOps()
3783 case ARM::tLDMIA: in getNumMicroOps()
3784 case ARM::tLDMIA_UPD: in getNumMicroOps()
3785 case ARM::tSTMIA_UPD: in getNumMicroOps()
3786 case ARM::tPOP_RET: in getNumMicroOps()
3787 case ARM::tPOP: in getNumMicroOps()
3788 case ARM::tPUSH: in getNumMicroOps()
3789 case ARM::t2LDMIA_RET: in getNumMicroOps()
3790 case ARM::t2LDMIA: in getNumMicroOps()
3791 case ARM::t2LDMDB: in getNumMicroOps()
3792 case ARM::t2LDMIA_UPD: in getNumMicroOps()
3793 case ARM::t2LDMDB_UPD: in getNumMicroOps()
3794 case ARM::t2STMIA: in getNumMicroOps()
3795 case ARM::t2STMDB: in getNumMicroOps()
3796 case ARM::t2STMIA_UPD: in getNumMicroOps()
3797 case ARM::t2STMDB_UPD: { in getNumMicroOps()
3852 case ARM::VLDMSIA: in getVLDMDefCycle()
3853 case ARM::VLDMSIA_UPD: in getVLDMDefCycle()
3854 case ARM::VLDMSDB_UPD: in getVLDMDefCycle()
3927 case ARM::VSTMSIA: in getVSTMUseCycle()
3928 case ARM::VSTMSIA_UPD: in getVSTMUseCycle()
3929 case ARM::VSTMSDB_UPD: in getVSTMUseCycle()
3997 case ARM::VLDMDIA: in getOperandLatency()
3998 case ARM::VLDMDIA_UPD: in getOperandLatency()
3999 case ARM::VLDMDDB_UPD: in getOperandLatency()
4000 case ARM::VLDMSIA: in getOperandLatency()
4001 case ARM::VLDMSIA_UPD: in getOperandLatency()
4002 case ARM::VLDMSDB_UPD: in getOperandLatency()
4006 case ARM::LDMIA_RET: in getOperandLatency()
4007 case ARM::LDMIA: in getOperandLatency()
4008 case ARM::LDMDA: in getOperandLatency()
4009 case ARM::LDMDB: in getOperandLatency()
4010 case ARM::LDMIB: in getOperandLatency()
4011 case ARM::LDMIA_UPD: in getOperandLatency()
4012 case ARM::LDMDA_UPD: in getOperandLatency()
4013 case ARM::LDMDB_UPD: in getOperandLatency()
4014 case ARM::LDMIB_UPD: in getOperandLatency()
4015 case ARM::tLDMIA: in getOperandLatency()
4016 case ARM::tLDMIA_UPD: in getOperandLatency()
4017 case ARM::tPUSH: in getOperandLatency()
4018 case ARM::t2LDMIA_RET: in getOperandLatency()
4019 case ARM::t2LDMIA: in getOperandLatency()
4020 case ARM::t2LDMDB: in getOperandLatency()
4021 case ARM::t2LDMIA_UPD: in getOperandLatency()
4022 case ARM::t2LDMDB_UPD: in getOperandLatency()
4038 case ARM::VSTMDIA: in getOperandLatency()
4039 case ARM::VSTMDIA_UPD: in getOperandLatency()
4040 case ARM::VSTMDDB_UPD: in getOperandLatency()
4041 case ARM::VSTMSIA: in getOperandLatency()
4042 case ARM::VSTMSIA_UPD: in getOperandLatency()
4043 case ARM::VSTMSDB_UPD: in getOperandLatency()
4047 case ARM::STMIA: in getOperandLatency()
4048 case ARM::STMDA: in getOperandLatency()
4049 case ARM::STMDB: in getOperandLatency()
4050 case ARM::STMIB: in getOperandLatency()
4051 case ARM::STMIA_UPD: in getOperandLatency()
4052 case ARM::STMDA_UPD: in getOperandLatency()
4053 case ARM::STMDB_UPD: in getOperandLatency()
4054 case ARM::STMIB_UPD: in getOperandLatency()
4055 case ARM::tSTMIA_UPD: in getOperandLatency()
4056 case ARM::tPOP_RET: in getOperandLatency()
4057 case ARM::tPOP: in getOperandLatency()
4058 case ARM::t2STMIA: in getOperandLatency()
4059 case ARM::t2STMDB: in getOperandLatency()
4060 case ARM::t2STMIA_UPD: in getOperandLatency()
4061 case ARM::t2STMDB_UPD: in getOperandLatency()
4125 if (II->getOpcode() != ARM::t2IT) in getBundledUseMI()
4151 case ARM::LDRrs: in adjustDefLatency()
4152 case ARM::LDRBrs: { in adjustDefLatency()
4160 case ARM::t2LDRs: in adjustDefLatency()
4161 case ARM::t2LDRBs: in adjustDefLatency()
4162 case ARM::t2LDRHs: in adjustDefLatency()
4163 case ARM::t2LDRSHs: { in adjustDefLatency()
4176 case ARM::LDRrs: in adjustDefLatency()
4177 case ARM::LDRBrs: { in adjustDefLatency()
4191 case ARM::t2LDRs: in adjustDefLatency()
4192 case ARM::t2LDRBs: in adjustDefLatency()
4193 case ARM::t2LDRHs: in adjustDefLatency()
4194 case ARM::t2LDRSHs: { in adjustDefLatency()
4207 case ARM::VLD1q8: in adjustDefLatency()
4208 case ARM::VLD1q16: in adjustDefLatency()
4209 case ARM::VLD1q32: in adjustDefLatency()
4210 case ARM::VLD1q64: in adjustDefLatency()
4211 case ARM::VLD1q8wb_fixed: in adjustDefLatency()
4212 case ARM::VLD1q16wb_fixed: in adjustDefLatency()
4213 case ARM::VLD1q32wb_fixed: in adjustDefLatency()
4214 case ARM::VLD1q64wb_fixed: in adjustDefLatency()
4215 case ARM::VLD1q8wb_register: in adjustDefLatency()
4216 case ARM::VLD1q16wb_register: in adjustDefLatency()
4217 case ARM::VLD1q32wb_register: in adjustDefLatency()
4218 case ARM::VLD1q64wb_register: in adjustDefLatency()
4219 case ARM::VLD2d8: in adjustDefLatency()
4220 case ARM::VLD2d16: in adjustDefLatency()
4221 case ARM::VLD2d32: in adjustDefLatency()
4222 case ARM::VLD2q8: in adjustDefLatency()
4223 case ARM::VLD2q16: in adjustDefLatency()
4224 case ARM::VLD2q32: in adjustDefLatency()
4225 case ARM::VLD2d8wb_fixed: in adjustDefLatency()
4226 case ARM::VLD2d16wb_fixed: in adjustDefLatency()
4227 case ARM::VLD2d32wb_fixed: in adjustDefLatency()
4228 case ARM::VLD2q8wb_fixed: in adjustDefLatency()
4229 case ARM::VLD2q16wb_fixed: in adjustDefLatency()
4230 case ARM::VLD2q32wb_fixed: in adjustDefLatency()
4231 case ARM::VLD2d8wb_register: in adjustDefLatency()
4232 case ARM::VLD2d16wb_register: in adjustDefLatency()
4233 case ARM::VLD2d32wb_register: in adjustDefLatency()
4234 case ARM::VLD2q8wb_register: in adjustDefLatency()
4235 case ARM::VLD2q16wb_register: in adjustDefLatency()
4236 case ARM::VLD2q32wb_register: in adjustDefLatency()
4237 case ARM::VLD3d8: in adjustDefLatency()
4238 case ARM::VLD3d16: in adjustDefLatency()
4239 case ARM::VLD3d32: in adjustDefLatency()
4240 case ARM::VLD1d64T: in adjustDefLatency()
4241 case ARM::VLD3d8_UPD: in adjustDefLatency()
4242 case ARM::VLD3d16_UPD: in adjustDefLatency()
4243 case ARM::VLD3d32_UPD: in adjustDefLatency()
4244 case ARM::VLD1d64Twb_fixed: in adjustDefLatency()
4245 case ARM::VLD1d64Twb_register: in adjustDefLatency()
4246 case ARM::VLD3q8_UPD: in adjustDefLatency()
4247 case ARM::VLD3q16_UPD: in adjustDefLatency()
4248 case ARM::VLD3q32_UPD: in adjustDefLatency()
4249 case ARM::VLD4d8: in adjustDefLatency()
4250 case ARM::VLD4d16: in adjustDefLatency()
4251 case ARM::VLD4d32: in adjustDefLatency()
4252 case ARM::VLD1d64Q: in adjustDefLatency()
4253 case ARM::VLD4d8_UPD: in adjustDefLatency()
4254 case ARM::VLD4d16_UPD: in adjustDefLatency()
4255 case ARM::VLD4d32_UPD: in adjustDefLatency()
4256 case ARM::VLD1d64Qwb_fixed: in adjustDefLatency()
4257 case ARM::VLD1d64Qwb_register: in adjustDefLatency()
4258 case ARM::VLD4q8_UPD: in adjustDefLatency()
4259 case ARM::VLD4q16_UPD: in adjustDefLatency()
4260 case ARM::VLD4q32_UPD: in adjustDefLatency()
4261 case ARM::VLD1DUPq8: in adjustDefLatency()
4262 case ARM::VLD1DUPq16: in adjustDefLatency()
4263 case ARM::VLD1DUPq32: in adjustDefLatency()
4264 case ARM::VLD1DUPq8wb_fixed: in adjustDefLatency()
4265 case ARM::VLD1DUPq16wb_fixed: in adjustDefLatency()
4266 case ARM::VLD1DUPq32wb_fixed: in adjustDefLatency()
4267 case ARM::VLD1DUPq8wb_register: in adjustDefLatency()
4268 case ARM::VLD1DUPq16wb_register: in adjustDefLatency()
4269 case ARM::VLD1DUPq32wb_register: in adjustDefLatency()
4270 case ARM::VLD2DUPd8: in adjustDefLatency()
4271 case ARM::VLD2DUPd16: in adjustDefLatency()
4272 case ARM::VLD2DUPd32: in adjustDefLatency()
4273 case ARM::VLD2DUPd8wb_fixed: in adjustDefLatency()
4274 case ARM::VLD2DUPd16wb_fixed: in adjustDefLatency()
4275 case ARM::VLD2DUPd32wb_fixed: in adjustDefLatency()
4276 case ARM::VLD2DUPd8wb_register: in adjustDefLatency()
4277 case ARM::VLD2DUPd16wb_register: in adjustDefLatency()
4278 case ARM::VLD2DUPd32wb_register: in adjustDefLatency()
4279 case ARM::VLD4DUPd8: in adjustDefLatency()
4280 case ARM::VLD4DUPd16: in adjustDefLatency()
4281 case ARM::VLD4DUPd32: in adjustDefLatency()
4282 case ARM::VLD4DUPd8_UPD: in adjustDefLatency()
4283 case ARM::VLD4DUPd16_UPD: in adjustDefLatency()
4284 case ARM::VLD4DUPd32_UPD: in adjustDefLatency()
4285 case ARM::VLD1LNd8: in adjustDefLatency()
4286 case ARM::VLD1LNd16: in adjustDefLatency()
4287 case ARM::VLD1LNd32: in adjustDefLatency()
4288 case ARM::VLD1LNd8_UPD: in adjustDefLatency()
4289 case ARM::VLD1LNd16_UPD: in adjustDefLatency()
4290 case ARM::VLD1LNd32_UPD: in adjustDefLatency()
4291 case ARM::VLD2LNd8: in adjustDefLatency()
4292 case ARM::VLD2LNd16: in adjustDefLatency()
4293 case ARM::VLD2LNd32: in adjustDefLatency()
4294 case ARM::VLD2LNq16: in adjustDefLatency()
4295 case ARM::VLD2LNq32: in adjustDefLatency()
4296 case ARM::VLD2LNd8_UPD: in adjustDefLatency()
4297 case ARM::VLD2LNd16_UPD: in adjustDefLatency()
4298 case ARM::VLD2LNd32_UPD: in adjustDefLatency()
4299 case ARM::VLD2LNq16_UPD: in adjustDefLatency()
4300 case ARM::VLD2LNq32_UPD: in adjustDefLatency()
4301 case ARM::VLD4LNd8: in adjustDefLatency()
4302 case ARM::VLD4LNd16: in adjustDefLatency()
4303 case ARM::VLD4LNd32: in adjustDefLatency()
4304 case ARM::VLD4LNq16: in adjustDefLatency()
4305 case ARM::VLD4LNq32: in adjustDefLatency()
4306 case ARM::VLD4LNd8_UPD: in adjustDefLatency()
4307 case ARM::VLD4LNd16_UPD: in adjustDefLatency()
4308 case ARM::VLD4LNd32_UPD: in adjustDefLatency()
4309 case ARM::VLD4LNq16_UPD: in adjustDefLatency()
4310 case ARM::VLD4LNq32_UPD: in adjustDefLatency()
4361 if (Reg == ARM::CPSR) { in getOperandLatencyImpl()
4362 if (DefMI.getOpcode() == ARM::FMSTAT) { in getOperandLatencyImpl()
4457 case ARM::LDRrs: in getOperandLatency()
4458 case ARM::LDRBrs: { in getOperandLatency()
4467 case ARM::t2LDRs: in getOperandLatency()
4468 case ARM::t2LDRBs: in getOperandLatency()
4469 case ARM::t2LDRHs: in getOperandLatency()
4470 case ARM::t2LDRSHs: { in getOperandLatency()
4484 case ARM::LDRrs: in getOperandLatency()
4485 case ARM::LDRBrs: { in getOperandLatency()
4497 case ARM::t2LDRs: in getOperandLatency()
4498 case ARM::t2LDRBs: in getOperandLatency()
4499 case ARM::t2LDRHs: in getOperandLatency()
4500 case ARM::t2LDRSHs: in getOperandLatency()
4510 case ARM::VLD1q8: in getOperandLatency()
4511 case ARM::VLD1q16: in getOperandLatency()
4512 case ARM::VLD1q32: in getOperandLatency()
4513 case ARM::VLD1q64: in getOperandLatency()
4514 case ARM::VLD1q8wb_register: in getOperandLatency()
4515 case ARM::VLD1q16wb_register: in getOperandLatency()
4516 case ARM::VLD1q32wb_register: in getOperandLatency()
4517 case ARM::VLD1q64wb_register: in getOperandLatency()
4518 case ARM::VLD1q8wb_fixed: in getOperandLatency()
4519 case ARM::VLD1q16wb_fixed: in getOperandLatency()
4520 case ARM::VLD1q32wb_fixed: in getOperandLatency()
4521 case ARM::VLD1q64wb_fixed: in getOperandLatency()
4522 case ARM::VLD2d8: in getOperandLatency()
4523 case ARM::VLD2d16: in getOperandLatency()
4524 case ARM::VLD2d32: in getOperandLatency()
4525 case ARM::VLD2q8Pseudo: in getOperandLatency()
4526 case ARM::VLD2q16Pseudo: in getOperandLatency()
4527 case ARM::VLD2q32Pseudo: in getOperandLatency()
4528 case ARM::VLD2d8wb_fixed: in getOperandLatency()
4529 case ARM::VLD2d16wb_fixed: in getOperandLatency()
4530 case ARM::VLD2d32wb_fixed: in getOperandLatency()
4531 case ARM::VLD2q8PseudoWB_fixed: in getOperandLatency()
4532 case ARM::VLD2q16PseudoWB_fixed: in getOperandLatency()
4533 case ARM::VLD2q32PseudoWB_fixed: in getOperandLatency()
4534 case ARM::VLD2d8wb_register: in getOperandLatency()
4535 case ARM::VLD2d16wb_register: in getOperandLatency()
4536 case ARM::VLD2d32wb_register: in getOperandLatency()
4537 case ARM::VLD2q8PseudoWB_register: in getOperandLatency()
4538 case ARM::VLD2q16PseudoWB_register: in getOperandLatency()
4539 case ARM::VLD2q32PseudoWB_register: in getOperandLatency()
4540 case ARM::VLD3d8Pseudo: in getOperandLatency()
4541 case ARM::VLD3d16Pseudo: in getOperandLatency()
4542 case ARM::VLD3d32Pseudo: in getOperandLatency()
4543 case ARM::VLD1d8TPseudo: in getOperandLatency()
4544 case ARM::VLD1d16TPseudo: in getOperandLatency()
4545 case ARM::VLD1d32TPseudo: in getOperandLatency()
4546 case ARM::VLD1d64TPseudo: in getOperandLatency()
4547 case ARM::VLD1d64TPseudoWB_fixed: in getOperandLatency()
4548 case ARM::VLD1d64TPseudoWB_register: in getOperandLatency()
4549 case ARM::VLD3d8Pseudo_UPD: in getOperandLatency()
4550 case ARM::VLD3d16Pseudo_UPD: in getOperandLatency()
4551 case ARM::VLD3d32Pseudo_UPD: in getOperandLatency()
4552 case ARM::VLD3q8Pseudo_UPD: in getOperandLatency()
4553 case ARM::VLD3q16Pseudo_UPD: in getOperandLatency()
4554 case ARM::VLD3q32Pseudo_UPD: in getOperandLatency()
4555 case ARM::VLD3q8oddPseudo: in getOperandLatency()
4556 case ARM::VLD3q16oddPseudo: in getOperandLatency()
4557 case ARM::VLD3q32oddPseudo: in getOperandLatency()
4558 case ARM::VLD3q8oddPseudo_UPD: in getOperandLatency()
4559 case ARM::VLD3q16oddPseudo_UPD: in getOperandLatency()
4560 case ARM::VLD3q32oddPseudo_UPD: in getOperandLatency()
4561 case ARM::VLD4d8Pseudo: in getOperandLatency()
4562 case ARM::VLD4d16Pseudo: in getOperandLatency()
4563 case ARM::VLD4d32Pseudo: in getOperandLatency()
4564 case ARM::VLD1d8QPseudo: in getOperandLatency()
4565 case ARM::VLD1d16QPseudo: in getOperandLatency()
4566 case ARM::VLD1d32QPseudo: in getOperandLatency()
4567 case ARM::VLD1d64QPseudo: in getOperandLatency()
4568 case ARM::VLD1d64QPseudoWB_fixed: in getOperandLatency()
4569 case ARM::VLD1d64QPseudoWB_register: in getOperandLatency()
4570 case ARM::VLD1q8HighQPseudo: in getOperandLatency()
4571 case ARM::VLD1q8LowQPseudo_UPD: in getOperandLatency()
4572 case ARM::VLD1q8HighTPseudo: in getOperandLatency()
4573 case ARM::VLD1q8LowTPseudo_UPD: in getOperandLatency()
4574 case ARM::VLD1q16HighQPseudo: in getOperandLatency()
4575 case ARM::VLD1q16LowQPseudo_UPD: in getOperandLatency()
4576 case ARM::VLD1q16HighTPseudo: in getOperandLatency()
4577 case ARM::VLD1q16LowTPseudo_UPD: in getOperandLatency()
4578 case ARM::VLD1q32HighQPseudo: in getOperandLatency()
4579 case ARM::VLD1q32LowQPseudo_UPD: in getOperandLatency()
4580 case ARM::VLD1q32HighTPseudo: in getOperandLatency()
4581 case ARM::VLD1q32LowTPseudo_UPD: in getOperandLatency()
4582 case ARM::VLD1q64HighQPseudo: in getOperandLatency()
4583 case ARM::VLD1q64LowQPseudo_UPD: in getOperandLatency()
4584 case ARM::VLD1q64HighTPseudo: in getOperandLatency()
4585 case ARM::VLD1q64LowTPseudo_UPD: in getOperandLatency()
4586 case ARM::VLD4d8Pseudo_UPD: in getOperandLatency()
4587 case ARM::VLD4d16Pseudo_UPD: in getOperandLatency()
4588 case ARM::VLD4d32Pseudo_UPD: in getOperandLatency()
4589 case ARM::VLD4q8Pseudo_UPD: in getOperandLatency()
4590 case ARM::VLD4q16Pseudo_UPD: in getOperandLatency()
4591 case ARM::VLD4q32Pseudo_UPD: in getOperandLatency()
4592 case ARM::VLD4q8oddPseudo: in getOperandLatency()
4593 case ARM::VLD4q16oddPseudo: in getOperandLatency()
4594 case ARM::VLD4q32oddPseudo: in getOperandLatency()
4595 case ARM::VLD4q8oddPseudo_UPD: in getOperandLatency()
4596 case ARM::VLD4q16oddPseudo_UPD: in getOperandLatency()
4597 case ARM::VLD4q32oddPseudo_UPD: in getOperandLatency()
4598 case ARM::VLD1DUPq8: in getOperandLatency()
4599 case ARM::VLD1DUPq16: in getOperandLatency()
4600 case ARM::VLD1DUPq32: in getOperandLatency()
4601 case ARM::VLD1DUPq8wb_fixed: in getOperandLatency()
4602 case ARM::VLD1DUPq16wb_fixed: in getOperandLatency()
4603 case ARM::VLD1DUPq32wb_fixed: in getOperandLatency()
4604 case ARM::VLD1DUPq8wb_register: in getOperandLatency()
4605 case ARM::VLD1DUPq16wb_register: in getOperandLatency()
4606 case ARM::VLD1DUPq32wb_register: in getOperandLatency()
4607 case ARM::VLD2DUPd8: in getOperandLatency()
4608 case ARM::VLD2DUPd16: in getOperandLatency()
4609 case ARM::VLD2DUPd32: in getOperandLatency()
4610 case ARM::VLD2DUPd8wb_fixed: in getOperandLatency()
4611 case ARM::VLD2DUPd16wb_fixed: in getOperandLatency()
4612 case ARM::VLD2DUPd32wb_fixed: in getOperandLatency()
4613 case ARM::VLD2DUPd8wb_register: in getOperandLatency()
4614 case ARM::VLD2DUPd16wb_register: in getOperandLatency()
4615 case ARM::VLD2DUPd32wb_register: in getOperandLatency()
4616 case ARM::VLD2DUPq8EvenPseudo: in getOperandLatency()
4617 case ARM::VLD2DUPq8OddPseudo: in getOperandLatency()
4618 case ARM::VLD2DUPq16EvenPseudo: in getOperandLatency()
4619 case ARM::VLD2DUPq16OddPseudo: in getOperandLatency()
4620 case ARM::VLD2DUPq32EvenPseudo: in getOperandLatency()
4621 case ARM::VLD2DUPq32OddPseudo: in getOperandLatency()
4622 case ARM::VLD3DUPq8EvenPseudo: in getOperandLatency()
4623 case ARM::VLD3DUPq8OddPseudo: in getOperandLatency()
4624 case ARM::VLD3DUPq16EvenPseudo: in getOperandLatency()
4625 case ARM::VLD3DUPq16OddPseudo: in getOperandLatency()
4626 case ARM::VLD3DUPq32EvenPseudo: in getOperandLatency()
4627 case ARM::VLD3DUPq32OddPseudo: in getOperandLatency()
4628 case ARM::VLD4DUPd8Pseudo: in getOperandLatency()
4629 case ARM::VLD4DUPd16Pseudo: in getOperandLatency()
4630 case ARM::VLD4DUPd32Pseudo: in getOperandLatency()
4631 case ARM::VLD4DUPd8Pseudo_UPD: in getOperandLatency()
4632 case ARM::VLD4DUPd16Pseudo_UPD: in getOperandLatency()
4633 case ARM::VLD4DUPd32Pseudo_UPD: in getOperandLatency()
4634 case ARM::VLD4DUPq8EvenPseudo: in getOperandLatency()
4635 case ARM::VLD4DUPq8OddPseudo: in getOperandLatency()
4636 case ARM::VLD4DUPq16EvenPseudo: in getOperandLatency()
4637 case ARM::VLD4DUPq16OddPseudo: in getOperandLatency()
4638 case ARM::VLD4DUPq32EvenPseudo: in getOperandLatency()
4639 case ARM::VLD4DUPq32OddPseudo: in getOperandLatency()
4640 case ARM::VLD1LNq8Pseudo: in getOperandLatency()
4641 case ARM::VLD1LNq16Pseudo: in getOperandLatency()
4642 case ARM::VLD1LNq32Pseudo: in getOperandLatency()
4643 case ARM::VLD1LNq8Pseudo_UPD: in getOperandLatency()
4644 case ARM::VLD1LNq16Pseudo_UPD: in getOperandLatency()
4645 case ARM::VLD1LNq32Pseudo_UPD: in getOperandLatency()
4646 case ARM::VLD2LNd8Pseudo: in getOperandLatency()
4647 case ARM::VLD2LNd16Pseudo: in getOperandLatency()
4648 case ARM::VLD2LNd32Pseudo: in getOperandLatency()
4649 case ARM::VLD2LNq16Pseudo: in getOperandLatency()
4650 case ARM::VLD2LNq32Pseudo: in getOperandLatency()
4651 case ARM::VLD2LNd8Pseudo_UPD: in getOperandLatency()
4652 case ARM::VLD2LNd16Pseudo_UPD: in getOperandLatency()
4653 case ARM::VLD2LNd32Pseudo_UPD: in getOperandLatency()
4654 case ARM::VLD2LNq16Pseudo_UPD: in getOperandLatency()
4655 case ARM::VLD2LNq32Pseudo_UPD: in getOperandLatency()
4656 case ARM::VLD4LNd8Pseudo: in getOperandLatency()
4657 case ARM::VLD4LNd16Pseudo: in getOperandLatency()
4658 case ARM::VLD4LNd32Pseudo: in getOperandLatency()
4659 case ARM::VLD4LNq16Pseudo: in getOperandLatency()
4660 case ARM::VLD4LNq32Pseudo: in getOperandLatency()
4661 case ARM::VLD4LNd8Pseudo_UPD: in getOperandLatency()
4662 case ARM::VLD4LNd16Pseudo_UPD: in getOperandLatency()
4663 case ARM::VLD4LNd32Pseudo_UPD: in getOperandLatency()
4664 case ARM::VLD4LNq16Pseudo_UPD: in getOperandLatency()
4665 case ARM::VLD4LNq32Pseudo_UPD: in getOperandLatency()
4685 if (MCID.isCall() || (MCID.hasImplicitDefOfPhysReg(ARM::CPSR) && in getPredicationCost()
4708 if (I->getOpcode() != ARM::t2IT) in getInstrLatency()
4715 if (PredCost && (MCID.isCall() || (MCID.hasImplicitDefOfPhysReg(ARM::CPSR) && in getInstrLatency()
4757 case ARM::VLDMQIA: in getInstrLatency()
4758 case ARM::VSTMQIA: in getInstrLatency()
4806 if (MI.getOpcode() == ARM::tMOVr && !Subtarget.hasV6Ops()) { in verifyInstruction()
4808 if (!ARM::hGPRRegClass.contains(MI.getOperand(0).getReg()) && in verifyInstruction()
4809 !ARM::hGPRRegClass.contains(MI.getOperand(1).getReg())) { in verifyInstruction()
4814 if (MI.getOpcode() == ARM::tPUSH || in verifyInstruction()
4815 MI.getOpcode() == ARM::tPOP || in verifyInstruction()
4816 MI.getOpcode() == ARM::tPOP_RET) { in verifyInstruction()
4822 if (Reg < ARM::R0 || Reg > ARM::R7) { in verifyInstruction()
4823 if (!(MI.getOpcode() == ARM::tPUSH && Reg == ARM::LR) && in verifyInstruction()
4824 !(MI.getOpcode() == ARM::tPOP_RET && Reg == ARM::PC)) { in verifyInstruction()
4831 if (MI.getOpcode() == ARM::MVE_VMOV_q_rr) { in verifyInstruction()
4921 if (MI.getOpcode() == ARM::VMOVD && !isPredicated(MI)) in getExecutionDomain()
4927 (MI.getOpcode() == ARM::VMOVRS || MI.getOpcode() == ARM::VMOVSR || in getExecutionDomain()
4928 MI.getOpcode() == ARM::VMOVS)) in getExecutionDomain()
4950 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
4953 if (DReg != ARM::NoRegister) in getCorrespondingDRegAndLane()
4957 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
4990 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1); in getImplicitSPRUseForDPRUse()
5015 case ARM::VMOVD: in setExecutionDomain()
5033 MI.setDesc(get(ARM::VORRd)); in setExecutionDomain()
5039 case ARM::VMOVRS: in setExecutionDomain()
5056 MI.setDesc(get(ARM::VGETLNi32)); in setExecutionDomain()
5066 case ARM::VMOVSR: { in setExecutionDomain()
5086 MI.setDesc(get(ARM::VSETLNi32)); in setExecutionDomain()
5100 case ARM::VMOVS: { in setExecutionDomain()
5122 MI.setDesc(get(ARM::VDUPLN32d)); in setExecutionDomain()
5150 NewMIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::VEXTd32), in setExecutionDomain()
5169 MI.setDesc(get(ARM::VEXTd32)); in setExecutionDomain()
5230 case ARM::VLDRS: in getPartialRegUpdateClearance()
5231 case ARM::FCONSTS: in getPartialRegUpdateClearance()
5232 case ARM::VMOVSR: in getPartialRegUpdateClearance()
5233 case ARM::VMOVv8i8: in getPartialRegUpdateClearance()
5234 case ARM::VMOVv4i16: in getPartialRegUpdateClearance()
5235 case ARM::VMOVv2i32: in getPartialRegUpdateClearance()
5236 case ARM::VMOVv2f32: in getPartialRegUpdateClearance()
5237 case ARM::VMOVv1i64: in getPartialRegUpdateClearance()
5242 case ARM::VLD1LNd32: in getPartialRegUpdateClearance()
5259 } else if (ARM::SPRRegClass.contains(Reg)) { in getPartialRegUpdateClearance()
5261 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0, in getPartialRegUpdateClearance()
5262 &ARM::DPRRegClass); in getPartialRegUpdateClearance()
5286 if (ARM::SPRRegClass.contains(Reg)) { in breakPartialRegDependency()
5287 DReg = ARM::D0 + (Reg - ARM::S0) / 2; in breakPartialRegDependency()
5291 assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps"); in breakPartialRegDependency()
5302 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::FCONSTD), DReg) in breakPartialRegDependency()
5309 return Subtarget.getFeatureBits()[ARM::HasV6KOps]; in hasNOP()
5333 case ARM::VMOVDRR: in getRegSequenceLikeInputs()
5342 MOReg->getSubReg(), ARM::ssub_0)); in getRegSequenceLikeInputs()
5347 MOReg->getSubReg(), ARM::ssub_1)); in getRegSequenceLikeInputs()
5360 case ARM::VMOVRRD: in getExtractSubregLikeInputs()
5370 InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1; in getExtractSubregLikeInputs()
5383 case ARM::VSETLNi32: in getInsertSubregLikeInputs()
5384 case ARM::MVE_VMOV_to_lane_32: in getInsertSubregLikeInputs()
5397 InsertedReg.SubIdx = ARM::ssub_0 + MOIndex.getImm(); in getInsertSubregLikeInputs()
5445 if (Opcode == ARM::SUBri) in isAddImmediate()
5447 else if (Opcode != ARM::ADDri) in isAddImmediate()
5478 if (CmpMI->modifiesRegister(ARM::CPSR, TRI)) in findCMPToFoldIntoCBZ()
5480 if (CmpMI->readsRegister(ARM::CPSR, TRI)) in findCMPToFoldIntoCBZ()
5486 if (CmpMI->getOpcode() != ARM::tCMPi8 && CmpMI->getOpcode() != ARM::t2CMPri) in findCMPToFoldIntoCBZ()
5703 for (unsigned Reg : ARM::rGPRRegClass) { in findRegisterToSaveLRTo()
5705 Reg != ARM::LR && // LR is not reserved, but don't use it. in findRegisterToSaveLRTo()
5706 Reg != ARM::R12 && // R12 is not guaranteed to be preserved. in findRegisterToSaveLRTo()
5727 if (MI.modifiesRegister(ARM::LR, &TRI)) in isLRAvailable()
5732 if (Opcode == ARM::BX_RET || Opcode == ARM::MOVPCLR || in isLRAvailable()
5733 Opcode == ARM::SUBS_PC_LR || Opcode == ARM::tBX_RET || in isLRAvailable()
5734 Opcode == ARM::tBXNS_RET) { in isLRAvailable()
5740 if (MI.readsRegister(ARM::LR, &TRI)) in isLRAvailable()
5783 return (!LRU.available(ARM::R12) || !LRU.available(ARM::CPSR)); in getOutliningCandidateInfo()
5820 } else if (LastInstrOpcode == ARM::BL || LastInstrOpcode == ARM::BLX || in getOutliningCandidateInfo()
5821 LastInstrOpcode == ARM::BLX_noip || LastInstrOpcode == ARM::tBL || in getOutliningCandidateInfo()
5822 LastInstrOpcode == ARM::tBLXr || in getOutliningCandidateInfo()
5823 LastInstrOpcode == ARM::tBLXr_noip || in getOutliningCandidateInfo()
5824 LastInstrOpcode == ARM::tBLXi) { in getOutliningCandidateInfo()
5844 : C.LRU.available(ARM::LR); in getOutliningCandidateInfo()
5863 else if (C.UsedInSequence.available(ARM::SP)) { in getOutliningCandidateInfo()
5912 int SPIdx = MI->findRegisterUseOperandIdx(ARM::SP); in checkAndUpdateStackOffset()
6047 bool R12AvailableInBlock = LRU.available(ARM::R12); in isMBBSafeToOutlineFrom()
6048 bool CPSRAvailableInBlock = LRU.available(ARM::CPSR); in isMBBSafeToOutlineFrom()
6060 if (R12AvailableInBlock && !LRU.available(ARM::R12)) in isMBBSafeToOutlineFrom()
6062 if (CPSRAvailableInBlock && !LRU.available(ARM::CPSR)) in isMBBSafeToOutlineFrom()
6075 : LRU.available(ARM::LR); in isMBBSafeToOutlineFrom()
6104 if (Opc == ARM::tPICADD || Opc == ARM::PICADD || Opc == ARM::PICSTR || in getOutliningType()
6105 Opc == ARM::PICSTRB || Opc == ARM::PICSTRH || Opc == ARM::PICLDR || in getOutliningType()
6106 Opc == ARM::PICLDRB || Opc == ARM::PICLDRH || Opc == ARM::PICLDRSB || in getOutliningType()
6107 Opc == ARM::PICLDRSH || Opc == ARM::t2LDRpci_pic || in getOutliningType()
6108 Opc == ARM::t2MOVi16_ga_pcrel || Opc == ARM::t2MOVTi16_ga_pcrel || in getOutliningType()
6109 Opc == ARM::t2MOV_ga_pcrel) in getOutliningType()
6113 if (Opc == ARM::t2BF_LabelPseudo || Opc == ARM::t2DoLoopStart || in getOutliningType()
6114 Opc == ARM::t2DoLoopStartTP || Opc == ARM::t2WhileLoopStart || in getOutliningType()
6115 Opc == ARM::t2WhileLoopStartLR || Opc == ARM::t2WhileLoopStartTP || in getOutliningType()
6116 Opc == ARM::t2LoopDec || Opc == ARM::t2LoopEnd || in getOutliningType()
6117 Opc == ARM::t2LoopEndDec) in getOutliningType()
6147 if (MI.readsRegister(ARM::LR, TRI) || MI.readsRegister(ARM::PC, TRI)) in getOutliningType()
6173 if (Opc == ARM::BL || Opc == ARM::tBL || Opc == ARM::BLX || in getOutliningType()
6174 Opc == ARM::BLX_noip || Opc == ARM::tBLXr || Opc == ARM::tBLXr_noip || in getOutliningType()
6175 Opc == ARM::tBLXi) in getOutliningType()
6204 if (MI.modifiesRegister(ARM::LR, TRI) || MI.modifiesRegister(ARM::PC, TRI)) in getOutliningType()
6208 if (MI.modifiesRegister(ARM::SP, TRI) || MI.readsRegister(ARM::SP, TRI)) { in getOutliningType()
6226 if (MI.modifiesRegister(ARM::SP, TRI)) in getOutliningType()
6240 if (MI.readsRegister(ARM::ITSTATE, TRI) || in getOutliningType()
6241 MI.modifiesRegister(ARM::ITSTATE, TRI)) in getOutliningType()
6259 unsigned Opc = Subtarget.isThumb() ? ARM::t2STR_PRE : ARM::STR_PRE_IMM; in saveLROnStack()
6261 BuildMI(MBB, It, DebugLoc(), get(Opc), ARM::SP) in saveLROnStack()
6262 .addReg(ARM::LR, RegState::Kill) in saveLROnStack()
6263 .addReg(ARM::SP) in saveLROnStack()
6272 unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true); in emitCFIForLRSaveOnStack()
6277 BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION)) in emitCFIForLRSaveOnStack()
6285 BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION)) in emitCFIForLRSaveOnStack()
6295 unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true); in emitCFIForLRSaveToReg()
6300 BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION)) in emitCFIForLRSaveToReg()
6307 unsigned Opc = Subtarget.isThumb() ? ARM::t2LDR_POST : ARM::LDR_POST_IMM; in restoreLRFromStack()
6308 MachineInstrBuilder MIB = BuildMI(MBB, It, DebugLoc(), get(Opc), ARM::LR) in restoreLRFromStack()
6309 .addReg(ARM::SP, RegState::Define) in restoreLRFromStack()
6310 .addReg(ARM::SP); in restoreLRFromStack()
6321 unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true); in emitCFIForLRRestoreFromStack()
6324 BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION)) in emitCFIForLRRestoreFromStack()
6331 BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION)) in emitCFIForLRRestoreFromStack()
6340 unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true); in emitCFIForLRRestoreFromReg()
6344 BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION)) in emitCFIForLRRestoreFromReg()
6359 ? isThumb ? ARM::tTAILJMPr : ARM::TAILJMPr in buildOutlinedFrame()
6360 : isThumb ? Subtarget.isTargetMachO() ? ARM::tTAILJMPd in buildOutlinedFrame()
6361 : ARM::tTAILJMPdND in buildOutlinedFrame()
6362 : ARM::TAILJMPd; in buildOutlinedFrame()
6385 if (!MBB.isLiveIn(ARM::LR)) in buildOutlinedFrame()
6386 MBB.addLiveIn(ARM::LR); in buildOutlinedFrame()
6435 ? Subtarget.isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND in insertOutlinedCall()
6436 : ARM::TAILJMPd; in insertOutlinedCall()
6446 Opc = isThumb ? ARM::tBL : ARM::BL; in insertOutlinedCall()
6466 copyPhysReg(MBB, It, DebugLoc(), Reg, ARM::LR, true); in insertOutlinedCall()
6470 copyPhysReg(MBB, It, DebugLoc(), ARM::LR, Reg, true); in insertOutlinedCall()
6477 if (!MBB.isLiveIn(ARM::LR)) in insertOutlinedCall()
6478 MBB.addLiveIn(ARM::LR); in insertOutlinedCall()
6505 return (MF.getSubtarget<ARMSubtarget>().hardenSlsBlr()) ? ARM::BLX_noip in getBLXOpcode()
6506 : ARM::BLX; in getBLXOpcode()
6510 return (MF.getSubtarget<ARMSubtarget>().hardenSlsBlr()) ? ARM::tBLXr_noip in gettBLXrOpcode()
6511 : ARM::tBLXr; in gettBLXrOpcode()
6515 return (MF.getSubtarget<ARMSubtarget>().hardenSlsBlr()) ? ARM::BLX_pred_noip in getBLXpredOpcode()
6516 : ARM::BLX_pred; in getBLXpredOpcode()