Lines Matching refs:ARM
117 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32); in SelectCMOVPred()
515 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasNoVMLxHazardUse()
1597 Opcode = ARM::LDR_PRE_IMM; in tryARMIndexedLoad()
1601 Opcode = ARM::LDR_POST_IMM; in tryARMIndexedLoad()
1605 Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG; in tryARMIndexedLoad()
1612 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST) in tryARMIndexedLoad()
1613 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST); in tryARMIndexedLoad()
1618 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST; in tryARMIndexedLoad()
1624 Opcode = ARM::LDRB_PRE_IMM; in tryARMIndexedLoad()
1628 Opcode = ARM::LDRB_POST_IMM; in tryARMIndexedLoad()
1631 Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG; in tryARMIndexedLoad()
1637 if (Opcode == ARM::LDR_PRE_IMM || Opcode == ARM::LDRB_PRE_IMM) { in tryARMIndexedLoad()
1683 SDNode *New = CurDAG->getMachineNode(ARM::tLDR_postidx, SDLoc(N), MVT::i32, in tryT1IndexedLoad()
1705 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST; in tryT2IndexedLoad()
1709 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST; in tryT2IndexedLoad()
1711 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST; in tryT2IndexedLoad()
1716 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST; in tryT2IndexedLoad()
1718 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST; in tryT2IndexedLoad()
1794 Opcode = isPre ? ARM::MVE_VLDRHS32_pre : ARM::MVE_VLDRHS32_post; in tryMVEIndexedLoad()
1796 Opcode = isPre ? ARM::MVE_VLDRHU32_pre : ARM::MVE_VLDRHU32_post; in tryMVEIndexedLoad()
1800 Opcode = isPre ? ARM::MVE_VLDRBS16_pre : ARM::MVE_VLDRBS16_post; in tryMVEIndexedLoad()
1802 Opcode = isPre ? ARM::MVE_VLDRBU16_pre : ARM::MVE_VLDRBU16_post; in tryMVEIndexedLoad()
1806 Opcode = isPre ? ARM::MVE_VLDRBS32_pre : ARM::MVE_VLDRBS32_post; in tryMVEIndexedLoad()
1808 Opcode = isPre ? ARM::MVE_VLDRBU32_pre : ARM::MVE_VLDRBU32_post; in tryMVEIndexedLoad()
1813 Opcode = isPre ? ARM::MVE_VLDRWU32_pre : ARM::MVE_VLDRWU32_post; in tryMVEIndexedLoad()
1818 Opcode = isPre ? ARM::MVE_VLDRHU16_pre : ARM::MVE_VLDRHU16_post; in tryMVEIndexedLoad()
1821 Opcode = isPre ? ARM::MVE_VLDRBU8_pre : ARM::MVE_VLDRBU8_post; in tryMVEIndexedLoad()
1842 CurDAG->getTargetConstant(ARM::GPRPairRegClassID, dl, MVT::i32); in createGPRPairNode()
1843 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, dl, MVT::i32); in createGPRPairNode()
1844 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32); in createGPRPairNode()
1853 CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, dl, MVT::i32); in createSRegPairNode()
1854 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32); in createSRegPairNode()
1855 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32); in createSRegPairNode()
1863 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl, in createDRegPairNode()
1865 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32); in createDRegPairNode()
1866 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32); in createDRegPairNode()
1874 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQRegPairNode()
1876 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32); in createQRegPairNode()
1877 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32); in createQRegPairNode()
1887 CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, dl, MVT::i32); in createQuadSRegsNode()
1888 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32); in createQuadSRegsNode()
1889 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32); in createQuadSRegsNode()
1890 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, dl, MVT::i32); in createQuadSRegsNode()
1891 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, dl, MVT::i32); in createQuadSRegsNode()
1901 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQuadDRegsNode()
1903 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32); in createQuadDRegsNode()
1904 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32); in createQuadDRegsNode()
1905 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, dl, MVT::i32); in createQuadDRegsNode()
1906 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, dl, MVT::i32); in createQuadDRegsNode()
1916 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl, in createQuadQRegsNode()
1918 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32); in createQuadQRegsNode()
1919 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32); in createQuadQRegsNode()
1920 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, dl, MVT::i32); in createQuadQRegsNode()
1921 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, dl, MVT::i32); in createQuadQRegsNode()
1953 case ARM::VLD1d8wb_fixed : return true; in isVLDfixed()
1954 case ARM::VLD1d16wb_fixed : return true; in isVLDfixed()
1955 case ARM::VLD1d64Qwb_fixed : return true; in isVLDfixed()
1956 case ARM::VLD1d32wb_fixed : return true; in isVLDfixed()
1957 case ARM::VLD1d64wb_fixed : return true; in isVLDfixed()
1958 case ARM::VLD1d8TPseudoWB_fixed : return true; in isVLDfixed()
1959 case ARM::VLD1d16TPseudoWB_fixed : return true; in isVLDfixed()
1960 case ARM::VLD1d32TPseudoWB_fixed : return true; in isVLDfixed()
1961 case ARM::VLD1d64TPseudoWB_fixed : return true; in isVLDfixed()
1962 case ARM::VLD1d8QPseudoWB_fixed : return true; in isVLDfixed()
1963 case ARM::VLD1d16QPseudoWB_fixed : return true; in isVLDfixed()
1964 case ARM::VLD1d32QPseudoWB_fixed : return true; in isVLDfixed()
1965 case ARM::VLD1d64QPseudoWB_fixed : return true; in isVLDfixed()
1966 case ARM::VLD1q8wb_fixed : return true; in isVLDfixed()
1967 case ARM::VLD1q16wb_fixed : return true; in isVLDfixed()
1968 case ARM::VLD1q32wb_fixed : return true; in isVLDfixed()
1969 case ARM::VLD1q64wb_fixed : return true; in isVLDfixed()
1970 case ARM::VLD1DUPd8wb_fixed : return true; in isVLDfixed()
1971 case ARM::VLD1DUPd16wb_fixed : return true; in isVLDfixed()
1972 case ARM::VLD1DUPd32wb_fixed : return true; in isVLDfixed()
1973 case ARM::VLD1DUPq8wb_fixed : return true; in isVLDfixed()
1974 case ARM::VLD1DUPq16wb_fixed : return true; in isVLDfixed()
1975 case ARM::VLD1DUPq32wb_fixed : return true; in isVLDfixed()
1976 case ARM::VLD2d8wb_fixed : return true; in isVLDfixed()
1977 case ARM::VLD2d16wb_fixed : return true; in isVLDfixed()
1978 case ARM::VLD2d32wb_fixed : return true; in isVLDfixed()
1979 case ARM::VLD2q8PseudoWB_fixed : return true; in isVLDfixed()
1980 case ARM::VLD2q16PseudoWB_fixed : return true; in isVLDfixed()
1981 case ARM::VLD2q32PseudoWB_fixed : return true; in isVLDfixed()
1982 case ARM::VLD2DUPd8wb_fixed : return true; in isVLDfixed()
1983 case ARM::VLD2DUPd16wb_fixed : return true; in isVLDfixed()
1984 case ARM::VLD2DUPd32wb_fixed : return true; in isVLDfixed()
1985 case ARM::VLD2DUPq8OddPseudoWB_fixed: return true; in isVLDfixed()
1986 case ARM::VLD2DUPq16OddPseudoWB_fixed: return true; in isVLDfixed()
1987 case ARM::VLD2DUPq32OddPseudoWB_fixed: return true; in isVLDfixed()
1995 case ARM::VST1d8wb_fixed : return true; in isVSTfixed()
1996 case ARM::VST1d16wb_fixed : return true; in isVSTfixed()
1997 case ARM::VST1d32wb_fixed : return true; in isVSTfixed()
1998 case ARM::VST1d64wb_fixed : return true; in isVSTfixed()
1999 case ARM::VST1q8wb_fixed : return true; in isVSTfixed()
2000 case ARM::VST1q16wb_fixed : return true; in isVSTfixed()
2001 case ARM::VST1q32wb_fixed : return true; in isVSTfixed()
2002 case ARM::VST1q64wb_fixed : return true; in isVSTfixed()
2003 case ARM::VST1d8TPseudoWB_fixed : return true; in isVSTfixed()
2004 case ARM::VST1d16TPseudoWB_fixed : return true; in isVSTfixed()
2005 case ARM::VST1d32TPseudoWB_fixed : return true; in isVSTfixed()
2006 case ARM::VST1d64TPseudoWB_fixed : return true; in isVSTfixed()
2007 case ARM::VST1d8QPseudoWB_fixed : return true; in isVSTfixed()
2008 case ARM::VST1d16QPseudoWB_fixed : return true; in isVSTfixed()
2009 case ARM::VST1d32QPseudoWB_fixed : return true; in isVSTfixed()
2010 case ARM::VST1d64QPseudoWB_fixed : return true; in isVSTfixed()
2011 case ARM::VST2d8wb_fixed : return true; in isVSTfixed()
2012 case ARM::VST2d16wb_fixed : return true; in isVSTfixed()
2013 case ARM::VST2d32wb_fixed : return true; in isVSTfixed()
2014 case ARM::VST2q8PseudoWB_fixed : return true; in isVSTfixed()
2015 case ARM::VST2q16PseudoWB_fixed : return true; in isVSTfixed()
2016 case ARM::VST2q32PseudoWB_fixed : return true; in isVSTfixed()
2027 case ARM::VLD1d8wb_fixed: return ARM::VLD1d8wb_register; in getVLDSTRegisterUpdateOpcode()
2028 case ARM::VLD1d16wb_fixed: return ARM::VLD1d16wb_register; in getVLDSTRegisterUpdateOpcode()
2029 case ARM::VLD1d32wb_fixed: return ARM::VLD1d32wb_register; in getVLDSTRegisterUpdateOpcode()
2030 case ARM::VLD1d64wb_fixed: return ARM::VLD1d64wb_register; in getVLDSTRegisterUpdateOpcode()
2031 case ARM::VLD1q8wb_fixed: return ARM::VLD1q8wb_register; in getVLDSTRegisterUpdateOpcode()
2032 case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register; in getVLDSTRegisterUpdateOpcode()
2033 case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register; in getVLDSTRegisterUpdateOpcode()
2034 case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register; in getVLDSTRegisterUpdateOpcode()
2035 case ARM::VLD1d64Twb_fixed: return ARM::VLD1d64Twb_register; in getVLDSTRegisterUpdateOpcode()
2036 case ARM::VLD1d64Qwb_fixed: return ARM::VLD1d64Qwb_register; in getVLDSTRegisterUpdateOpcode()
2037 case ARM::VLD1d8TPseudoWB_fixed: return ARM::VLD1d8TPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2038 case ARM::VLD1d16TPseudoWB_fixed: return ARM::VLD1d16TPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2039 case ARM::VLD1d32TPseudoWB_fixed: return ARM::VLD1d32TPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2040 case ARM::VLD1d64TPseudoWB_fixed: return ARM::VLD1d64TPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2041 case ARM::VLD1d8QPseudoWB_fixed: return ARM::VLD1d8QPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2042 case ARM::VLD1d16QPseudoWB_fixed: return ARM::VLD1d16QPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2043 case ARM::VLD1d32QPseudoWB_fixed: return ARM::VLD1d32QPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2044 case ARM::VLD1d64QPseudoWB_fixed: return ARM::VLD1d64QPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2045 case ARM::VLD1DUPd8wb_fixed : return ARM::VLD1DUPd8wb_register; in getVLDSTRegisterUpdateOpcode()
2046 case ARM::VLD1DUPd16wb_fixed : return ARM::VLD1DUPd16wb_register; in getVLDSTRegisterUpdateOpcode()
2047 case ARM::VLD1DUPd32wb_fixed : return ARM::VLD1DUPd32wb_register; in getVLDSTRegisterUpdateOpcode()
2048 case ARM::VLD1DUPq8wb_fixed : return ARM::VLD1DUPq8wb_register; in getVLDSTRegisterUpdateOpcode()
2049 case ARM::VLD1DUPq16wb_fixed : return ARM::VLD1DUPq16wb_register; in getVLDSTRegisterUpdateOpcode()
2050 case ARM::VLD1DUPq32wb_fixed : return ARM::VLD1DUPq32wb_register; in getVLDSTRegisterUpdateOpcode()
2051 case ARM::VLD2DUPq8OddPseudoWB_fixed: return ARM::VLD2DUPq8OddPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2052 case ARM::VLD2DUPq16OddPseudoWB_fixed: return ARM::VLD2DUPq16OddPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2053 case ARM::VLD2DUPq32OddPseudoWB_fixed: return ARM::VLD2DUPq32OddPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2055 case ARM::VST1d8wb_fixed: return ARM::VST1d8wb_register; in getVLDSTRegisterUpdateOpcode()
2056 case ARM::VST1d16wb_fixed: return ARM::VST1d16wb_register; in getVLDSTRegisterUpdateOpcode()
2057 case ARM::VST1d32wb_fixed: return ARM::VST1d32wb_register; in getVLDSTRegisterUpdateOpcode()
2058 case ARM::VST1d64wb_fixed: return ARM::VST1d64wb_register; in getVLDSTRegisterUpdateOpcode()
2059 case ARM::VST1q8wb_fixed: return ARM::VST1q8wb_register; in getVLDSTRegisterUpdateOpcode()
2060 case ARM::VST1q16wb_fixed: return ARM::VST1q16wb_register; in getVLDSTRegisterUpdateOpcode()
2061 case ARM::VST1q32wb_fixed: return ARM::VST1q32wb_register; in getVLDSTRegisterUpdateOpcode()
2062 case ARM::VST1q64wb_fixed: return ARM::VST1q64wb_register; in getVLDSTRegisterUpdateOpcode()
2063 case ARM::VST1d8TPseudoWB_fixed: return ARM::VST1d8TPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2064 case ARM::VST1d16TPseudoWB_fixed: return ARM::VST1d16TPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2065 case ARM::VST1d32TPseudoWB_fixed: return ARM::VST1d32TPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2066 case ARM::VST1d64TPseudoWB_fixed: return ARM::VST1d64TPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2067 case ARM::VST1d8QPseudoWB_fixed: return ARM::VST1d8QPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2068 case ARM::VST1d16QPseudoWB_fixed: return ARM::VST1d16QPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2069 case ARM::VST1d32QPseudoWB_fixed: return ARM::VST1d32QPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2070 case ARM::VST1d64QPseudoWB_fixed: return ARM::VST1d64QPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2072 case ARM::VLD2d8wb_fixed: return ARM::VLD2d8wb_register; in getVLDSTRegisterUpdateOpcode()
2073 case ARM::VLD2d16wb_fixed: return ARM::VLD2d16wb_register; in getVLDSTRegisterUpdateOpcode()
2074 case ARM::VLD2d32wb_fixed: return ARM::VLD2d32wb_register; in getVLDSTRegisterUpdateOpcode()
2075 case ARM::VLD2q8PseudoWB_fixed: return ARM::VLD2q8PseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2076 case ARM::VLD2q16PseudoWB_fixed: return ARM::VLD2q16PseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2077 case ARM::VLD2q32PseudoWB_fixed: return ARM::VLD2q32PseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2079 case ARM::VST2d8wb_fixed: return ARM::VST2d8wb_register; in getVLDSTRegisterUpdateOpcode()
2080 case ARM::VST2d16wb_fixed: return ARM::VST2d16wb_register; in getVLDSTRegisterUpdateOpcode()
2081 case ARM::VST2d32wb_fixed: return ARM::VST2d32wb_register; in getVLDSTRegisterUpdateOpcode()
2082 case ARM::VST2q8PseudoWB_fixed: return ARM::VST2q8PseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2083 case ARM::VST2q16PseudoWB_fixed: return ARM::VST2q16PseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2084 case ARM::VST2q32PseudoWB_fixed: return ARM::VST2q32PseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2086 case ARM::VLD2DUPd8wb_fixed: return ARM::VLD2DUPd8wb_register; in getVLDSTRegisterUpdateOpcode()
2087 case ARM::VLD2DUPd16wb_fixed: return ARM::VLD2DUPd16wb_register; in getVLDSTRegisterUpdateOpcode()
2088 case ARM::VLD2DUPd32wb_fixed: return ARM::VLD2DUPd32wb_register; in getVLDSTRegisterUpdateOpcode()
2230 static_assert(ARM::dsub_7 == ARM::dsub_0 + 7 && in SelectVLD()
2231 ARM::qsub_3 == ARM::qsub_0 + 3, in SelectVLD()
2233 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0); in SelectVLD()
2514 static_assert(ARM::dsub_7 == ARM::dsub_0 + 7 && in SelectVLDSTLane()
2515 ARM::qsub_3 == ARM::qsub_0 + 3, in SelectVLDSTLane()
2517 unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0; in SelectVLDSTLane()
2683 CurDAG->SelectNodeTo(N, ARM::MVE_VSHLC, N->getVTList(), makeArrayRef(Ops)); in SelectMVE_VSHLC()
2825 CurDAG->getTargetExtractSubreg(ARM::qsub_0 + i, Loc, VT, in SelectMVE_VLD()
2924 uint16_t SubRegs[2] = {ARM::gsub_0, ARM::gsub_1}; in SelectCDE_CXxD()
3057 static_assert(ARM::dsub_7 == ARM::dsub_0 + 7, "Unexpected subreg numbering"); in SelectVLDDup()
3058 unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0; in SelectVLDDup()
3119 ARM::ssub_0 + ExtractLane2 / 2, dl, MVT::f32, Val1.getOperand(0)); in tryInsertVectorElt()
3121 ARM::ssub_0 + Lane2 / 2, dl, VT, Ins2.getOperand(0), in tryInsertVectorElt()
3131 ARM::ssub_0 + ExtractLane1 / 2, dl, MVT::f32, Val1.getOperand(0)); in tryInsertVectorElt()
3133 ARM::ssub_0 + ExtractLane2 / 2, dl, MVT::f32, Val2.getOperand(0)); in tryInsertVectorElt()
3135 Inp1 = SDValue(CurDAG->getMachineNode(ARM::VMOVH, dl, MVT::f32, Inp1), 0); in tryInsertVectorElt()
3137 Inp2 = SDValue(CurDAG->getMachineNode(ARM::VMOVH, dl, MVT::f32, Inp2), 0); in tryInsertVectorElt()
3138 SDNode *VINS = CurDAG->getMachineNode(ARM::VINSH, dl, MVT::f32, Inp2, Inp1); in tryInsertVectorElt()
3140 CurDAG->getTargetInsertSubreg(ARM::ssub_0 + Lane2 / 2, dl, MVT::v4f32, in tryInsertVectorElt()
3150 SDNode *VINS = CurDAG->getMachineNode(ARM::VINSH, dl, MVT::f32, Val2, Val1); in tryInsertVectorElt()
3152 CurDAG->getTargetInsertSubreg(ARM::ssub_0 + Lane2 / 2, dl, MVT::v4f32, in tryInsertVectorElt()
3244 Opcode = IsUnsigned ? ARM::MVE_VCVTf16u16_fix : ARM::MVE_VCVTf16s16_fix; in transformFixedFloatingPointConversion()
3246 Opcode = IsUnsigned ? ARM::MVE_VCVTu16f16_fix : ARM::MVE_VCVTs16f16_fix; in transformFixedFloatingPointConversion()
3250 Opcode = IsUnsigned ? ARM::MVE_VCVTf32u32_fix : ARM::MVE_VCVTf32s32_fix; in transformFixedFloatingPointConversion()
3252 Opcode = IsUnsigned ? ARM::MVE_VCVTu32f32_fix : ARM::MVE_VCVTs32f32_fix; in transformFixedFloatingPointConversion()
3289 Opcode = IsUnsigned ? ARM::MVE_VCVTu16f16_fix : ARM::MVE_VCVTs16f16_fix; in tryFP_TO_INT()
3292 Opcode = IsUnsigned ? ARM::MVE_VCVTu32f32_fix : ARM::MVE_VCVTs32f32_fix; in tryFP_TO_INT()
3330 ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX) in tryV6T2BitfieldExtractOp()
3331 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX); in tryV6T2BitfieldExtractOp()
3362 Opc = isSigned ? ARM::t2ASRri : ARM::t2LSRri; in tryV6T2BitfieldExtractOp()
3377 CurDAG->SelectNodeTo(N, ARM::MOVsi, MVT::i32, Ops); in tryV6T2BitfieldExtractOp()
3493 unsigned Opcode = Subtarget->isThumb2() ? ARM::t2ABS : ARM::ABS; in tryABSOp()
3506 Opcode = Subtarget->isThumb() ? ARM::tCMP_SWAP_8 : ARM::CMP_SWAP_8; in SelectCMP_SWAP()
3508 Opcode = Subtarget->isThumb() ? ARM::tCMP_SWAP_16 : ARM::CMP_SWAP_16; in SelectCMP_SWAP()
3510 Opcode = ARM::CMP_SWAP_32; in SelectCMP_SWAP()
3570 Opc = (Opc == ARM::tLSLri) ? ARM::t2LSLri : ARM::t2LSRri; in SelectCMPZ()
3576 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), Src, in SelectCMPZ()
3585 NewN = EmitShift(ARM::tLSLri, X, 31 - Range->first); in SelectCMPZ()
3589 NewN = EmitShift(ARM::tLSRri, X, Range->second); in SelectCMPZ()
3594 NewN = EmitShift(ARM::tLSLri, X, 31 - Range->first); in SelectCMPZ()
3601 NewN = EmitShift(ARM::tLSLri, X, 31 - Range->first); in SelectCMPZ()
3602 NewN = EmitShift(ARM::tLSRri, SDValue(NewN, 0), in SelectCMPZ()
3639 cast<RegisterSDNode>(Ptr.getOperand(1))->getReg() == ARM::SP && in Select()
3642 CurDAG->getRegister(ARM::SP, MVT::i32), in Select()
3648 CurDAG->getMachineNode(ARM::tSTRspi, dl, MVT::Other, Ops); in Select()
3692 ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other, in Select()
3702 ResNode = CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other, in Select()
3733 CurDAG->SelectNodeTo(N, ARM::tADDframe, MVT::i32, TFI, in Select()
3738 ARM::t2ADDri : ARM::ADDri); in Select()
3785 CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops); in Select()
3790 CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops); in Select()
3804 CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops); in Select()
3809 CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops); in Select()
3846 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), in Select()
3849 ReplaceNode(N, CurDAG->getMachineNode(ARM::tBIC, dl, MVT::i32, Ops)); in Select()
3856 CurDAG->getMachineNode(ARM::t2BICrr, dl, MVT::i32, Ops)); in Select()
3871 ? ARM::t2MOVTi16 in Select()
3872 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0); in Select()
3901 unsigned Opc = Subtarget->isThumb() ? ARM::t2UMAAL : ARM::UMAAL; in Select()
3915 N, CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops)); in Select()
3923 Subtarget->hasV6Ops() ? ARM::UMLAL : ARM::UMLALv5, dl, in Select()
3934 N, CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops)); in Select()
3942 Subtarget->hasV6Ops() ? ARM::SMLAL : ARM::SMLALv5, dl, in Select()
3971 unsigned Opc = Subtarget->isThumb2() ? ARM::t2SMMLS : ARM::SMMLS; in Select()
3998 SDNode *New = CurDAG->getMachineNode(ARM::t2WhileLoopSetup, dl, MVT::i32, in Select()
4005 SDNode *New = CurDAG->getMachineNode(ARM::t2WhileLoopStart, dl, MVT::Other, in Select()
4016 unsigned Opc = ARM::t2LoopEnd; in Select()
4038 SDNode *New = CurDAG->getMachineNode(ARM::LOADDUAL, dl, in Select()
4040 SDValue Lo = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32, in Select()
4042 SDValue Hi = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32, in Select()
4069 SDNode *New = CurDAG->getMachineNode(ARM::STOREDUAL, dl, MVT::Other, Ops); in Select()
4080 CurDAG->getMachineNode(ARM::t2LoopDec, dl, in Select()
4100 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc; in Select()
4126 CurDAG->getMachineNode(ARM::t2LoopDec, dl, in Select()
4133 CurDAG->getMachineNode(ARM::t2LoopEnd, dl, MVT::Other, EndArgs); in Select()
4195 Add = CurDAG->getMachineNode(ARM::t2ADDri, dl, MVT::i32, Ops); in Select()
4197 unsigned Opc = (Addend < 1<<3) ? ARM::tADDi3 : ARM::tADDi8; in Select()
4198 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), X, in Select()
4250 case MVT::v8i8: Opc = ARM::VZIPd8; break; in Select()
4252 case MVT::v4i16: Opc = ARM::VZIPd16; break; in Select()
4255 case MVT::v2i32: Opc = ARM::VTRNd32; break; in Select()
4256 case MVT::v16i8: Opc = ARM::VZIPq8; break; in Select()
4258 case MVT::v8i16: Opc = ARM::VZIPq16; break; in Select()
4260 case MVT::v4i32: Opc = ARM::VZIPq32; break; in Select()
4273 case MVT::v8i8: Opc = ARM::VUZPd8; break; in Select()
4275 case MVT::v4i16: Opc = ARM::VUZPd16; break; in Select()
4278 case MVT::v2i32: Opc = ARM::VTRNd32; break; in Select()
4279 case MVT::v16i8: Opc = ARM::VUZPq8; break; in Select()
4281 case MVT::v8i16: Opc = ARM::VUZPq16; break; in Select()
4283 case MVT::v4i32: Opc = ARM::VUZPq32; break; in Select()
4296 case MVT::v8i8: Opc = ARM::VTRNd8; break; in Select()
4298 case MVT::v4i16: Opc = ARM::VTRNd16; break; in Select()
4300 case MVT::v2i32: Opc = ARM::VTRNd32; break; in Select()
4301 case MVT::v16i8: Opc = ARM::VTRNq8; break; in Select()
4303 case MVT::v8i16: Opc = ARM::VTRNq16; break; in Select()
4305 case MVT::v4i32: Opc = ARM::VTRNq32; break; in Select()
4337 static const uint16_t DOpcodes[] = { ARM::VLD1DUPd8, ARM::VLD1DUPd16, in Select()
4338 ARM::VLD1DUPd32 }; in Select()
4339 static const uint16_t QOpcodes[] = { ARM::VLD1DUPq8, ARM::VLD1DUPq16, in Select()
4340 ARM::VLD1DUPq32 }; in Select()
4346 static const uint16_t Opcodes[] = { ARM::VLD2DUPd8, ARM::VLD2DUPd16, in Select()
4347 ARM::VLD2DUPd32 }; in Select()
4353 static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo, in Select()
4354 ARM::VLD3DUPd16Pseudo, in Select()
4355 ARM::VLD3DUPd32Pseudo }; in Select()
4361 static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo, in Select()
4362 ARM::VLD4DUPd16Pseudo, in Select()
4363 ARM::VLD4DUPd32Pseudo }; in Select()
4369 static const uint16_t DOpcodes[] = { ARM::VLD1DUPd8wb_fixed, in Select()
4370 ARM::VLD1DUPd16wb_fixed, in Select()
4371 ARM::VLD1DUPd32wb_fixed }; in Select()
4372 static const uint16_t QOpcodes[] = { ARM::VLD1DUPq8wb_fixed, in Select()
4373 ARM::VLD1DUPq16wb_fixed, in Select()
4374 ARM::VLD1DUPq32wb_fixed }; in Select()
4380 static const uint16_t DOpcodes[] = { ARM::VLD2DUPd8wb_fixed, in Select()
4381 ARM::VLD2DUPd16wb_fixed, in Select()
4382 ARM::VLD2DUPd32wb_fixed, in Select()
4383 ARM::VLD1q64wb_fixed }; in Select()
4384 static const uint16_t QOpcodes0[] = { ARM::VLD2DUPq8EvenPseudo, in Select()
4385 ARM::VLD2DUPq16EvenPseudo, in Select()
4386 ARM::VLD2DUPq32EvenPseudo }; in Select()
4387 static const uint16_t QOpcodes1[] = { ARM::VLD2DUPq8OddPseudoWB_fixed, in Select()
4388 ARM::VLD2DUPq16OddPseudoWB_fixed, in Select()
4389 ARM::VLD2DUPq32OddPseudoWB_fixed }; in Select()
4395 static const uint16_t DOpcodes[] = { ARM::VLD3DUPd8Pseudo_UPD, in Select()
4396 ARM::VLD3DUPd16Pseudo_UPD, in Select()
4397 ARM::VLD3DUPd32Pseudo_UPD, in Select()
4398 ARM::VLD1d64TPseudoWB_fixed }; in Select()
4399 static const uint16_t QOpcodes0[] = { ARM::VLD3DUPq8EvenPseudo, in Select()
4400 ARM::VLD3DUPq16EvenPseudo, in Select()
4401 ARM::VLD3DUPq32EvenPseudo }; in Select()
4402 static const uint16_t QOpcodes1[] = { ARM::VLD3DUPq8OddPseudo_UPD, in Select()
4403 ARM::VLD3DUPq16OddPseudo_UPD, in Select()
4404 ARM::VLD3DUPq32OddPseudo_UPD }; in Select()
4410 static const uint16_t DOpcodes[] = { ARM::VLD4DUPd8Pseudo_UPD, in Select()
4411 ARM::VLD4DUPd16Pseudo_UPD, in Select()
4412 ARM::VLD4DUPd32Pseudo_UPD, in Select()
4413 ARM::VLD1d64QPseudoWB_fixed }; in Select()
4414 static const uint16_t QOpcodes0[] = { ARM::VLD4DUPq8EvenPseudo, in Select()
4415 ARM::VLD4DUPq16EvenPseudo, in Select()
4416 ARM::VLD4DUPq32EvenPseudo }; in Select()
4417 static const uint16_t QOpcodes1[] = { ARM::VLD4DUPq8OddPseudo_UPD, in Select()
4418 ARM::VLD4DUPq16OddPseudo_UPD, in Select()
4419 ARM::VLD4DUPq32OddPseudo_UPD }; in Select()
4425 static const uint16_t DOpcodes[] = { ARM::VLD1d8wb_fixed, in Select()
4426 ARM::VLD1d16wb_fixed, in Select()
4427 ARM::VLD1d32wb_fixed, in Select()
4428 ARM::VLD1d64wb_fixed }; in Select()
4429 static const uint16_t QOpcodes[] = { ARM::VLD1q8wb_fixed, in Select()
4430 ARM::VLD1q16wb_fixed, in Select()
4431 ARM::VLD1q32wb_fixed, in Select()
4432 ARM::VLD1q64wb_fixed }; in Select()
4440 ARM::VLD2d8wb_fixed, ARM::VLD2d16wb_fixed, ARM::VLD2d32wb_fixed, in Select()
4441 ARM::VLD1q64wb_fixed}; in Select()
4442 static const uint16_t QOpcodes[] = {ARM::VLD2q8PseudoWB_fixed, in Select()
4443 ARM::VLD2q16PseudoWB_fixed, in Select()
4444 ARM::VLD2q32PseudoWB_fixed}; in Select()
4447 static const uint16_t Opcodes8[] = {ARM::MVE_VLD20_8, in Select()
4448 ARM::MVE_VLD21_8_wb}; in Select()
4449 static const uint16_t Opcodes16[] = {ARM::MVE_VLD20_16, in Select()
4450 ARM::MVE_VLD21_16_wb}; in Select()
4451 static const uint16_t Opcodes32[] = {ARM::MVE_VLD20_32, in Select()
4452 ARM::MVE_VLD21_32_wb}; in Select()
4460 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo_UPD, in Select()
4461 ARM::VLD3d16Pseudo_UPD, in Select()
4462 ARM::VLD3d32Pseudo_UPD, in Select()
4463 ARM::VLD1d64TPseudoWB_fixed}; in Select()
4464 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD, in Select()
4465 ARM::VLD3q16Pseudo_UPD, in Select()
4466 ARM::VLD3q32Pseudo_UPD }; in Select()
4467 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD, in Select()
4468 ARM::VLD3q16oddPseudo_UPD, in Select()
4469 ARM::VLD3q32oddPseudo_UPD }; in Select()
4477 ARM::VLD4d8Pseudo_UPD, ARM::VLD4d16Pseudo_UPD, ARM::VLD4d32Pseudo_UPD, in Select()
4478 ARM::VLD1d64QPseudoWB_fixed}; in Select()
4479 static const uint16_t QOpcodes0[] = {ARM::VLD4q8Pseudo_UPD, in Select()
4480 ARM::VLD4q16Pseudo_UPD, in Select()
4481 ARM::VLD4q32Pseudo_UPD}; in Select()
4482 static const uint16_t QOpcodes1[] = {ARM::VLD4q8oddPseudo_UPD, in Select()
4483 ARM::VLD4q16oddPseudo_UPD, in Select()
4484 ARM::VLD4q32oddPseudo_UPD}; in Select()
4487 static const uint16_t Opcodes8[] = {ARM::MVE_VLD40_8, ARM::MVE_VLD41_8, in Select()
4488 ARM::MVE_VLD42_8, in Select()
4489 ARM::MVE_VLD43_8_wb}; in Select()
4490 static const uint16_t Opcodes16[] = {ARM::MVE_VLD40_16, ARM::MVE_VLD41_16, in Select()
4491 ARM::MVE_VLD42_16, in Select()
4492 ARM::MVE_VLD43_16_wb}; in Select()
4493 static const uint16_t Opcodes32[] = {ARM::MVE_VLD40_32, ARM::MVE_VLD41_32, in Select()
4494 ARM::MVE_VLD42_32, in Select()
4495 ARM::MVE_VLD43_32_wb}; in Select()
4505 ARM::VLD1q8wb_fixed, ARM::VLD1q16wb_fixed, ARM::VLD1q32wb_fixed, in Select()
4506 ARM::VLD1q64wb_fixed}; in Select()
4508 ARM::VLD1d8QPseudoWB_fixed, ARM::VLD1d16QPseudoWB_fixed, in Select()
4509 ARM::VLD1d32QPseudoWB_fixed, ARM::VLD1d64QPseudoWB_fixed}; in Select()
4519 ARM::VLD1d8TPseudoWB_fixed, ARM::VLD1d16TPseudoWB_fixed, in Select()
4520 ARM::VLD1d32TPseudoWB_fixed, ARM::VLD1d64TPseudoWB_fixed}; in Select()
4522 ARM::VLD1q8LowTPseudo_UPD, ARM::VLD1q16LowTPseudo_UPD, in Select()
4523 ARM::VLD1q32LowTPseudo_UPD, ARM::VLD1q64LowTPseudo_UPD}; in Select()
4525 ARM::VLD1q8HighTPseudo_UPD, ARM::VLD1q16HighTPseudo_UPD, in Select()
4526 ARM::VLD1q32HighTPseudo_UPD, ARM::VLD1q64HighTPseudo_UPD}; in Select()
4536 ARM::VLD1d8QPseudoWB_fixed, ARM::VLD1d16QPseudoWB_fixed, in Select()
4537 ARM::VLD1d32QPseudoWB_fixed, ARM::VLD1d64QPseudoWB_fixed}; in Select()
4539 ARM::VLD1q8LowQPseudo_UPD, ARM::VLD1q16LowQPseudo_UPD, in Select()
4540 ARM::VLD1q32LowQPseudo_UPD, ARM::VLD1q64LowQPseudo_UPD}; in Select()
4542 ARM::VLD1q8HighQPseudo_UPD, ARM::VLD1q16HighQPseudo_UPD, in Select()
4543 ARM::VLD1q32HighQPseudo_UPD, ARM::VLD1q64HighQPseudo_UPD}; in Select()
4551 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD, in Select()
4552 ARM::VLD2LNd16Pseudo_UPD, in Select()
4553 ARM::VLD2LNd32Pseudo_UPD }; in Select()
4554 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD, in Select()
4555 ARM::VLD2LNq32Pseudo_UPD }; in Select()
4561 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD, in Select()
4562 ARM::VLD3LNd16Pseudo_UPD, in Select()
4563 ARM::VLD3LNd32Pseudo_UPD }; in Select()
4564 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD, in Select()
4565 ARM::VLD3LNq32Pseudo_UPD }; in Select()
4571 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD, in Select()
4572 ARM::VLD4LNd16Pseudo_UPD, in Select()
4573 ARM::VLD4LNd32Pseudo_UPD }; in Select()
4574 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD, in Select()
4575 ARM::VLD4LNq32Pseudo_UPD }; in Select()
4581 static const uint16_t DOpcodes[] = { ARM::VST1d8wb_fixed, in Select()
4582 ARM::VST1d16wb_fixed, in Select()
4583 ARM::VST1d32wb_fixed, in Select()
4584 ARM::VST1d64wb_fixed }; in Select()
4585 static const uint16_t QOpcodes[] = { ARM::VST1q8wb_fixed, in Select()
4586 ARM::VST1q16wb_fixed, in Select()
4587 ARM::VST1q32wb_fixed, in Select()
4588 ARM::VST1q64wb_fixed }; in Select()
4596 ARM::VST2d8wb_fixed, ARM::VST2d16wb_fixed, ARM::VST2d32wb_fixed, in Select()
4597 ARM::VST1q64wb_fixed}; in Select()
4598 static const uint16_t QOpcodes[] = {ARM::VST2q8PseudoWB_fixed, in Select()
4599 ARM::VST2q16PseudoWB_fixed, in Select()
4600 ARM::VST2q32PseudoWB_fixed}; in Select()
4608 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo_UPD, in Select()
4609 ARM::VST3d16Pseudo_UPD, in Select()
4610 ARM::VST3d32Pseudo_UPD, in Select()
4611 ARM::VST1d64TPseudoWB_fixed}; in Select()
4612 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD, in Select()
4613 ARM::VST3q16Pseudo_UPD, in Select()
4614 ARM::VST3q32Pseudo_UPD }; in Select()
4615 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD, in Select()
4616 ARM::VST3q16oddPseudo_UPD, in Select()
4617 ARM::VST3q32oddPseudo_UPD }; in Select()
4625 ARM::VST4d8Pseudo_UPD, ARM::VST4d16Pseudo_UPD, ARM::VST4d32Pseudo_UPD, in Select()
4626 ARM::VST1d64QPseudoWB_fixed}; in Select()
4627 static const uint16_t QOpcodes0[] = {ARM::VST4q8Pseudo_UPD, in Select()
4628 ARM::VST4q16Pseudo_UPD, in Select()
4629 ARM::VST4q32Pseudo_UPD}; in Select()
4630 static const uint16_t QOpcodes1[] = {ARM::VST4q8oddPseudo_UPD, in Select()
4631 ARM::VST4q16oddPseudo_UPD, in Select()
4632 ARM::VST4q32oddPseudo_UPD}; in Select()
4641 static const uint16_t DOpcodes[] = { ARM::VST1q8wb_fixed, in Select()
4642 ARM::VST1q16wb_fixed, in Select()
4643 ARM::VST1q32wb_fixed, in Select()
4644 ARM::VST1q64wb_fixed}; in Select()
4645 static const uint16_t QOpcodes[] = { ARM::VST1d8QPseudoWB_fixed, in Select()
4646 ARM::VST1d16QPseudoWB_fixed, in Select()
4647 ARM::VST1d32QPseudoWB_fixed, in Select()
4648 ARM::VST1d64QPseudoWB_fixed }; in Select()
4657 static const uint16_t DOpcodes[] = { ARM::VST1d8TPseudoWB_fixed, in Select()
4658 ARM::VST1d16TPseudoWB_fixed, in Select()
4659 ARM::VST1d32TPseudoWB_fixed, in Select()
4660 ARM::VST1d64TPseudoWB_fixed }; in Select()
4661 static const uint16_t QOpcodes0[] = { ARM::VST1q8LowTPseudo_UPD, in Select()
4662 ARM::VST1q16LowTPseudo_UPD, in Select()
4663 ARM::VST1q32LowTPseudo_UPD, in Select()
4664 ARM::VST1q64LowTPseudo_UPD }; in Select()
4665 static const uint16_t QOpcodes1[] = { ARM::VST1q8HighTPseudo_UPD, in Select()
4666 ARM::VST1q16HighTPseudo_UPD, in Select()
4667 ARM::VST1q32HighTPseudo_UPD, in Select()
4668 ARM::VST1q64HighTPseudo_UPD }; in Select()
4677 static const uint16_t DOpcodes[] = { ARM::VST1d8QPseudoWB_fixed, in Select()
4678 ARM::VST1d16QPseudoWB_fixed, in Select()
4679 ARM::VST1d32QPseudoWB_fixed, in Select()
4680 ARM::VST1d64QPseudoWB_fixed }; in Select()
4681 static const uint16_t QOpcodes0[] = { ARM::VST1q8LowQPseudo_UPD, in Select()
4682 ARM::VST1q16LowQPseudo_UPD, in Select()
4683 ARM::VST1q32LowQPseudo_UPD, in Select()
4684 ARM::VST1q64LowQPseudo_UPD }; in Select()
4685 static const uint16_t QOpcodes1[] = { ARM::VST1q8HighQPseudo_UPD, in Select()
4686 ARM::VST1q16HighQPseudo_UPD, in Select()
4687 ARM::VST1q32HighQPseudo_UPD, in Select()
4688 ARM::VST1q64HighQPseudo_UPD }; in Select()
4695 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD, in Select()
4696 ARM::VST2LNd16Pseudo_UPD, in Select()
4697 ARM::VST2LNd32Pseudo_UPD }; in Select()
4698 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD, in Select()
4699 ARM::VST2LNq32Pseudo_UPD }; in Select()
4705 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD, in Select()
4706 ARM::VST3LNd16Pseudo_UPD, in Select()
4707 ARM::VST3LNd32Pseudo_UPD }; in Select()
4708 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD, in Select()
4709 ARM::VST3LNq32Pseudo_UPD }; in Select()
4715 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD, in Select()
4716 ARM::VST4LNd16Pseudo_UPD, in Select()
4717 ARM::VST4LNd32Pseudo_UPD }; in Select()
4718 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD, in Select()
4719 ARM::VST4LNq32Pseudo_UPD }; in Select()
4738 Opc = (IntNo == Intrinsic::arm_mrrc ? ARM::t2MRRC : ARM::t2MRRC2); in Select()
4740 Opc = (IntNo == Intrinsic::arm_mrrc ? ARM::MRRC : ARM::MRRC2); in Select()
4750 if (Opc != ARM::MRRC2) { in Select()
4771 unsigned NewOpc = isThumb ? (IsAcquire ? ARM::t2LDAEXD : ARM::t2LDREXD) in Select()
4772 : (IsAcquire ? ARM::LDAEXD : ARM::LDREXD); in Select()
4799 CurDAG->getTargetConstant(ARM::gsub_0, dl, MVT::i32); in Select()
4812 CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32); in Select()
4850 unsigned NewOpc = isThumb ? (IsRelease ? ARM::t2STLEXD : ARM::t2STREXD) in Select()
4851 : (IsRelease ? ARM::STLEXD : ARM::STREXD); in Select()
4863 static const uint16_t DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16, in Select()
4864 ARM::VLD1d32, ARM::VLD1d64 }; in Select()
4865 static const uint16_t QOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16, in Select()
4866 ARM::VLD1q32, ARM::VLD1q64}; in Select()
4872 static const uint16_t DOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16, in Select()
4873 ARM::VLD1q32, ARM::VLD1q64 }; in Select()
4874 static const uint16_t QOpcodes[] = { ARM::VLD1d8QPseudo, in Select()
4875 ARM::VLD1d16QPseudo, in Select()
4876 ARM::VLD1d32QPseudo, in Select()
4877 ARM::VLD1d64QPseudo }; in Select()
4883 static const uint16_t DOpcodes[] = { ARM::VLD1d8TPseudo, in Select()
4884 ARM::VLD1d16TPseudo, in Select()
4885 ARM::VLD1d32TPseudo, in Select()
4886 ARM::VLD1d64TPseudo }; in Select()
4887 static const uint16_t QOpcodes0[] = { ARM::VLD1q8LowTPseudo_UPD, in Select()
4888 ARM::VLD1q16LowTPseudo_UPD, in Select()
4889 ARM::VLD1q32LowTPseudo_UPD, in Select()
4890 ARM::VLD1q64LowTPseudo_UPD }; in Select()
4891 static const uint16_t QOpcodes1[] = { ARM::VLD1q8HighTPseudo, in Select()
4892 ARM::VLD1q16HighTPseudo, in Select()
4893 ARM::VLD1q32HighTPseudo, in Select()
4894 ARM::VLD1q64HighTPseudo }; in Select()
4900 static const uint16_t DOpcodes[] = { ARM::VLD1d8QPseudo, in Select()
4901 ARM::VLD1d16QPseudo, in Select()
4902 ARM::VLD1d32QPseudo, in Select()
4903 ARM::VLD1d64QPseudo }; in Select()
4904 static const uint16_t QOpcodes0[] = { ARM::VLD1q8LowQPseudo_UPD, in Select()
4905 ARM::VLD1q16LowQPseudo_UPD, in Select()
4906 ARM::VLD1q32LowQPseudo_UPD, in Select()
4907 ARM::VLD1q64LowQPseudo_UPD }; in Select()
4908 static const uint16_t QOpcodes1[] = { ARM::VLD1q8HighQPseudo, in Select()
4909 ARM::VLD1q16HighQPseudo, in Select()
4910 ARM::VLD1q32HighQPseudo, in Select()
4911 ARM::VLD1q64HighQPseudo }; in Select()
4917 static const uint16_t DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16, in Select()
4918 ARM::VLD2d32, ARM::VLD1q64 }; in Select()
4919 static const uint16_t QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo, in Select()
4920 ARM::VLD2q32Pseudo }; in Select()
4926 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo, in Select()
4927 ARM::VLD3d16Pseudo, in Select()
4928 ARM::VLD3d32Pseudo, in Select()
4929 ARM::VLD1d64TPseudo }; in Select()
4930 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD, in Select()
4931 ARM::VLD3q16Pseudo_UPD, in Select()
4932 ARM::VLD3q32Pseudo_UPD }; in Select()
4933 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo, in Select()
4934 ARM::VLD3q16oddPseudo, in Select()
4935 ARM::VLD3q32oddPseudo }; in Select()
4941 static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo, in Select()
4942 ARM::VLD4d16Pseudo, in Select()
4943 ARM::VLD4d32Pseudo, in Select()
4944 ARM::VLD1d64QPseudo }; in Select()
4945 static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD, in Select()
4946 ARM::VLD4q16Pseudo_UPD, in Select()
4947 ARM::VLD4q32Pseudo_UPD }; in Select()
4948 static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo, in Select()
4949 ARM::VLD4q16oddPseudo, in Select()
4950 ARM::VLD4q32oddPseudo }; in Select()
4956 static const uint16_t DOpcodes[] = { ARM::VLD2DUPd8, ARM::VLD2DUPd16, in Select()
4957 ARM::VLD2DUPd32, ARM::VLD1q64 }; in Select()
4958 static const uint16_t QOpcodes0[] = { ARM::VLD2DUPq8EvenPseudo, in Select()
4959 ARM::VLD2DUPq16EvenPseudo, in Select()
4960 ARM::VLD2DUPq32EvenPseudo }; in Select()
4961 static const uint16_t QOpcodes1[] = { ARM::VLD2DUPq8OddPseudo, in Select()
4962 ARM::VLD2DUPq16OddPseudo, in Select()
4963 ARM::VLD2DUPq32OddPseudo }; in Select()
4970 static const uint16_t DOpcodes[] = { ARM::VLD3DUPd8Pseudo, in Select()
4971 ARM::VLD3DUPd16Pseudo, in Select()
4972 ARM::VLD3DUPd32Pseudo, in Select()
4973 ARM::VLD1d64TPseudo }; in Select()
4974 static const uint16_t QOpcodes0[] = { ARM::VLD3DUPq8EvenPseudo, in Select()
4975 ARM::VLD3DUPq16EvenPseudo, in Select()
4976 ARM::VLD3DUPq32EvenPseudo }; in Select()
4977 static const uint16_t QOpcodes1[] = { ARM::VLD3DUPq8OddPseudo, in Select()
4978 ARM::VLD3DUPq16OddPseudo, in Select()
4979 ARM::VLD3DUPq32OddPseudo }; in Select()
4986 static const uint16_t DOpcodes[] = { ARM::VLD4DUPd8Pseudo, in Select()
4987 ARM::VLD4DUPd16Pseudo, in Select()
4988 ARM::VLD4DUPd32Pseudo, in Select()
4989 ARM::VLD1d64QPseudo }; in Select()
4990 static const uint16_t QOpcodes0[] = { ARM::VLD4DUPq8EvenPseudo, in Select()
4991 ARM::VLD4DUPq16EvenPseudo, in Select()
4992 ARM::VLD4DUPq32EvenPseudo }; in Select()
4993 static const uint16_t QOpcodes1[] = { ARM::VLD4DUPq8OddPseudo, in Select()
4994 ARM::VLD4DUPq16OddPseudo, in Select()
4995 ARM::VLD4DUPq32OddPseudo }; in Select()
5002 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo, in Select()
5003 ARM::VLD2LNd16Pseudo, in Select()
5004 ARM::VLD2LNd32Pseudo }; in Select()
5005 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo, in Select()
5006 ARM::VLD2LNq32Pseudo }; in Select()
5012 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo, in Select()
5013 ARM::VLD3LNd16Pseudo, in Select()
5014 ARM::VLD3LNd32Pseudo }; in Select()
5015 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo, in Select()
5016 ARM::VLD3LNq32Pseudo }; in Select()
5022 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo, in Select()
5023 ARM::VLD4LNd16Pseudo, in Select()
5024 ARM::VLD4LNd32Pseudo }; in Select()
5025 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo, in Select()
5026 ARM::VLD4LNq32Pseudo }; in Select()
5032 static const uint16_t DOpcodes[] = { ARM::VST1d8, ARM::VST1d16, in Select()
5033 ARM::VST1d32, ARM::VST1d64 }; in Select()
5034 static const uint16_t QOpcodes[] = { ARM::VST1q8, ARM::VST1q16, in Select()
5035 ARM::VST1q32, ARM::VST1q64 }; in Select()
5041 static const uint16_t DOpcodes[] = { ARM::VST1q8, ARM::VST1q16, in Select()
5042 ARM::VST1q32, ARM::VST1q64 }; in Select()
5043 static const uint16_t QOpcodes[] = { ARM::VST1d8QPseudo, in Select()
5044 ARM::VST1d16QPseudo, in Select()
5045 ARM::VST1d32QPseudo, in Select()
5046 ARM::VST1d64QPseudo }; in Select()
5052 static const uint16_t DOpcodes[] = { ARM::VST1d8TPseudo, in Select()
5053 ARM::VST1d16TPseudo, in Select()
5054 ARM::VST1d32TPseudo, in Select()
5055 ARM::VST1d64TPseudo }; in Select()
5056 static const uint16_t QOpcodes0[] = { ARM::VST1q8LowTPseudo_UPD, in Select()
5057 ARM::VST1q16LowTPseudo_UPD, in Select()
5058 ARM::VST1q32LowTPseudo_UPD, in Select()
5059 ARM::VST1q64LowTPseudo_UPD }; in Select()
5060 static const uint16_t QOpcodes1[] = { ARM::VST1q8HighTPseudo, in Select()
5061 ARM::VST1q16HighTPseudo, in Select()
5062 ARM::VST1q32HighTPseudo, in Select()
5063 ARM::VST1q64HighTPseudo }; in Select()
5069 static const uint16_t DOpcodes[] = { ARM::VST1d8QPseudo, in Select()
5070 ARM::VST1d16QPseudo, in Select()
5071 ARM::VST1d32QPseudo, in Select()
5072 ARM::VST1d64QPseudo }; in Select()
5073 static const uint16_t QOpcodes0[] = { ARM::VST1q8LowQPseudo_UPD, in Select()
5074 ARM::VST1q16LowQPseudo_UPD, in Select()
5075 ARM::VST1q32LowQPseudo_UPD, in Select()
5076 ARM::VST1q64LowQPseudo_UPD }; in Select()
5077 static const uint16_t QOpcodes1[] = { ARM::VST1q8HighQPseudo, in Select()
5078 ARM::VST1q16HighQPseudo, in Select()
5079 ARM::VST1q32HighQPseudo, in Select()
5080 ARM::VST1q64HighQPseudo }; in Select()
5086 static const uint16_t DOpcodes[] = { ARM::VST2d8, ARM::VST2d16, in Select()
5087 ARM::VST2d32, ARM::VST1q64 }; in Select()
5088 static const uint16_t QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo, in Select()
5089 ARM::VST2q32Pseudo }; in Select()
5095 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo, in Select()
5096 ARM::VST3d16Pseudo, in Select()
5097 ARM::VST3d32Pseudo, in Select()
5098 ARM::VST1d64TPseudo }; in Select()
5099 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD, in Select()
5100 ARM::VST3q16Pseudo_UPD, in Select()
5101 ARM::VST3q32Pseudo_UPD }; in Select()
5102 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo, in Select()
5103 ARM::VST3q16oddPseudo, in Select()
5104 ARM::VST3q32oddPseudo }; in Select()
5110 static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo, in Select()
5111 ARM::VST4d16Pseudo, in Select()
5112 ARM::VST4d32Pseudo, in Select()
5113 ARM::VST1d64QPseudo }; in Select()
5114 static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD, in Select()
5115 ARM::VST4q16Pseudo_UPD, in Select()
5116 ARM::VST4q32Pseudo_UPD }; in Select()
5117 static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo, in Select()
5118 ARM::VST4q16oddPseudo, in Select()
5119 ARM::VST4q32oddPseudo }; in Select()
5125 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo, in Select()
5126 ARM::VST2LNd16Pseudo, in Select()
5127 ARM::VST2LNd32Pseudo }; in Select()
5128 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo, in Select()
5129 ARM::VST2LNq32Pseudo }; in Select()
5135 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo, in Select()
5136 ARM::VST3LNd16Pseudo, in Select()
5137 ARM::VST3LNd32Pseudo }; in Select()
5138 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo, in Select()
5139 ARM::VST3LNq32Pseudo }; in Select()
5145 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo, in Select()
5146 ARM::VST4LNd16Pseudo, in Select()
5147 ARM::VST4LNd32Pseudo }; in Select()
5148 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo, in Select()
5149 ARM::VST4LNq32Pseudo }; in Select()
5156 static const uint16_t Opcodes[] = {ARM::MVE_VLDRWU32_qi_pre, in Select()
5157 ARM::MVE_VLDRDU64_qi_pre}; in Select()
5164 static const uint16_t Opcodes8[] = {ARM::MVE_VLD20_8, ARM::MVE_VLD21_8}; in Select()
5165 static const uint16_t Opcodes16[] = {ARM::MVE_VLD20_16, in Select()
5166 ARM::MVE_VLD21_16}; in Select()
5167 static const uint16_t Opcodes32[] = {ARM::MVE_VLD20_32, in Select()
5168 ARM::MVE_VLD21_32}; in Select()
5175 static const uint16_t Opcodes8[] = {ARM::MVE_VLD40_8, ARM::MVE_VLD41_8, in Select()
5176 ARM::MVE_VLD42_8, ARM::MVE_VLD43_8}; in Select()
5177 static const uint16_t Opcodes16[] = {ARM::MVE_VLD40_16, ARM::MVE_VLD41_16, in Select()
5178 ARM::MVE_VLD42_16, in Select()
5179 ARM::MVE_VLD43_16}; in Select()
5180 static const uint16_t Opcodes32[] = {ARM::MVE_VLD40_32, ARM::MVE_VLD41_32, in Select()
5181 ARM::MVE_VLD42_32, in Select()
5182 ARM::MVE_VLD43_32}; in Select()
5205 CurDAG->SelectNodeTo(N, ARM::BF16_VCVTB, DestTy, Ops); in Select()
5216 CurDAG->SelectNodeTo(N, ARM::BF16_VCVT, MVT::v4bf16, Ops); in Select()
5221 SelectMVE_LongShift(N, ARM::MVE_URSHRL, true, false); in Select()
5224 SelectMVE_LongShift(N, ARM::MVE_UQSHLL, true, false); in Select()
5227 SelectMVE_LongShift(N, ARM::MVE_SRSHRL, true, false); in Select()
5230 SelectMVE_LongShift(N, ARM::MVE_SQSHLL, true, false); in Select()
5233 SelectMVE_LongShift(N, ARM::MVE_UQRSHLL, false, true); in Select()
5236 SelectMVE_LongShift(N, ARM::MVE_SQRSHRL, false, true); in Select()
5241 SelectMVE_VADCSBC(N, ARM::MVE_VADC, ARM::MVE_VADCI, true, in Select()
5246 SelectMVE_VADCSBC(N, ARM::MVE_VSBC, ARM::MVE_VSBCI, true, in Select()
5257 ARM::MVE_VMLALDAVu16, ARM::MVE_VMLALDAVu32, in Select()
5258 ARM::MVE_VMLALDAVau16, ARM::MVE_VMLALDAVau32, in Select()
5261 ARM::MVE_VMLALDAVs16, ARM::MVE_VMLALDAVs32, in Select()
5262 ARM::MVE_VMLALDAVas16, ARM::MVE_VMLALDAVas32, in Select()
5263 ARM::MVE_VMLALDAVxs16, ARM::MVE_VMLALDAVxs32, in Select()
5264 ARM::MVE_VMLALDAVaxs16, ARM::MVE_VMLALDAVaxs32, in Select()
5265 ARM::MVE_VMLSLDAVs16, ARM::MVE_VMLSLDAVs32, in Select()
5266 ARM::MVE_VMLSLDAVas16, ARM::MVE_VMLSLDAVas32, in Select()
5267 ARM::MVE_VMLSLDAVxs16, ARM::MVE_VMLSLDAVxs32, in Select()
5268 ARM::MVE_VMLSLDAVaxs16, ARM::MVE_VMLSLDAVaxs32, in Select()
5278 ARM::MVE_VRMLALDAVHu32, ARM::MVE_VRMLALDAVHau32, in Select()
5281 ARM::MVE_VRMLALDAVHs32, ARM::MVE_VRMLALDAVHas32, in Select()
5282 ARM::MVE_VRMLALDAVHxs32, ARM::MVE_VRMLALDAVHaxs32, in Select()
5283 ARM::MVE_VRMLSLDAVHs32, ARM::MVE_VRMLSLDAVHas32, in Select()
5284 ARM::MVE_VRMLSLDAVHxs32, ARM::MVE_VRMLSLDAVHaxs32, in Select()
5294 ARM::MVE_VIDUPu8, ARM::MVE_VIDUPu16, ARM::MVE_VIDUPu32, in Select()
5304 ARM::MVE_VDDUPu8, ARM::MVE_VDDUPu16, ARM::MVE_VDDUPu32, in Select()
5314 ARM::MVE_VIWDUPu8, ARM::MVE_VIWDUPu16, ARM::MVE_VIWDUPu32, in Select()
5324 ARM::MVE_VDWDUPu8, ARM::MVE_VDWDUPu16, ARM::MVE_VDWDUPu32, in Select()
5346 Opcode = HasAccum ? ARM::CDE_CX1DA : ARM::CDE_CX1D; in Select()
5351 Opcode = HasAccum ? ARM::CDE_CX2DA : ARM::CDE_CX2D; in Select()
5356 Opcode = HasAccum ? ARM::CDE_CX3DA : ARM::CDE_CX3D; in Select()
5518 Opcode = IsThumb2 ? ARM::t2MRC : ARM::MRC; in tryReadRegister()
5523 Opcode = IsThumb2 ? ARM::t2MRRC : ARM::MRRC; in tryReadRegister()
5542 N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRSbanked : ARM::MRSbanked, in tryReadRegister()
5551 .Case("fpscr", ARM::VMRS) in tryReadRegister()
5552 .Case("fpexc", ARM::VMRS_FPEXC) in tryReadRegister()
5553 .Case("fpsid", ARM::VMRS_FPSID) in tryReadRegister()
5554 .Case("mvfr0", ARM::VMRS_MVFR0) in tryReadRegister()
5555 .Case("mvfr1", ARM::VMRS_MVFR1) in tryReadRegister()
5556 .Case("mvfr2", ARM::VMRS_MVFR2) in tryReadRegister()
5557 .Case("fpinst", ARM::VMRS_FPINST) in tryReadRegister()
5558 .Case("fpinst2", ARM::VMRS_FPINST2) in tryReadRegister()
5565 if (Opcode == ARM::VMRS_MVFR2 && !Subtarget->hasFPARMv8Base()) in tryReadRegister()
5587 N, CurDAG->getMachineNode(ARM::t2MRS_M, DL, MVT::i32, MVT::Other, Ops)); in tryReadRegister()
5596 ReplaceNode(N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRS_AR : ARM::MRS, in tryReadRegister()
5605 N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRSsys_AR : ARM::MRSsys, DL, in tryReadRegister()
5632 Opcode = IsThumb2 ? ARM::t2MCR : ARM::MCR; in tryWriteRegister()
5637 Opcode = IsThumb2 ? ARM::t2MCRR : ARM::MCRR; in tryWriteRegister()
5657 N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MSRbanked : ARM::MSRbanked, in tryWriteRegister()
5666 .Case("fpscr", ARM::VMSR) in tryWriteRegister()
5667 .Case("fpexc", ARM::VMSR_FPEXC) in tryWriteRegister()
5668 .Case("fpsid", ARM::VMSR_FPSID) in tryWriteRegister()
5669 .Case("fpinst", ARM::VMSR_FPINST) in tryWriteRegister()
5670 .Case("fpinst2", ARM::VMSR_FPINST2) in tryWriteRegister()
5697 ReplaceNode(N, CurDAG->getMachineNode(ARM::t2MSR_M, DL, MVT::Other, Ops)); in tryWriteRegister()
5709 ReplaceNode(N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MSR_AR : ARM::MSR, in tryWriteRegister()
5789 if ((!IsTiedToChangedOp && (!HasRC || RC != ARM::GPRRegClassID)) in tryInlineAsm()
5806 Register GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass); in tryInlineAsm()
5815 SDValue Sub0 = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32, in tryInlineAsm()
5817 SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32, in tryInlineAsm()
5842 Register GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass); in tryInlineAsm()
5858 Flag = InlineAsm::getFlagWordForRegClass(Flag, ARM::GPRPairRegClassID); in tryInlineAsm()