Lines Matching refs:ARM
587 case ARM::HVC: { in checkDecodedInstruction()
597 case ARM::t2ADDri: in checkDecodedInstruction()
598 case ARM::t2ADDri12: in checkDecodedInstruction()
599 case ARM::t2ADDrr: in checkDecodedInstruction()
600 case ARM::t2ADDrs: in checkDecodedInstruction()
601 case ARM::t2SUBri: in checkDecodedInstruction()
602 case ARM::t2SUBri12: in checkDecodedInstruction()
603 case ARM::t2SUBrr: in checkDecodedInstruction()
604 case ARM::t2SUBrs: in checkDecodedInstruction()
605 if (MI.getOperand(0).getReg() == ARM::SP && in checkDecodedInstruction()
606 MI.getOperand(1).getReg() != ARM::SP) in checkDecodedInstruction()
617 if (STI.getFeatureBits()[ARM::ModeThumb]) in getInstruction()
628 assert(!STI.getFeatureBits()[ARM::ModeThumb] && in getARMInstruction()
737 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { in AddThumb1SBit()
739 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
744 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
751 if (ARM::isVpred(OpInfo[i].OperandType)) in isVectorPredicable()
770 case ARM::tBcc: in AddThumbPredicate()
771 case ARM::t2Bcc: in AddThumbPredicate()
772 case ARM::tCBZ: in AddThumbPredicate()
773 case ARM::tCBNZ: in AddThumbPredicate()
774 case ARM::tCPS: in AddThumbPredicate()
775 case ARM::t2CPS3p: in AddThumbPredicate()
776 case ARM::t2CPS2p: in AddThumbPredicate()
777 case ARM::t2CPS1p: in AddThumbPredicate()
778 case ARM::t2CSEL: in AddThumbPredicate()
779 case ARM::t2CSINC: in AddThumbPredicate()
780 case ARM::t2CSINV: in AddThumbPredicate()
781 case ARM::t2CSNEG: in AddThumbPredicate()
782 case ARM::tMOVSr: in AddThumbPredicate()
783 case ARM::tSETEND: in AddThumbPredicate()
791 case ARM::t2HINT: in AddThumbPredicate()
792 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) in AddThumbPredicate()
795 case ARM::tB: in AddThumbPredicate()
796 case ARM::t2B: in AddThumbPredicate()
797 case ARM::t2TBB: in AddThumbPredicate()
798 case ARM::t2TBH: in AddThumbPredicate()
840 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); in AddThumbPredicate()
848 if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break; in AddThumbPredicate()
857 MI.insert(VCCI, MCOperand::createReg(ARM::P0)); in AddThumbPredicate()
858 if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) { in AddThumbPredicate()
903 I->setReg(ARM::CPSR); in UpdateThumbVFPPredicate()
915 assert(STI.getFeatureBits()[ARM::ModeThumb] && in getThumbInstruction()
950 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) in getThumbInstruction()
958 if (MI.getOpcode() == ARM::t2IT) { in getThumbInstruction()
1093 const uint8_t *DecoderTable = ARM::isCDECoproc(Coproc, STI) in getThumbInstruction()
1120 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1121 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1122 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1123 ARM::R12, ARM::SP, ARM::LR, ARM::PC
1127 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1128 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1129 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1130 ARM::R12, 0, ARM::LR, ARM::APSR
1177 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); in DecodeGPRwithAPSRRegisterClass()
1192 Inst.addOperand(MCOperand::createReg(ARM::ZR)); in DecodeGPRwithZRRegisterClass()
1221 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
1222 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
1271 Register = ARM::R0; in DecodetcGPRRegisterClass()
1274 Register = ARM::R1; in DecodetcGPRRegisterClass()
1277 Register = ARM::R2; in DecodetcGPRRegisterClass()
1280 Register = ARM::R3; in DecodetcGPRRegisterClass()
1283 Register = ARM::R9; in DecodetcGPRRegisterClass()
1286 Register = ARM::R12; in DecodetcGPRRegisterClass()
1303 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) in DecoderGPRRegisterClass()
1311 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1312 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1313 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1314 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
1315 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
1316 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
1317 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
1318 ARM::S28, ARM::S29, ARM::S30, ARM::S31
1337 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1338 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1339 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1340 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1341 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1342 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1343 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1344 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1352 bool hasD32 = featureBits[ARM::FeatureD32]; in DecodeDPRRegisterClass()
1385 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1386 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1387 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1388 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1403 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1404 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1405 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1406 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1407 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1408 ARM::Q15
1422 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1423 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1424 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1425 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1426 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1427 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1428 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1429 ARM::D28_D30, ARM::D29_D31
1449 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) in DecodePredicateOperand()
1457 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); in DecodePredicateOperand()
1464 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); in DecodeCCOutOperand()
1552 case ARM::LDMIA_UPD: in DecodeRegListOperand()
1553 case ARM::LDMDB_UPD: in DecodeRegListOperand()
1554 case ARM::LDMIB_UPD: in DecodeRegListOperand()
1555 case ARM::LDMDA_UPD: in DecodeRegListOperand()
1556 case ARM::t2LDMIA_UPD: in DecodeRegListOperand()
1557 case ARM::t2LDMDB_UPD: in DecodeRegListOperand()
1558 case ARM::t2STMIA_UPD: in DecodeRegListOperand()
1559 case ARM::t2STMDB_UPD: in DecodeRegListOperand()
1563 case ARM::t2CLRM: in DecodeRegListOperand()
1679 case ARM::LDC_OFFSET: in DecodeCopMemInstruction()
1680 case ARM::LDC_PRE: in DecodeCopMemInstruction()
1681 case ARM::LDC_POST: in DecodeCopMemInstruction()
1682 case ARM::LDC_OPTION: in DecodeCopMemInstruction()
1683 case ARM::LDCL_OFFSET: in DecodeCopMemInstruction()
1684 case ARM::LDCL_PRE: in DecodeCopMemInstruction()
1685 case ARM::LDCL_POST: in DecodeCopMemInstruction()
1686 case ARM::LDCL_OPTION: in DecodeCopMemInstruction()
1687 case ARM::STC_OFFSET: in DecodeCopMemInstruction()
1688 case ARM::STC_PRE: in DecodeCopMemInstruction()
1689 case ARM::STC_POST: in DecodeCopMemInstruction()
1690 case ARM::STC_OPTION: in DecodeCopMemInstruction()
1691 case ARM::STCL_OFFSET: in DecodeCopMemInstruction()
1692 case ARM::STCL_PRE: in DecodeCopMemInstruction()
1693 case ARM::STCL_POST: in DecodeCopMemInstruction()
1694 case ARM::STCL_OPTION: in DecodeCopMemInstruction()
1695 case ARM::t2LDC_OFFSET: in DecodeCopMemInstruction()
1696 case ARM::t2LDC_PRE: in DecodeCopMemInstruction()
1697 case ARM::t2LDC_POST: in DecodeCopMemInstruction()
1698 case ARM::t2LDC_OPTION: in DecodeCopMemInstruction()
1699 case ARM::t2LDCL_OFFSET: in DecodeCopMemInstruction()
1700 case ARM::t2LDCL_PRE: in DecodeCopMemInstruction()
1701 case ARM::t2LDCL_POST: in DecodeCopMemInstruction()
1702 case ARM::t2LDCL_OPTION: in DecodeCopMemInstruction()
1703 case ARM::t2STC_OFFSET: in DecodeCopMemInstruction()
1704 case ARM::t2STC_PRE: in DecodeCopMemInstruction()
1705 case ARM::t2STC_POST: in DecodeCopMemInstruction()
1706 case ARM::t2STC_OPTION: in DecodeCopMemInstruction()
1707 case ARM::t2STCL_OFFSET: in DecodeCopMemInstruction()
1708 case ARM::t2STCL_PRE: in DecodeCopMemInstruction()
1709 case ARM::t2STCL_POST: in DecodeCopMemInstruction()
1710 case ARM::t2STCL_OPTION: in DecodeCopMemInstruction()
1711 case ARM::t2LDC2_OFFSET: in DecodeCopMemInstruction()
1712 case ARM::t2LDC2L_OFFSET: in DecodeCopMemInstruction()
1713 case ARM::t2LDC2_PRE: in DecodeCopMemInstruction()
1714 case ARM::t2LDC2L_PRE: in DecodeCopMemInstruction()
1715 case ARM::t2STC2_OFFSET: in DecodeCopMemInstruction()
1716 case ARM::t2STC2L_OFFSET: in DecodeCopMemInstruction()
1717 case ARM::t2STC2_PRE: in DecodeCopMemInstruction()
1718 case ARM::t2STC2L_PRE: in DecodeCopMemInstruction()
1719 case ARM::LDC2_OFFSET: in DecodeCopMemInstruction()
1720 case ARM::LDC2L_OFFSET: in DecodeCopMemInstruction()
1721 case ARM::LDC2_PRE: in DecodeCopMemInstruction()
1722 case ARM::LDC2L_PRE: in DecodeCopMemInstruction()
1723 case ARM::STC2_OFFSET: in DecodeCopMemInstruction()
1724 case ARM::STC2L_OFFSET: in DecodeCopMemInstruction()
1725 case ARM::STC2_PRE: in DecodeCopMemInstruction()
1726 case ARM::STC2L_PRE: in DecodeCopMemInstruction()
1727 case ARM::t2LDC2_OPTION: in DecodeCopMemInstruction()
1728 case ARM::t2STC2_OPTION: in DecodeCopMemInstruction()
1729 case ARM::t2LDC2_POST: in DecodeCopMemInstruction()
1730 case ARM::t2LDC2L_POST: in DecodeCopMemInstruction()
1731 case ARM::t2STC2_POST: in DecodeCopMemInstruction()
1732 case ARM::t2STC2L_POST: in DecodeCopMemInstruction()
1733 case ARM::LDC2_POST: in DecodeCopMemInstruction()
1734 case ARM::LDC2L_POST: in DecodeCopMemInstruction()
1735 case ARM::STC2_POST: in DecodeCopMemInstruction()
1736 case ARM::STC2L_POST: in DecodeCopMemInstruction()
1738 (featureBits[ARM::HasV8_1MMainlineOps] && in DecodeCopMemInstruction()
1747 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) in DecodeCopMemInstruction()
1756 case ARM::t2LDC2_OFFSET: in DecodeCopMemInstruction()
1757 case ARM::t2LDC2L_OFFSET: in DecodeCopMemInstruction()
1758 case ARM::t2LDC2_PRE: in DecodeCopMemInstruction()
1759 case ARM::t2LDC2L_PRE: in DecodeCopMemInstruction()
1760 case ARM::t2STC2_OFFSET: in DecodeCopMemInstruction()
1761 case ARM::t2STC2L_OFFSET: in DecodeCopMemInstruction()
1762 case ARM::t2STC2_PRE: in DecodeCopMemInstruction()
1763 case ARM::t2STC2L_PRE: in DecodeCopMemInstruction()
1764 case ARM::LDC2_OFFSET: in DecodeCopMemInstruction()
1765 case ARM::LDC2L_OFFSET: in DecodeCopMemInstruction()
1766 case ARM::LDC2_PRE: in DecodeCopMemInstruction()
1767 case ARM::LDC2L_PRE: in DecodeCopMemInstruction()
1768 case ARM::STC2_OFFSET: in DecodeCopMemInstruction()
1769 case ARM::STC2L_OFFSET: in DecodeCopMemInstruction()
1770 case ARM::STC2_PRE: in DecodeCopMemInstruction()
1771 case ARM::STC2L_PRE: in DecodeCopMemInstruction()
1772 case ARM::t2LDC_OFFSET: in DecodeCopMemInstruction()
1773 case ARM::t2LDCL_OFFSET: in DecodeCopMemInstruction()
1774 case ARM::t2LDC_PRE: in DecodeCopMemInstruction()
1775 case ARM::t2LDCL_PRE: in DecodeCopMemInstruction()
1776 case ARM::t2STC_OFFSET: in DecodeCopMemInstruction()
1777 case ARM::t2STCL_OFFSET: in DecodeCopMemInstruction()
1778 case ARM::t2STC_PRE: in DecodeCopMemInstruction()
1779 case ARM::t2STCL_PRE: in DecodeCopMemInstruction()
1780 case ARM::LDC_OFFSET: in DecodeCopMemInstruction()
1781 case ARM::LDCL_OFFSET: in DecodeCopMemInstruction()
1782 case ARM::LDC_PRE: in DecodeCopMemInstruction()
1783 case ARM::LDCL_PRE: in DecodeCopMemInstruction()
1784 case ARM::STC_OFFSET: in DecodeCopMemInstruction()
1785 case ARM::STCL_OFFSET: in DecodeCopMemInstruction()
1786 case ARM::STC_PRE: in DecodeCopMemInstruction()
1787 case ARM::STCL_PRE: in DecodeCopMemInstruction()
1791 case ARM::t2LDC2_POST: in DecodeCopMemInstruction()
1792 case ARM::t2LDC2L_POST: in DecodeCopMemInstruction()
1793 case ARM::t2STC2_POST: in DecodeCopMemInstruction()
1794 case ARM::t2STC2L_POST: in DecodeCopMemInstruction()
1795 case ARM::LDC2_POST: in DecodeCopMemInstruction()
1796 case ARM::LDC2L_POST: in DecodeCopMemInstruction()
1797 case ARM::STC2_POST: in DecodeCopMemInstruction()
1798 case ARM::STC2L_POST: in DecodeCopMemInstruction()
1799 case ARM::t2LDC_POST: in DecodeCopMemInstruction()
1800 case ARM::t2LDCL_POST: in DecodeCopMemInstruction()
1801 case ARM::t2STC_POST: in DecodeCopMemInstruction()
1802 case ARM::t2STCL_POST: in DecodeCopMemInstruction()
1803 case ARM::LDC_POST: in DecodeCopMemInstruction()
1804 case ARM::LDCL_POST: in DecodeCopMemInstruction()
1805 case ARM::STC_POST: in DecodeCopMemInstruction()
1806 case ARM::STCL_POST: in DecodeCopMemInstruction()
1817 case ARM::LDC_OFFSET: in DecodeCopMemInstruction()
1818 case ARM::LDC_PRE: in DecodeCopMemInstruction()
1819 case ARM::LDC_POST: in DecodeCopMemInstruction()
1820 case ARM::LDC_OPTION: in DecodeCopMemInstruction()
1821 case ARM::LDCL_OFFSET: in DecodeCopMemInstruction()
1822 case ARM::LDCL_PRE: in DecodeCopMemInstruction()
1823 case ARM::LDCL_POST: in DecodeCopMemInstruction()
1824 case ARM::LDCL_OPTION: in DecodeCopMemInstruction()
1825 case ARM::STC_OFFSET: in DecodeCopMemInstruction()
1826 case ARM::STC_PRE: in DecodeCopMemInstruction()
1827 case ARM::STC_POST: in DecodeCopMemInstruction()
1828 case ARM::STC_OPTION: in DecodeCopMemInstruction()
1829 case ARM::STCL_OFFSET: in DecodeCopMemInstruction()
1830 case ARM::STCL_PRE: in DecodeCopMemInstruction()
1831 case ARM::STCL_POST: in DecodeCopMemInstruction()
1832 case ARM::STCL_OPTION: in DecodeCopMemInstruction()
1859 case ARM::STR_POST_IMM: in DecodeAddrMode2IdxInstruction()
1860 case ARM::STR_POST_REG: in DecodeAddrMode2IdxInstruction()
1861 case ARM::STRB_POST_IMM: in DecodeAddrMode2IdxInstruction()
1862 case ARM::STRB_POST_REG: in DecodeAddrMode2IdxInstruction()
1863 case ARM::STRT_POST_REG: in DecodeAddrMode2IdxInstruction()
1864 case ARM::STRT_POST_IMM: in DecodeAddrMode2IdxInstruction()
1865 case ARM::STRBT_POST_REG: in DecodeAddrMode2IdxInstruction()
1866 case ARM::STRBT_POST_IMM: in DecodeAddrMode2IdxInstruction()
1879 case ARM::LDR_POST_IMM: in DecodeAddrMode2IdxInstruction()
1880 case ARM::LDR_POST_REG: in DecodeAddrMode2IdxInstruction()
1881 case ARM::LDRB_POST_IMM: in DecodeAddrMode2IdxInstruction()
1882 case ARM::LDRB_POST_REG: in DecodeAddrMode2IdxInstruction()
1883 case ARM::LDRBT_POST_REG: in DecodeAddrMode2IdxInstruction()
1884 case ARM::LDRBT_POST_IMM: in DecodeAddrMode2IdxInstruction()
1885 case ARM::LDRT_POST_REG: in DecodeAddrMode2IdxInstruction()
1886 case ARM::LDRT_POST_IMM: in DecodeAddrMode2IdxInstruction()
2012 case ARM::STRD: in DecodeAddrMode3Instruction()
2013 case ARM::STRD_PRE: in DecodeAddrMode3Instruction()
2014 case ARM::STRD_POST: in DecodeAddrMode3Instruction()
2015 case ARM::LDRD: in DecodeAddrMode3Instruction()
2016 case ARM::LDRD_PRE: in DecodeAddrMode3Instruction()
2017 case ARM::LDRD_POST: in DecodeAddrMode3Instruction()
2024 case ARM::STRD: in DecodeAddrMode3Instruction()
2025 case ARM::STRD_PRE: in DecodeAddrMode3Instruction()
2026 case ARM::STRD_POST: in DecodeAddrMode3Instruction()
2039 case ARM::STRH: in DecodeAddrMode3Instruction()
2040 case ARM::STRH_PRE: in DecodeAddrMode3Instruction()
2041 case ARM::STRH_POST: in DecodeAddrMode3Instruction()
2049 case ARM::LDRD: in DecodeAddrMode3Instruction()
2050 case ARM::LDRD_PRE: in DecodeAddrMode3Instruction()
2051 case ARM::LDRD_POST: in DecodeAddrMode3Instruction()
2066 case ARM::LDRH: in DecodeAddrMode3Instruction()
2067 case ARM::LDRH_PRE: in DecodeAddrMode3Instruction()
2068 case ARM::LDRH_POST: in DecodeAddrMode3Instruction()
2081 case ARM::LDRSH: in DecodeAddrMode3Instruction()
2082 case ARM::LDRSH_PRE: in DecodeAddrMode3Instruction()
2083 case ARM::LDRSH_POST: in DecodeAddrMode3Instruction()
2084 case ARM::LDRSB: in DecodeAddrMode3Instruction()
2085 case ARM::LDRSB_PRE: in DecodeAddrMode3Instruction()
2086 case ARM::LDRSB_POST: in DecodeAddrMode3Instruction()
2111 case ARM::STRD: in DecodeAddrMode3Instruction()
2112 case ARM::STRD_PRE: in DecodeAddrMode3Instruction()
2113 case ARM::STRD_POST: in DecodeAddrMode3Instruction()
2114 case ARM::STRH: in DecodeAddrMode3Instruction()
2115 case ARM::STRH_PRE: in DecodeAddrMode3Instruction()
2116 case ARM::STRH_POST: in DecodeAddrMode3Instruction()
2128 case ARM::STRD: in DecodeAddrMode3Instruction()
2129 case ARM::STRD_PRE: in DecodeAddrMode3Instruction()
2130 case ARM::STRD_POST: in DecodeAddrMode3Instruction()
2131 case ARM::LDRD: in DecodeAddrMode3Instruction()
2132 case ARM::LDRD_PRE: in DecodeAddrMode3Instruction()
2133 case ARM::LDRD_POST: in DecodeAddrMode3Instruction()
2144 case ARM::LDRD: in DecodeAddrMode3Instruction()
2145 case ARM::LDRD_PRE: in DecodeAddrMode3Instruction()
2146 case ARM::LDRD_POST: in DecodeAddrMode3Instruction()
2147 case ARM::LDRH: in DecodeAddrMode3Instruction()
2148 case ARM::LDRH_PRE: in DecodeAddrMode3Instruction()
2149 case ARM::LDRH_POST: in DecodeAddrMode3Instruction()
2150 case ARM::LDRSH: in DecodeAddrMode3Instruction()
2151 case ARM::LDRSH_PRE: in DecodeAddrMode3Instruction()
2152 case ARM::LDRSH_POST: in DecodeAddrMode3Instruction()
2153 case ARM::LDRSB: in DecodeAddrMode3Instruction()
2154 case ARM::LDRSB_PRE: in DecodeAddrMode3Instruction()
2155 case ARM::LDRSB_POST: in DecodeAddrMode3Instruction()
2156 case ARM::LDRHTr: in DecodeAddrMode3Instruction()
2157 case ARM::LDRSBTr: in DecodeAddrMode3Instruction()
2248 case ARM::LDMDA: in DecodeMemMultipleWritebackInstruction()
2249 Inst.setOpcode(ARM::RFEDA); in DecodeMemMultipleWritebackInstruction()
2251 case ARM::LDMDA_UPD: in DecodeMemMultipleWritebackInstruction()
2252 Inst.setOpcode(ARM::RFEDA_UPD); in DecodeMemMultipleWritebackInstruction()
2254 case ARM::LDMDB: in DecodeMemMultipleWritebackInstruction()
2255 Inst.setOpcode(ARM::RFEDB); in DecodeMemMultipleWritebackInstruction()
2257 case ARM::LDMDB_UPD: in DecodeMemMultipleWritebackInstruction()
2258 Inst.setOpcode(ARM::RFEDB_UPD); in DecodeMemMultipleWritebackInstruction()
2260 case ARM::LDMIA: in DecodeMemMultipleWritebackInstruction()
2261 Inst.setOpcode(ARM::RFEIA); in DecodeMemMultipleWritebackInstruction()
2263 case ARM::LDMIA_UPD: in DecodeMemMultipleWritebackInstruction()
2264 Inst.setOpcode(ARM::RFEIA_UPD); in DecodeMemMultipleWritebackInstruction()
2266 case ARM::LDMIB: in DecodeMemMultipleWritebackInstruction()
2267 Inst.setOpcode(ARM::RFEIB); in DecodeMemMultipleWritebackInstruction()
2269 case ARM::LDMIB_UPD: in DecodeMemMultipleWritebackInstruction()
2270 Inst.setOpcode(ARM::RFEIB_UPD); in DecodeMemMultipleWritebackInstruction()
2272 case ARM::STMDA: in DecodeMemMultipleWritebackInstruction()
2273 Inst.setOpcode(ARM::SRSDA); in DecodeMemMultipleWritebackInstruction()
2275 case ARM::STMDA_UPD: in DecodeMemMultipleWritebackInstruction()
2276 Inst.setOpcode(ARM::SRSDA_UPD); in DecodeMemMultipleWritebackInstruction()
2278 case ARM::STMDB: in DecodeMemMultipleWritebackInstruction()
2279 Inst.setOpcode(ARM::SRSDB); in DecodeMemMultipleWritebackInstruction()
2281 case ARM::STMDB_UPD: in DecodeMemMultipleWritebackInstruction()
2282 Inst.setOpcode(ARM::SRSDB_UPD); in DecodeMemMultipleWritebackInstruction()
2284 case ARM::STMIA: in DecodeMemMultipleWritebackInstruction()
2285 Inst.setOpcode(ARM::SRSIA); in DecodeMemMultipleWritebackInstruction()
2287 case ARM::STMIA_UPD: in DecodeMemMultipleWritebackInstruction()
2288 Inst.setOpcode(ARM::SRSIA_UPD); in DecodeMemMultipleWritebackInstruction()
2290 case ARM::STMIB: in DecodeMemMultipleWritebackInstruction()
2291 Inst.setOpcode(ARM::SRSIB); in DecodeMemMultipleWritebackInstruction()
2293 case ARM::STMIB_UPD: in DecodeMemMultipleWritebackInstruction()
2294 Inst.setOpcode(ARM::SRSIB_UPD); in DecodeMemMultipleWritebackInstruction()
2344 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) in DecodeHINTInstruction()
2374 Inst.setOpcode(ARM::CPS3p); in DecodeCPSInstruction()
2379 Inst.setOpcode(ARM::CPS2p); in DecodeCPSInstruction()
2384 Inst.setOpcode(ARM::CPS1p); in DecodeCPSInstruction()
2389 Inst.setOpcode(ARM::CPS1p); in DecodeCPSInstruction()
2414 Inst.setOpcode(ARM::t2CPS3p); in DecodeT2CPSInstruction()
2419 Inst.setOpcode(ARM::t2CPS2p); in DecodeT2CPSInstruction()
2424 Inst.setOpcode(ARM::t2CPS1p); in DecodeT2CPSInstruction()
2432 Inst.setOpcode(ARM::t2HINT); in DecodeT2CPSInstruction()
2451 if (Inst.getOpcode() == ARM::t2MOVTi16) in DecodeT2MOVTWInstruction()
2474 if (Inst.getOpcode() == ARM::MOVTi16) in DecodeArmMOVTWInstruction()
2548 if (!FeatureBits[ARM::HasV8_1aOps] || in DecodeSETPANInstruction()
2549 !FeatureBits[ARM::HasV8Ops]) in DecodeSETPANInstruction()
2561 Inst.setOpcode(ARM::SETPAN); in DecodeSETPANInstruction()
2668 Inst.setOpcode(ARM::BLXi); in DecodeBranchImmInstruction()
2682 if (Inst.getOpcode() != ARM::BL) in DecodeBranchImmInstruction()
2719 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: in DecodeVLDInstruction()
2720 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: in DecodeVLDInstruction()
2721 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: in DecodeVLDInstruction()
2722 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: in DecodeVLDInstruction()
2723 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: in DecodeVLDInstruction()
2724 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: in DecodeVLDInstruction()
2725 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: in DecodeVLDInstruction()
2726 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: in DecodeVLDInstruction()
2727 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: in DecodeVLDInstruction()
2731 case ARM::VLD2b16: in DecodeVLDInstruction()
2732 case ARM::VLD2b32: in DecodeVLDInstruction()
2733 case ARM::VLD2b8: in DecodeVLDInstruction()
2734 case ARM::VLD2b16wb_fixed: in DecodeVLDInstruction()
2735 case ARM::VLD2b16wb_register: in DecodeVLDInstruction()
2736 case ARM::VLD2b32wb_fixed: in DecodeVLDInstruction()
2737 case ARM::VLD2b32wb_register: in DecodeVLDInstruction()
2738 case ARM::VLD2b8wb_fixed: in DecodeVLDInstruction()
2739 case ARM::VLD2b8wb_register: in DecodeVLDInstruction()
2750 case ARM::VLD3d8: in DecodeVLDInstruction()
2751 case ARM::VLD3d16: in DecodeVLDInstruction()
2752 case ARM::VLD3d32: in DecodeVLDInstruction()
2753 case ARM::VLD3d8_UPD: in DecodeVLDInstruction()
2754 case ARM::VLD3d16_UPD: in DecodeVLDInstruction()
2755 case ARM::VLD3d32_UPD: in DecodeVLDInstruction()
2756 case ARM::VLD4d8: in DecodeVLDInstruction()
2757 case ARM::VLD4d16: in DecodeVLDInstruction()
2758 case ARM::VLD4d32: in DecodeVLDInstruction()
2759 case ARM::VLD4d8_UPD: in DecodeVLDInstruction()
2760 case ARM::VLD4d16_UPD: in DecodeVLDInstruction()
2761 case ARM::VLD4d32_UPD: in DecodeVLDInstruction()
2765 case ARM::VLD3q8: in DecodeVLDInstruction()
2766 case ARM::VLD3q16: in DecodeVLDInstruction()
2767 case ARM::VLD3q32: in DecodeVLDInstruction()
2768 case ARM::VLD3q8_UPD: in DecodeVLDInstruction()
2769 case ARM::VLD3q16_UPD: in DecodeVLDInstruction()
2770 case ARM::VLD3q32_UPD: in DecodeVLDInstruction()
2771 case ARM::VLD4q8: in DecodeVLDInstruction()
2772 case ARM::VLD4q16: in DecodeVLDInstruction()
2773 case ARM::VLD4q32: in DecodeVLDInstruction()
2774 case ARM::VLD4q8_UPD: in DecodeVLDInstruction()
2775 case ARM::VLD4q16_UPD: in DecodeVLDInstruction()
2776 case ARM::VLD4q32_UPD: in DecodeVLDInstruction()
2786 case ARM::VLD3d8: in DecodeVLDInstruction()
2787 case ARM::VLD3d16: in DecodeVLDInstruction()
2788 case ARM::VLD3d32: in DecodeVLDInstruction()
2789 case ARM::VLD3d8_UPD: in DecodeVLDInstruction()
2790 case ARM::VLD3d16_UPD: in DecodeVLDInstruction()
2791 case ARM::VLD3d32_UPD: in DecodeVLDInstruction()
2792 case ARM::VLD4d8: in DecodeVLDInstruction()
2793 case ARM::VLD4d16: in DecodeVLDInstruction()
2794 case ARM::VLD4d32: in DecodeVLDInstruction()
2795 case ARM::VLD4d8_UPD: in DecodeVLDInstruction()
2796 case ARM::VLD4d16_UPD: in DecodeVLDInstruction()
2797 case ARM::VLD4d32_UPD: in DecodeVLDInstruction()
2801 case ARM::VLD3q8: in DecodeVLDInstruction()
2802 case ARM::VLD3q16: in DecodeVLDInstruction()
2803 case ARM::VLD3q32: in DecodeVLDInstruction()
2804 case ARM::VLD3q8_UPD: in DecodeVLDInstruction()
2805 case ARM::VLD3q16_UPD: in DecodeVLDInstruction()
2806 case ARM::VLD3q32_UPD: in DecodeVLDInstruction()
2807 case ARM::VLD4q8: in DecodeVLDInstruction()
2808 case ARM::VLD4q16: in DecodeVLDInstruction()
2809 case ARM::VLD4q32: in DecodeVLDInstruction()
2810 case ARM::VLD4q8_UPD: in DecodeVLDInstruction()
2811 case ARM::VLD4q16_UPD: in DecodeVLDInstruction()
2812 case ARM::VLD4q32_UPD: in DecodeVLDInstruction()
2822 case ARM::VLD4d8: in DecodeVLDInstruction()
2823 case ARM::VLD4d16: in DecodeVLDInstruction()
2824 case ARM::VLD4d32: in DecodeVLDInstruction()
2825 case ARM::VLD4d8_UPD: in DecodeVLDInstruction()
2826 case ARM::VLD4d16_UPD: in DecodeVLDInstruction()
2827 case ARM::VLD4d32_UPD: in DecodeVLDInstruction()
2831 case ARM::VLD4q8: in DecodeVLDInstruction()
2832 case ARM::VLD4q16: in DecodeVLDInstruction()
2833 case ARM::VLD4q32: in DecodeVLDInstruction()
2834 case ARM::VLD4q8_UPD: in DecodeVLDInstruction()
2835 case ARM::VLD4q16_UPD: in DecodeVLDInstruction()
2836 case ARM::VLD4q32_UPD: in DecodeVLDInstruction()
2846 case ARM::VLD1d8wb_fixed: in DecodeVLDInstruction()
2847 case ARM::VLD1d16wb_fixed: in DecodeVLDInstruction()
2848 case ARM::VLD1d32wb_fixed: in DecodeVLDInstruction()
2849 case ARM::VLD1d64wb_fixed: in DecodeVLDInstruction()
2850 case ARM::VLD1d8wb_register: in DecodeVLDInstruction()
2851 case ARM::VLD1d16wb_register: in DecodeVLDInstruction()
2852 case ARM::VLD1d32wb_register: in DecodeVLDInstruction()
2853 case ARM::VLD1d64wb_register: in DecodeVLDInstruction()
2854 case ARM::VLD1q8wb_fixed: in DecodeVLDInstruction()
2855 case ARM::VLD1q16wb_fixed: in DecodeVLDInstruction()
2856 case ARM::VLD1q32wb_fixed: in DecodeVLDInstruction()
2857 case ARM::VLD1q64wb_fixed: in DecodeVLDInstruction()
2858 case ARM::VLD1q8wb_register: in DecodeVLDInstruction()
2859 case ARM::VLD1q16wb_register: in DecodeVLDInstruction()
2860 case ARM::VLD1q32wb_register: in DecodeVLDInstruction()
2861 case ARM::VLD1q64wb_register: in DecodeVLDInstruction()
2862 case ARM::VLD1d8Twb_fixed: in DecodeVLDInstruction()
2863 case ARM::VLD1d8Twb_register: in DecodeVLDInstruction()
2864 case ARM::VLD1d16Twb_fixed: in DecodeVLDInstruction()
2865 case ARM::VLD1d16Twb_register: in DecodeVLDInstruction()
2866 case ARM::VLD1d32Twb_fixed: in DecodeVLDInstruction()
2867 case ARM::VLD1d32Twb_register: in DecodeVLDInstruction()
2868 case ARM::VLD1d64Twb_fixed: in DecodeVLDInstruction()
2869 case ARM::VLD1d64Twb_register: in DecodeVLDInstruction()
2870 case ARM::VLD1d8Qwb_fixed: in DecodeVLDInstruction()
2871 case ARM::VLD1d8Qwb_register: in DecodeVLDInstruction()
2872 case ARM::VLD1d16Qwb_fixed: in DecodeVLDInstruction()
2873 case ARM::VLD1d16Qwb_register: in DecodeVLDInstruction()
2874 case ARM::VLD1d32Qwb_fixed: in DecodeVLDInstruction()
2875 case ARM::VLD1d32Qwb_register: in DecodeVLDInstruction()
2876 case ARM::VLD1d64Qwb_fixed: in DecodeVLDInstruction()
2877 case ARM::VLD1d64Qwb_register: in DecodeVLDInstruction()
2878 case ARM::VLD2d8wb_fixed: in DecodeVLDInstruction()
2879 case ARM::VLD2d16wb_fixed: in DecodeVLDInstruction()
2880 case ARM::VLD2d32wb_fixed: in DecodeVLDInstruction()
2881 case ARM::VLD2q8wb_fixed: in DecodeVLDInstruction()
2882 case ARM::VLD2q16wb_fixed: in DecodeVLDInstruction()
2883 case ARM::VLD2q32wb_fixed: in DecodeVLDInstruction()
2884 case ARM::VLD2d8wb_register: in DecodeVLDInstruction()
2885 case ARM::VLD2d16wb_register: in DecodeVLDInstruction()
2886 case ARM::VLD2d32wb_register: in DecodeVLDInstruction()
2887 case ARM::VLD2q8wb_register: in DecodeVLDInstruction()
2888 case ARM::VLD2q16wb_register: in DecodeVLDInstruction()
2889 case ARM::VLD2q32wb_register: in DecodeVLDInstruction()
2890 case ARM::VLD2b8wb_fixed: in DecodeVLDInstruction()
2891 case ARM::VLD2b16wb_fixed: in DecodeVLDInstruction()
2892 case ARM::VLD2b32wb_fixed: in DecodeVLDInstruction()
2893 case ARM::VLD2b8wb_register: in DecodeVLDInstruction()
2894 case ARM::VLD2b16wb_register: in DecodeVLDInstruction()
2895 case ARM::VLD2b32wb_register: in DecodeVLDInstruction()
2898 case ARM::VLD3d8_UPD: in DecodeVLDInstruction()
2899 case ARM::VLD3d16_UPD: in DecodeVLDInstruction()
2900 case ARM::VLD3d32_UPD: in DecodeVLDInstruction()
2901 case ARM::VLD3q8_UPD: in DecodeVLDInstruction()
2902 case ARM::VLD3q16_UPD: in DecodeVLDInstruction()
2903 case ARM::VLD3q32_UPD: in DecodeVLDInstruction()
2904 case ARM::VLD4d8_UPD: in DecodeVLDInstruction()
2905 case ARM::VLD4d16_UPD: in DecodeVLDInstruction()
2906 case ARM::VLD4d32_UPD: in DecodeVLDInstruction()
2907 case ARM::VLD4q8_UPD: in DecodeVLDInstruction()
2908 case ARM::VLD4q16_UPD: in DecodeVLDInstruction()
2909 case ARM::VLD4q32_UPD: in DecodeVLDInstruction()
2936 case ARM::VLD1d8wb_fixed: in DecodeVLDInstruction()
2937 case ARM::VLD1d16wb_fixed: in DecodeVLDInstruction()
2938 case ARM::VLD1d32wb_fixed: in DecodeVLDInstruction()
2939 case ARM::VLD1d64wb_fixed: in DecodeVLDInstruction()
2940 case ARM::VLD1d8Twb_fixed: in DecodeVLDInstruction()
2941 case ARM::VLD1d16Twb_fixed: in DecodeVLDInstruction()
2942 case ARM::VLD1d32Twb_fixed: in DecodeVLDInstruction()
2943 case ARM::VLD1d64Twb_fixed: in DecodeVLDInstruction()
2944 case ARM::VLD1d8Qwb_fixed: in DecodeVLDInstruction()
2945 case ARM::VLD1d16Qwb_fixed: in DecodeVLDInstruction()
2946 case ARM::VLD1d32Qwb_fixed: in DecodeVLDInstruction()
2947 case ARM::VLD1d64Qwb_fixed: in DecodeVLDInstruction()
2948 case ARM::VLD1d8wb_register: in DecodeVLDInstruction()
2949 case ARM::VLD1d16wb_register: in DecodeVLDInstruction()
2950 case ARM::VLD1d32wb_register: in DecodeVLDInstruction()
2951 case ARM::VLD1d64wb_register: in DecodeVLDInstruction()
2952 case ARM::VLD1q8wb_fixed: in DecodeVLDInstruction()
2953 case ARM::VLD1q16wb_fixed: in DecodeVLDInstruction()
2954 case ARM::VLD1q32wb_fixed: in DecodeVLDInstruction()
2955 case ARM::VLD1q64wb_fixed: in DecodeVLDInstruction()
2956 case ARM::VLD1q8wb_register: in DecodeVLDInstruction()
2957 case ARM::VLD1q16wb_register: in DecodeVLDInstruction()
2958 case ARM::VLD1q32wb_register: in DecodeVLDInstruction()
2959 case ARM::VLD1q64wb_register: in DecodeVLDInstruction()
2967 case ARM::VLD2d8wb_fixed: in DecodeVLDInstruction()
2968 case ARM::VLD2d16wb_fixed: in DecodeVLDInstruction()
2969 case ARM::VLD2d32wb_fixed: in DecodeVLDInstruction()
2970 case ARM::VLD2b8wb_fixed: in DecodeVLDInstruction()
2971 case ARM::VLD2b16wb_fixed: in DecodeVLDInstruction()
2972 case ARM::VLD2b32wb_fixed: in DecodeVLDInstruction()
2973 case ARM::VLD2q8wb_fixed: in DecodeVLDInstruction()
2974 case ARM::VLD2q16wb_fixed: in DecodeVLDInstruction()
2975 case ARM::VLD2q32wb_fixed: in DecodeVLDInstruction()
3046 case ARM::VST1d8wb_fixed: in DecodeVSTInstruction()
3047 case ARM::VST1d16wb_fixed: in DecodeVSTInstruction()
3048 case ARM::VST1d32wb_fixed: in DecodeVSTInstruction()
3049 case ARM::VST1d64wb_fixed: in DecodeVSTInstruction()
3050 case ARM::VST1d8wb_register: in DecodeVSTInstruction()
3051 case ARM::VST1d16wb_register: in DecodeVSTInstruction()
3052 case ARM::VST1d32wb_register: in DecodeVSTInstruction()
3053 case ARM::VST1d64wb_register: in DecodeVSTInstruction()
3054 case ARM::VST1q8wb_fixed: in DecodeVSTInstruction()
3055 case ARM::VST1q16wb_fixed: in DecodeVSTInstruction()
3056 case ARM::VST1q32wb_fixed: in DecodeVSTInstruction()
3057 case ARM::VST1q64wb_fixed: in DecodeVSTInstruction()
3058 case ARM::VST1q8wb_register: in DecodeVSTInstruction()
3059 case ARM::VST1q16wb_register: in DecodeVSTInstruction()
3060 case ARM::VST1q32wb_register: in DecodeVSTInstruction()
3061 case ARM::VST1q64wb_register: in DecodeVSTInstruction()
3062 case ARM::VST1d8Twb_fixed: in DecodeVSTInstruction()
3063 case ARM::VST1d16Twb_fixed: in DecodeVSTInstruction()
3064 case ARM::VST1d32Twb_fixed: in DecodeVSTInstruction()
3065 case ARM::VST1d64Twb_fixed: in DecodeVSTInstruction()
3066 case ARM::VST1d8Twb_register: in DecodeVSTInstruction()
3067 case ARM::VST1d16Twb_register: in DecodeVSTInstruction()
3068 case ARM::VST1d32Twb_register: in DecodeVSTInstruction()
3069 case ARM::VST1d64Twb_register: in DecodeVSTInstruction()
3070 case ARM::VST1d8Qwb_fixed: in DecodeVSTInstruction()
3071 case ARM::VST1d16Qwb_fixed: in DecodeVSTInstruction()
3072 case ARM::VST1d32Qwb_fixed: in DecodeVSTInstruction()
3073 case ARM::VST1d64Qwb_fixed: in DecodeVSTInstruction()
3074 case ARM::VST1d8Qwb_register: in DecodeVSTInstruction()
3075 case ARM::VST1d16Qwb_register: in DecodeVSTInstruction()
3076 case ARM::VST1d32Qwb_register: in DecodeVSTInstruction()
3077 case ARM::VST1d64Qwb_register: in DecodeVSTInstruction()
3078 case ARM::VST2d8wb_fixed: in DecodeVSTInstruction()
3079 case ARM::VST2d16wb_fixed: in DecodeVSTInstruction()
3080 case ARM::VST2d32wb_fixed: in DecodeVSTInstruction()
3081 case ARM::VST2d8wb_register: in DecodeVSTInstruction()
3082 case ARM::VST2d16wb_register: in DecodeVSTInstruction()
3083 case ARM::VST2d32wb_register: in DecodeVSTInstruction()
3084 case ARM::VST2q8wb_fixed: in DecodeVSTInstruction()
3085 case ARM::VST2q16wb_fixed: in DecodeVSTInstruction()
3086 case ARM::VST2q32wb_fixed: in DecodeVSTInstruction()
3087 case ARM::VST2q8wb_register: in DecodeVSTInstruction()
3088 case ARM::VST2q16wb_register: in DecodeVSTInstruction()
3089 case ARM::VST2q32wb_register: in DecodeVSTInstruction()
3090 case ARM::VST2b8wb_fixed: in DecodeVSTInstruction()
3091 case ARM::VST2b16wb_fixed: in DecodeVSTInstruction()
3092 case ARM::VST2b32wb_fixed: in DecodeVSTInstruction()
3093 case ARM::VST2b8wb_register: in DecodeVSTInstruction()
3094 case ARM::VST2b16wb_register: in DecodeVSTInstruction()
3095 case ARM::VST2b32wb_register: in DecodeVSTInstruction()
3100 case ARM::VST3d8_UPD: in DecodeVSTInstruction()
3101 case ARM::VST3d16_UPD: in DecodeVSTInstruction()
3102 case ARM::VST3d32_UPD: in DecodeVSTInstruction()
3103 case ARM::VST3q8_UPD: in DecodeVSTInstruction()
3104 case ARM::VST3q16_UPD: in DecodeVSTInstruction()
3105 case ARM::VST3q32_UPD: in DecodeVSTInstruction()
3106 case ARM::VST4d8_UPD: in DecodeVSTInstruction()
3107 case ARM::VST4d16_UPD: in DecodeVSTInstruction()
3108 case ARM::VST4d32_UPD: in DecodeVSTInstruction()
3109 case ARM::VST4q8_UPD: in DecodeVSTInstruction()
3110 case ARM::VST4q16_UPD: in DecodeVSTInstruction()
3111 case ARM::VST4q32_UPD: in DecodeVSTInstruction()
3133 case ARM::VST1d8wb_fixed: in DecodeVSTInstruction()
3134 case ARM::VST1d16wb_fixed: in DecodeVSTInstruction()
3135 case ARM::VST1d32wb_fixed: in DecodeVSTInstruction()
3136 case ARM::VST1d64wb_fixed: in DecodeVSTInstruction()
3137 case ARM::VST1q8wb_fixed: in DecodeVSTInstruction()
3138 case ARM::VST1q16wb_fixed: in DecodeVSTInstruction()
3139 case ARM::VST1q32wb_fixed: in DecodeVSTInstruction()
3140 case ARM::VST1q64wb_fixed: in DecodeVSTInstruction()
3141 case ARM::VST1d8Twb_fixed: in DecodeVSTInstruction()
3142 case ARM::VST1d16Twb_fixed: in DecodeVSTInstruction()
3143 case ARM::VST1d32Twb_fixed: in DecodeVSTInstruction()
3144 case ARM::VST1d64Twb_fixed: in DecodeVSTInstruction()
3145 case ARM::VST1d8Qwb_fixed: in DecodeVSTInstruction()
3146 case ARM::VST1d16Qwb_fixed: in DecodeVSTInstruction()
3147 case ARM::VST1d32Qwb_fixed: in DecodeVSTInstruction()
3148 case ARM::VST1d64Qwb_fixed: in DecodeVSTInstruction()
3149 case ARM::VST2d8wb_fixed: in DecodeVSTInstruction()
3150 case ARM::VST2d16wb_fixed: in DecodeVSTInstruction()
3151 case ARM::VST2d32wb_fixed: in DecodeVSTInstruction()
3152 case ARM::VST2q8wb_fixed: in DecodeVSTInstruction()
3153 case ARM::VST2q16wb_fixed: in DecodeVSTInstruction()
3154 case ARM::VST2q32wb_fixed: in DecodeVSTInstruction()
3155 case ARM::VST2b8wb_fixed: in DecodeVSTInstruction()
3156 case ARM::VST2b16wb_fixed: in DecodeVSTInstruction()
3157 case ARM::VST2b32wb_fixed: in DecodeVSTInstruction()
3163 case ARM::VST1q16: in DecodeVSTInstruction()
3164 case ARM::VST1q32: in DecodeVSTInstruction()
3165 case ARM::VST1q64: in DecodeVSTInstruction()
3166 case ARM::VST1q8: in DecodeVSTInstruction()
3167 case ARM::VST1q16wb_fixed: in DecodeVSTInstruction()
3168 case ARM::VST1q16wb_register: in DecodeVSTInstruction()
3169 case ARM::VST1q32wb_fixed: in DecodeVSTInstruction()
3170 case ARM::VST1q32wb_register: in DecodeVSTInstruction()
3171 case ARM::VST1q64wb_fixed: in DecodeVSTInstruction()
3172 case ARM::VST1q64wb_register: in DecodeVSTInstruction()
3173 case ARM::VST1q8wb_fixed: in DecodeVSTInstruction()
3174 case ARM::VST1q8wb_register: in DecodeVSTInstruction()
3175 case ARM::VST2d16: in DecodeVSTInstruction()
3176 case ARM::VST2d32: in DecodeVSTInstruction()
3177 case ARM::VST2d8: in DecodeVSTInstruction()
3178 case ARM::VST2d16wb_fixed: in DecodeVSTInstruction()
3179 case ARM::VST2d16wb_register: in DecodeVSTInstruction()
3180 case ARM::VST2d32wb_fixed: in DecodeVSTInstruction()
3181 case ARM::VST2d32wb_register: in DecodeVSTInstruction()
3182 case ARM::VST2d8wb_fixed: in DecodeVSTInstruction()
3183 case ARM::VST2d8wb_register: in DecodeVSTInstruction()
3187 case ARM::VST2b16: in DecodeVSTInstruction()
3188 case ARM::VST2b32: in DecodeVSTInstruction()
3189 case ARM::VST2b8: in DecodeVSTInstruction()
3190 case ARM::VST2b16wb_fixed: in DecodeVSTInstruction()
3191 case ARM::VST2b16wb_register: in DecodeVSTInstruction()
3192 case ARM::VST2b32wb_fixed: in DecodeVSTInstruction()
3193 case ARM::VST2b32wb_register: in DecodeVSTInstruction()
3194 case ARM::VST2b8wb_fixed: in DecodeVSTInstruction()
3195 case ARM::VST2b8wb_register: in DecodeVSTInstruction()
3206 case ARM::VST3d8: in DecodeVSTInstruction()
3207 case ARM::VST3d16: in DecodeVSTInstruction()
3208 case ARM::VST3d32: in DecodeVSTInstruction()
3209 case ARM::VST3d8_UPD: in DecodeVSTInstruction()
3210 case ARM::VST3d16_UPD: in DecodeVSTInstruction()
3211 case ARM::VST3d32_UPD: in DecodeVSTInstruction()
3212 case ARM::VST4d8: in DecodeVSTInstruction()
3213 case ARM::VST4d16: in DecodeVSTInstruction()
3214 case ARM::VST4d32: in DecodeVSTInstruction()
3215 case ARM::VST4d8_UPD: in DecodeVSTInstruction()
3216 case ARM::VST4d16_UPD: in DecodeVSTInstruction()
3217 case ARM::VST4d32_UPD: in DecodeVSTInstruction()
3221 case ARM::VST3q8: in DecodeVSTInstruction()
3222 case ARM::VST3q16: in DecodeVSTInstruction()
3223 case ARM::VST3q32: in DecodeVSTInstruction()
3224 case ARM::VST3q8_UPD: in DecodeVSTInstruction()
3225 case ARM::VST3q16_UPD: in DecodeVSTInstruction()
3226 case ARM::VST3q32_UPD: in DecodeVSTInstruction()
3227 case ARM::VST4q8: in DecodeVSTInstruction()
3228 case ARM::VST4q16: in DecodeVSTInstruction()
3229 case ARM::VST4q32: in DecodeVSTInstruction()
3230 case ARM::VST4q8_UPD: in DecodeVSTInstruction()
3231 case ARM::VST4q16_UPD: in DecodeVSTInstruction()
3232 case ARM::VST4q32_UPD: in DecodeVSTInstruction()
3242 case ARM::VST3d8: in DecodeVSTInstruction()
3243 case ARM::VST3d16: in DecodeVSTInstruction()
3244 case ARM::VST3d32: in DecodeVSTInstruction()
3245 case ARM::VST3d8_UPD: in DecodeVSTInstruction()
3246 case ARM::VST3d16_UPD: in DecodeVSTInstruction()
3247 case ARM::VST3d32_UPD: in DecodeVSTInstruction()
3248 case ARM::VST4d8: in DecodeVSTInstruction()
3249 case ARM::VST4d16: in DecodeVSTInstruction()
3250 case ARM::VST4d32: in DecodeVSTInstruction()
3251 case ARM::VST4d8_UPD: in DecodeVSTInstruction()
3252 case ARM::VST4d16_UPD: in DecodeVSTInstruction()
3253 case ARM::VST4d32_UPD: in DecodeVSTInstruction()
3257 case ARM::VST3q8: in DecodeVSTInstruction()
3258 case ARM::VST3q16: in DecodeVSTInstruction()
3259 case ARM::VST3q32: in DecodeVSTInstruction()
3260 case ARM::VST3q8_UPD: in DecodeVSTInstruction()
3261 case ARM::VST3q16_UPD: in DecodeVSTInstruction()
3262 case ARM::VST3q32_UPD: in DecodeVSTInstruction()
3263 case ARM::VST4q8: in DecodeVSTInstruction()
3264 case ARM::VST4q16: in DecodeVSTInstruction()
3265 case ARM::VST4q32: in DecodeVSTInstruction()
3266 case ARM::VST4q8_UPD: in DecodeVSTInstruction()
3267 case ARM::VST4q16_UPD: in DecodeVSTInstruction()
3268 case ARM::VST4q32_UPD: in DecodeVSTInstruction()
3278 case ARM::VST4d8: in DecodeVSTInstruction()
3279 case ARM::VST4d16: in DecodeVSTInstruction()
3280 case ARM::VST4d32: in DecodeVSTInstruction()
3281 case ARM::VST4d8_UPD: in DecodeVSTInstruction()
3282 case ARM::VST4d16_UPD: in DecodeVSTInstruction()
3283 case ARM::VST4d32_UPD: in DecodeVSTInstruction()
3287 case ARM::VST4q8: in DecodeVSTInstruction()
3288 case ARM::VST4q16: in DecodeVSTInstruction()
3289 case ARM::VST4q32: in DecodeVSTInstruction()
3290 case ARM::VST4q8_UPD: in DecodeVSTInstruction()
3291 case ARM::VST4q16_UPD: in DecodeVSTInstruction()
3292 case ARM::VST4q32_UPD: in DecodeVSTInstruction()
3319 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: in DecodeVLD1DupInstruction()
3320 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: in DecodeVLD1DupInstruction()
3321 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: in DecodeVLD1DupInstruction()
3322 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: in DecodeVLD1DupInstruction()
3363 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: in DecodeVLD2DupInstruction()
3364 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: in DecodeVLD2DupInstruction()
3365 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: in DecodeVLD2DupInstruction()
3366 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: in DecodeVLD2DupInstruction()
3370 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: in DecodeVLD2DupInstruction()
3371 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: in DecodeVLD2DupInstruction()
3372 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: in DecodeVLD2DupInstruction()
3373 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: in DecodeVLD2DupInstruction()
3510 case ARM::VORRiv4i16: in DecodeVMOVModImmInstruction()
3511 case ARM::VORRiv2i32: in DecodeVMOVModImmInstruction()
3512 case ARM::VBICiv4i16: in DecodeVMOVModImmInstruction()
3513 case ARM::VBICiv2i32: in DecodeVMOVModImmInstruction()
3517 case ARM::VORRiv8i16: in DecodeVMOVModImmInstruction()
3518 case ARM::VORRiv4i32: in DecodeVMOVModImmInstruction()
3519 case ARM::VBICiv8i16: in DecodeVMOVModImmInstruction()
3520 case ARM::VBICiv4i32: in DecodeVMOVModImmInstruction()
3545 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32) in DecodeMVEModImmInstruction()
3568 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); in DecodeMVEVADCInstruction()
3579 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); in DecodeMVEVADCInstruction()
3648 case ARM::VTBL2: in DecodeTBLInstruction()
3649 case ARM::VTBX2: in DecodeTBLInstruction()
3677 case ARM::tADR: in DecodeThumbAddSpecialReg()
3679 case ARM::tADDrSPi: in DecodeThumbAddSpecialReg()
3680 Inst.addOperand(MCOperand::createReg(ARM::SP)); in DecodeThumbAddSpecialReg()
3753 Inst.addOperand(MCOperand::createReg(ARM::SP)); in DecodeThumbAddrModeSP()
3769 case ARM::t2STRHs: in DecodeT2AddrModeSOReg()
3770 case ARM::t2STRBs: in DecodeT2AddrModeSOReg()
3771 case ARM::t2STRs: in DecodeT2AddrModeSOReg()
3798 bool hasMP = featureBits[ARM::FeatureMP]; in DecodeT2LoadShift()
3799 bool hasV7Ops = featureBits[ARM::HasV7Ops]; in DecodeT2LoadShift()
3803 case ARM::t2LDRBs: in DecodeT2LoadShift()
3804 Inst.setOpcode(ARM::t2LDRBpci); in DecodeT2LoadShift()
3806 case ARM::t2LDRHs: in DecodeT2LoadShift()
3807 Inst.setOpcode(ARM::t2LDRHpci); in DecodeT2LoadShift()
3809 case ARM::t2LDRSHs: in DecodeT2LoadShift()
3810 Inst.setOpcode(ARM::t2LDRSHpci); in DecodeT2LoadShift()
3812 case ARM::t2LDRSBs: in DecodeT2LoadShift()
3813 Inst.setOpcode(ARM::t2LDRSBpci); in DecodeT2LoadShift()
3815 case ARM::t2LDRs: in DecodeT2LoadShift()
3816 Inst.setOpcode(ARM::t2LDRpci); in DecodeT2LoadShift()
3818 case ARM::t2PLDs: in DecodeT2LoadShift()
3819 Inst.setOpcode(ARM::t2PLDpci); in DecodeT2LoadShift()
3821 case ARM::t2PLIs: in DecodeT2LoadShift()
3822 Inst.setOpcode(ARM::t2PLIpci); in DecodeT2LoadShift()
3833 case ARM::t2LDRSHs: in DecodeT2LoadShift()
3835 case ARM::t2LDRHs: in DecodeT2LoadShift()
3836 Inst.setOpcode(ARM::t2PLDWs); in DecodeT2LoadShift()
3838 case ARM::t2LDRSBs: in DecodeT2LoadShift()
3839 Inst.setOpcode(ARM::t2PLIs); in DecodeT2LoadShift()
3847 case ARM::t2PLDs: in DecodeT2LoadShift()
3849 case ARM::t2PLIs: in DecodeT2LoadShift()
3853 case ARM::t2PLDWs: in DecodeT2LoadShift()
3886 bool hasMP = featureBits[ARM::FeatureMP]; in DecodeT2LoadImm8()
3887 bool hasV7Ops = featureBits[ARM::HasV7Ops]; in DecodeT2LoadImm8()
3891 case ARM::t2LDRi8: in DecodeT2LoadImm8()
3892 Inst.setOpcode(ARM::t2LDRpci); in DecodeT2LoadImm8()
3894 case ARM::t2LDRBi8: in DecodeT2LoadImm8()
3895 Inst.setOpcode(ARM::t2LDRBpci); in DecodeT2LoadImm8()
3897 case ARM::t2LDRSBi8: in DecodeT2LoadImm8()
3898 Inst.setOpcode(ARM::t2LDRSBpci); in DecodeT2LoadImm8()
3900 case ARM::t2LDRHi8: in DecodeT2LoadImm8()
3901 Inst.setOpcode(ARM::t2LDRHpci); in DecodeT2LoadImm8()
3903 case ARM::t2LDRSHi8: in DecodeT2LoadImm8()
3904 Inst.setOpcode(ARM::t2LDRSHpci); in DecodeT2LoadImm8()
3906 case ARM::t2PLDi8: in DecodeT2LoadImm8()
3907 Inst.setOpcode(ARM::t2PLDpci); in DecodeT2LoadImm8()
3909 case ARM::t2PLIi8: in DecodeT2LoadImm8()
3910 Inst.setOpcode(ARM::t2PLIpci); in DecodeT2LoadImm8()
3920 case ARM::t2LDRSHi8: in DecodeT2LoadImm8()
3922 case ARM::t2LDRHi8: in DecodeT2LoadImm8()
3924 Inst.setOpcode(ARM::t2PLDWi8); in DecodeT2LoadImm8()
3926 case ARM::t2LDRSBi8: in DecodeT2LoadImm8()
3927 Inst.setOpcode(ARM::t2PLIi8); in DecodeT2LoadImm8()
3935 case ARM::t2PLDi8: in DecodeT2LoadImm8()
3937 case ARM::t2PLIi8: in DecodeT2LoadImm8()
3941 case ARM::t2PLDWi8: in DecodeT2LoadImm8()
3967 bool hasMP = featureBits[ARM::FeatureMP]; in DecodeT2LoadImm12()
3968 bool hasV7Ops = featureBits[ARM::HasV7Ops]; in DecodeT2LoadImm12()
3972 case ARM::t2LDRi12: in DecodeT2LoadImm12()
3973 Inst.setOpcode(ARM::t2LDRpci); in DecodeT2LoadImm12()
3975 case ARM::t2LDRHi12: in DecodeT2LoadImm12()
3976 Inst.setOpcode(ARM::t2LDRHpci); in DecodeT2LoadImm12()
3978 case ARM::t2LDRSHi12: in DecodeT2LoadImm12()
3979 Inst.setOpcode(ARM::t2LDRSHpci); in DecodeT2LoadImm12()
3981 case ARM::t2LDRBi12: in DecodeT2LoadImm12()
3982 Inst.setOpcode(ARM::t2LDRBpci); in DecodeT2LoadImm12()
3984 case ARM::t2LDRSBi12: in DecodeT2LoadImm12()
3985 Inst.setOpcode(ARM::t2LDRSBpci); in DecodeT2LoadImm12()
3987 case ARM::t2PLDi12: in DecodeT2LoadImm12()
3988 Inst.setOpcode(ARM::t2PLDpci); in DecodeT2LoadImm12()
3990 case ARM::t2PLIi12: in DecodeT2LoadImm12()
3991 Inst.setOpcode(ARM::t2PLIpci); in DecodeT2LoadImm12()
4001 case ARM::t2LDRSHi12: in DecodeT2LoadImm12()
4003 case ARM::t2LDRHi12: in DecodeT2LoadImm12()
4004 Inst.setOpcode(ARM::t2PLDWi12); in DecodeT2LoadImm12()
4006 case ARM::t2LDRSBi12: in DecodeT2LoadImm12()
4007 Inst.setOpcode(ARM::t2PLIi12); in DecodeT2LoadImm12()
4015 case ARM::t2PLDi12: in DecodeT2LoadImm12()
4017 case ARM::t2PLIi12: in DecodeT2LoadImm12()
4021 case ARM::t2PLDWi12: in DecodeT2LoadImm12()
4046 case ARM::t2LDRT: in DecodeT2LoadT()
4047 Inst.setOpcode(ARM::t2LDRpci); in DecodeT2LoadT()
4049 case ARM::t2LDRBT: in DecodeT2LoadT()
4050 Inst.setOpcode(ARM::t2LDRBpci); in DecodeT2LoadT()
4052 case ARM::t2LDRHT: in DecodeT2LoadT()
4053 Inst.setOpcode(ARM::t2LDRHpci); in DecodeT2LoadT()
4055 case ARM::t2LDRSBT: in DecodeT2LoadT()
4056 Inst.setOpcode(ARM::t2LDRSBpci); in DecodeT2LoadT()
4058 case ARM::t2LDRSHT: in DecodeT2LoadT()
4059 Inst.setOpcode(ARM::t2LDRSHpci); in DecodeT2LoadT()
4085 bool hasV7Ops = featureBits[ARM::HasV7Ops]; in DecodeT2LoadLabel()
4089 case ARM::t2LDRBpci: in DecodeT2LoadLabel()
4090 case ARM::t2LDRHpci: in DecodeT2LoadLabel()
4091 Inst.setOpcode(ARM::t2PLDpci); in DecodeT2LoadLabel()
4093 case ARM::t2LDRSBpci: in DecodeT2LoadLabel()
4094 Inst.setOpcode(ARM::t2PLIpci); in DecodeT2LoadLabel()
4096 case ARM::t2LDRSHpci: in DecodeT2LoadLabel()
4104 case ARM::t2PLDpci: in DecodeT2LoadLabel()
4106 case ARM::t2PLIpci: in DecodeT2LoadLabel()
4238 case ARM::t2STRT: in DecodeT2AddrModeImm8()
4239 case ARM::t2STRBT: in DecodeT2AddrModeImm8()
4240 case ARM::t2STRHT: in DecodeT2AddrModeImm8()
4241 case ARM::t2STRi8: in DecodeT2AddrModeImm8()
4242 case ARM::t2STRHi8: in DecodeT2AddrModeImm8()
4243 case ARM::t2STRBi8: in DecodeT2AddrModeImm8()
4253 case ARM::t2LDRT: in DecodeT2AddrModeImm8()
4254 case ARM::t2LDRBT: in DecodeT2AddrModeImm8()
4255 case ARM::t2LDRHT: in DecodeT2AddrModeImm8()
4256 case ARM::t2LDRSBT: in DecodeT2AddrModeImm8()
4257 case ARM::t2LDRSHT: in DecodeT2AddrModeImm8()
4258 case ARM::t2STRT: in DecodeT2AddrModeImm8()
4259 case ARM::t2STRBT: in DecodeT2AddrModeImm8()
4260 case ARM::t2STRHT: in DecodeT2AddrModeImm8()
4324 case ARM::t2LDR_PRE: in DecodeT2LdStPre()
4325 case ARM::t2LDR_POST: in DecodeT2LdStPre()
4326 Inst.setOpcode(ARM::t2LDRpci); in DecodeT2LdStPre()
4328 case ARM::t2LDRB_PRE: in DecodeT2LdStPre()
4329 case ARM::t2LDRB_POST: in DecodeT2LdStPre()
4330 Inst.setOpcode(ARM::t2LDRBpci); in DecodeT2LdStPre()
4332 case ARM::t2LDRH_PRE: in DecodeT2LdStPre()
4333 case ARM::t2LDRH_POST: in DecodeT2LdStPre()
4334 Inst.setOpcode(ARM::t2LDRHpci); in DecodeT2LdStPre()
4336 case ARM::t2LDRSB_PRE: in DecodeT2LdStPre()
4337 case ARM::t2LDRSB_POST: in DecodeT2LdStPre()
4339 Inst.setOpcode(ARM::t2PLIpci); in DecodeT2LdStPre()
4341 Inst.setOpcode(ARM::t2LDRSBpci); in DecodeT2LdStPre()
4343 case ARM::t2LDRSH_PRE: in DecodeT2LdStPre()
4344 case ARM::t2LDRSH_POST: in DecodeT2LdStPre()
4345 Inst.setOpcode(ARM::t2LDRSHpci); in DecodeT2LdStPre()
4381 case ARM::t2STRi12: in DecodeT2AddrModeImm12()
4382 case ARM::t2STRBi12: in DecodeT2AddrModeImm12()
4383 case ARM::t2STRHi12: in DecodeT2AddrModeImm12()
4402 Inst.addOperand(MCOperand::createReg(ARM::SP)); in DecodeThumbAddSPImm()
4403 Inst.addOperand(MCOperand::createReg(ARM::SP)); in DecodeThumbAddSPImm()
4413 if (Inst.getOpcode() == ARM::tADDrSP) { in DecodeThumbAddSPReg()
4419 Inst.addOperand(MCOperand::createReg(ARM::SP)); in DecodeThumbAddSPReg()
4422 } else if (Inst.getOpcode() == ARM::tADDspr) { in DecodeThumbAddSPReg()
4425 Inst.addOperand(MCOperand::createReg(ARM::SP)); in DecodeThumbAddSPReg()
4426 Inst.addOperand(MCOperand::createReg(ARM::SP)); in DecodeThumbAddSPReg()
4544 if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail; in DecodeThumbTableBranch()
4564 Inst.setOpcode(ARM::t2DSB); in DecodeThumb2BCCInstruction()
4567 Inst.setOpcode(ARM::t2DMB); in DecodeThumb2BCCInstruction()
4570 Inst.setOpcode(ARM::t2ISB); in DecodeThumb2BCCInstruction()
4683 if (FeatureBits[ARM::FeatureMClass]) { in DecodeMSRMask()
4703 if (!(FeatureBits[ARM::HasV7Ops])) in DecodeMSRMask()
4711 if (!(FeatureBits[ARM::HasV8MMainlineOps])) in DecodeMSRMask()
4721 if (!(FeatureBits[ARM::Feature8MSecExt])) in DecodeMSRMask()
4730 if (Inst.getOpcode() == ARM::t2MSR_M) { in DecodeMSRMask()
4732 if (!(FeatureBits[ARM::HasV7Ops])) { in DecodeMSRMask()
4746 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) in DecodeMSRMask()
5641 Inst.setOpcode(ARM::t2SUBri12); in DecodeT2Adr()
5642 Inst.addOperand(MCOperand::createReg(ARM::PC)); in DecodeT2Adr()
5692 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; in DecodeVCVTD()
5708 Inst.setOpcode(ARM::VMOVv2f32); in DecodeVCVTD()
5713 Inst.setOpcode(ARM::VMOVv1i64); in DecodeVCVTD()
5715 Inst.setOpcode(ARM::VMOVv8i8); in DecodeVCVTD()
5720 Inst.setOpcode(ARM::VMVNv2i32); in DecodeVCVTD()
5722 Inst.setOpcode(ARM::VMOVv2i32); in DecodeVCVTD()
5727 Inst.setOpcode(ARM::VMVNv2i32); in DecodeVCVTD()
5729 Inst.setOpcode(ARM::VMOVv2i32); in DecodeVCVTD()
5751 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; in DecodeVCVTQ()
5767 Inst.setOpcode(ARM::VMOVv4f32); in DecodeVCVTQ()
5772 Inst.setOpcode(ARM::VMOVv2i64); in DecodeVCVTQ()
5774 Inst.setOpcode(ARM::VMOVv16i8); in DecodeVCVTQ()
5779 Inst.setOpcode(ARM::VMVNv4i32); in DecodeVCVTQ()
5781 Inst.setOpcode(ARM::VMOVv4i32); in DecodeVCVTQ()
5786 Inst.setOpcode(ARM::VMVNv4i32); in DecodeVCVTQ()
5788 Inst.setOpcode(ARM::VMOVv4i32); in DecodeVCVTQ()
5892 if (Inst.getOpcode() == ARM::MRRC2) { in DecoderForMRRC2AndMCRR2()
5900 if (Inst.getOpcode() == ARM::MCRR2) { in DecoderForMRRC2AndMCRR2()
5921 case ARM::VMSR_FPSCR_NZCVQC: in DecodeForVMRSandVMSR()
5922 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); in DecodeForVMRSandVMSR()
5924 case ARM::VMSR_P0: in DecodeForVMRSandVMSR()
5925 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeForVMRSandVMSR()
5929 if (Inst.getOpcode() != ARM::FMSTAT) { in DecodeForVMRSandVMSR()
5932 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { in DecodeForVMRSandVMSR()
5942 case ARM::VMRS_FPSCR_NZCVQC: in DecodeForVMRSandVMSR()
5943 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); in DecodeForVMRSandVMSR()
5945 case ARM::VMRS_P0: in DecodeForVMRSandVMSR()
5946 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeForVMRSandVMSR()
5950 if (featureBits[ARM::ModeThumb]) { in DecodeForVMRSandVMSR()
6007 if (Inst.getOpcode() == ARM::MVE_LCTP) in DecodeLOLoop()
6013 case ARM::t2LEUpdate: in DecodeLOLoop()
6014 case ARM::MVE_LETP: in DecodeLOLoop()
6015 Inst.addOperand(MCOperand::createReg(ARM::LR)); in DecodeLOLoop()
6016 Inst.addOperand(MCOperand::createReg(ARM::LR)); in DecodeLOLoop()
6018 case ARM::t2LE: in DecodeLOLoop()
6023 case ARM::t2WLS: in DecodeLOLoop()
6024 case ARM::MVE_WLSTP_8: in DecodeLOLoop()
6025 case ARM::MVE_WLSTP_16: in DecodeLOLoop()
6026 case ARM::MVE_WLSTP_32: in DecodeLOLoop()
6027 case ARM::MVE_WLSTP_64: in DecodeLOLoop()
6028 Inst.addOperand(MCOperand::createReg(ARM::LR)); in DecodeLOLoop()
6036 case ARM::t2DLS: in DecodeLOLoop()
6037 case ARM::MVE_DLSTP_8: in DecodeLOLoop()
6038 case ARM::MVE_DLSTP_16: in DecodeLOLoop()
6039 case ARM::MVE_DLSTP_32: in DecodeLOLoop()
6040 case ARM::MVE_DLSTP_64: in DecodeLOLoop()
6052 Inst.setOpcode(ARM::MVE_LCTP); in DecodeLOLoop()
6054 Inst.addOperand(MCOperand::createReg(ARM::LR)); in DecodeLOLoop()
6102 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); in DecodeGPRwithAPSR_NZCVnospRegisterClass()
6121 if (Inst.getOpcode() == ARM::VSCCLRMD) { in DecodeVSCCLRM()
6136 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeVSCCLRM()
6153 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4,
6154 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7
6169 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5,
6170 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7
6304 case ARM::MVE_VCVTf16s16_fix: in DecodeVCVTImmOperand()
6305 case ARM::MVE_VCVTs16f16_fix: in DecodeVCVTImmOperand()
6306 case ARM::MVE_VCVTf16u16_fix: in DecodeVCVTImmOperand()
6307 case ARM::MVE_VCVTu16f16_fix: in DecodeVCVTImmOperand()
6311 case ARM::MVE_VCVTf32s32_fix: in DecodeVCVTImmOperand()
6312 case ARM::MVE_VCVTs32f32_fix: in DecodeVCVTImmOperand()
6313 case ARM::MVE_VCVTf32u32_fix: in DecodeVCVTImmOperand()
6314 case ARM::MVE_VCVTu32f32_fix: in DecodeVCVTImmOperand()
6327 case ARM::VSTR_P0_off: in FixedRegForVSTRVLDR_SYSREG()
6328 case ARM::VSTR_P0_pre: in FixedRegForVSTRVLDR_SYSREG()
6329 case ARM::VSTR_P0_post: in FixedRegForVSTRVLDR_SYSREG()
6330 case ARM::VLDR_P0_off: in FixedRegForVSTRVLDR_SYSREG()
6331 case ARM::VLDR_P0_pre: in FixedRegForVSTRVLDR_SYSREG()
6332 case ARM::VLDR_P0_post: in FixedRegForVSTRVLDR_SYSREG()
6333 return ARM::P0; in FixedRegForVSTRVLDR_SYSREG()
6344 case ARM::VSTR_FPSCR_pre: in DecodeVSTRVLDR_SYSREG()
6345 case ARM::VSTR_FPSCR_NZCVQC_pre: in DecodeVSTRVLDR_SYSREG()
6346 case ARM::VLDR_FPSCR_pre: in DecodeVSTRVLDR_SYSREG()
6347 case ARM::VLDR_FPSCR_NZCVQC_pre: in DecodeVSTRVLDR_SYSREG()
6348 case ARM::VSTR_FPSCR_off: in DecodeVSTRVLDR_SYSREG()
6349 case ARM::VSTR_FPSCR_NZCVQC_off: in DecodeVSTRVLDR_SYSREG()
6350 case ARM::VLDR_FPSCR_off: in DecodeVSTRVLDR_SYSREG()
6351 case ARM::VLDR_FPSCR_NZCVQC_off: in DecodeVSTRVLDR_SYSREG()
6352 case ARM::VSTR_FPSCR_post: in DecodeVSTRVLDR_SYSREG()
6353 case ARM::VSTR_FPSCR_NZCVQC_post: in DecodeVSTRVLDR_SYSREG()
6354 case ARM::VLDR_FPSCR_post: in DecodeVSTRVLDR_SYSREG()
6355 case ARM::VLDR_FPSCR_NZCVQC_post: in DecodeVSTRVLDR_SYSREG()
6359 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2]) in DecodeVSTRVLDR_SYSREG()
6518 case ARM::MVE_ASRLr: in DecodeMVEOverlappingLongShift()
6519 case ARM::MVE_SQRSHRL: in DecodeMVEOverlappingLongShift()
6520 Inst.setOpcode(ARM::MVE_SQRSHR); in DecodeMVEOverlappingLongShift()
6522 case ARM::MVE_LSLLr: in DecodeMVEOverlappingLongShift()
6523 case ARM::MVE_UQRSHLL: in DecodeMVEOverlappingLongShift()
6524 Inst.setOpcode(ARM::MVE_UQRSHL); in DecodeMVEOverlappingLongShift()
6570 if (Inst.getOpcode() == ARM::MVE_SQRSHRL || in DecodeMVEOverlappingLongShift()
6571 Inst.getOpcode() == ARM::MVE_UQRSHLL) { in DecodeMVEOverlappingLongShift()
6603 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVCMP()
6640 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMveVCTP()
6650 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVPNOT()
6651 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVPNOT()
6676 Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12); in DecodeT2AddSubSPImm()
6679 Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm); in DecodeT2AddSubSPImm()