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Searched refs:TII (Results 1 – 25 of 375) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/
H A DWebAssemblyLowerBrUnless.cpp82 Def->setDesc(TII.get(NE_I32)); in runOnMachineFunction()
86 Def->setDesc(TII.get(EQ_I32)); in runOnMachineFunction()
90 Def->setDesc(TII.get(LE_S_I32)); in runOnMachineFunction()
94 Def->setDesc(TII.get(LT_S_I32)); in runOnMachineFunction()
98 Def->setDesc(TII.get(GE_S_I32)); in runOnMachineFunction()
122 Def->setDesc(TII.get(NE_I64)); in runOnMachineFunction()
126 Def->setDesc(TII.get(EQ_I64)); in runOnMachineFunction()
162 Def->setDesc(TII.get(NE_F32)); in runOnMachineFunction()
166 Def->setDesc(TII.get(EQ_F32)); in runOnMachineFunction()
170 Def->setDesc(TII.get(NE_F64)); in runOnMachineFunction()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DShadowCallStack.cpp95 BuildMI(MBB, MBBI, DL, TII->get(X86::XOR64rr)) in addProlog()
127 BuildMI(MBB, MI, DL, TII->get(X86::XOR64rr)) in addEpilog()
146 BuildMI(MBB, MI, DL, TII->get(X86::JNE_1)).addMBB(&TrapBB); in addEpilog()
159 BuildMI(MBB, MI, DL, TII->get(X86::JNE_1)).addMBB(&TrapBB); in addEpilogLeaf()
168 BuildMI(MBB, MI, DL, TII->get(X86::XOR64rr)) in addEpilogOnlyR10()
186 BuildMI(MBB, MI, DL, TII->get(X86::JNE_1)).addMBB(&TrapBB); in addEpilogOnlyR10()
288 addPrologLeaf(Fn, TII, MBB, DL, LeafFuncRegister); in runOnMachineFunction()
290 addProlog(Fn, TII, MBB, DL); in runOnMachineFunction()
301 BuildMI(Trap, MI.getDebugLoc(), TII->get(X86::TRAP)); in runOnMachineFunction()
308 addEpilogOnlyR10(TII, MBB, MI, *Trap); in runOnMachineFunction()
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/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIShrinkInstructions.cpp72 assert(TII->isVOP1(MI) || TII->isVOP2(MI) || TII->isVOPC(MI)); in foldImmediates()
111 if (TII->commuteInstruction(MI)) { in foldImmediates()
116 TII->commuteInstruction(MI); in foldImmediates()
140 return !TII->isInlineConstant(Src); in isKImmOrKUImmOperand()
145 return !TII->isInlineConstant(Src); in isKImmOrKUImmOperand()
201 MI.setDesc(TII->get(SOPKOpc)); in shrinkScalarCompare()
209 if ((TII->sopkIsZext(SOPKOpc) && isKUImmOperand(TII, Src1)) || in shrinkScalarCompare()
210 (!TII->sopkIsZext(SOPKOpc) && isKImmOperand(TII, Src1))) { in shrinkScalarCompare()
276 MI.setDesc(TII->get(Opc)); in shrinkScalarLogicOp()
568 shrinkScalarCompare(TII, MI); in runOnMachineFunction()
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H A DR600ExpandSpecialInstrs.cpp42 const R600InstrInfo *TII = nullptr; member in __anon85c7d8840111::R600ExpandSpecialInstrsPass
76 int OpIdx = TII->getOperandIdx(*OldMI, Op); in SetFlagInNewMI()
79 TII->setImmOperand(*NewMI, Op, Val); in SetFlagInNewMI()
85 TII = ST.getInstrInfo(); in runOnMachineFunction()
98 if (TII->isLDSRetInstr(MI.getOpcode())) { in runOnMachineFunction()
126 TII->addFlag(*PredSet, 0, MO_FLAG_MASK); in runOnMachineFunction()
152 TII->addFlag(*BMI, 0, MO_FLAG_MASK); in runOnMachineFunction()
155 TII->addFlag(*BMI, 0, MO_FLAG_NOT_LAST); in runOnMachineFunction()
177 bool IsVector = TII->isVector(MI); in runOnMachineFunction()
178 bool IsCube = TII->isCubeOp(MI.getOpcode()); in runOnMachineFunction()
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H A DSIPeepholeSDWA.cpp75 const SIInstrInfo *TII; member in __anon536d3cb50111::SIPeepholeSDWA
436 SrcMods->setImm(getSrcMods(TII, Src)); in convertToSDWA()
532 if (!TII->isFoldableCopy(*DefInst)) in foldToImm()
736 if (!TII->isSDWA(*Op1Inst)) in matchSDWAOperand()
786 if (!TII->isSDWA(*OtherInst)) in matchSDWAOperand()
884 if (!TII->canShrink(MI, *MRI)) in pseudoOpConvertToVOP2()
896 if (!TII->canShrink(MISucc, *MRI)) in pseudoOpConvertToVOP2()
938 if (TII->isSDWA(Opc)) in isConvertibleToSDWA()
951 if (TII->isVOPC(Opc)) { in isConvertibleToSDWA()
987 if (TII->isSDWA(Opcode)) { in convertToSDWA()
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H A DGCNHazardRecognizer.cpp44 TII(*ST.getInstrInfo()), in GCNHazardRecognizer()
45 TRI(TII.getRegisterInfo()), in GCNHazardRecognizer()
107 if (TII.isDS(MI.getOpcode())) { in isSendMsgTraceDataOrGDS()
337 bool IsSMRD = TII.isSMRD(*MEM); in checkSoftClauseHazards()
452 auto IsHazardDefFn = [TII] (MachineInstr *MI) { return TII->isVALU(*MI); }; in checkDPPHazards()
475 auto IsHazardDefFn = [TII] (MachineInstr *MI) { return TII->isVALU(*MI); }; in checkDivFMasHazards()
520 if (TII->isMUBUF(MI) || TII->isMTBUF(MI)) { in createsVALUHazard()
540 if (TII->isMIMG(MI)) { in createsVALUHazard()
547 if (TII->isFLAT(MI)) { in createsVALUHazard()
635 return TII->isVALU(*MI); in checkRWLaneHazards()
[all …]
H A DSIFoldOperands.cpp88 const SIInstrInfo *TII; member in __anon5a94fe150111::SIFoldOperands
299 MI->setDesc(TII->get(NewOpc)); in tryAddToFoldList()
305 MI->setDesc(TII->get(Opc)); in tryAddToFoldList()
404 if (!isUseSafeToFold(TII, *UseMI, UseOp)) in foldOperand()
486 UseMI->setDesc(TII->get(MovOp)); in foldOperand()
898 tryFoldInst(TII, Fold.UseMI); in foldInstOperand()
970 if (TII->getClampMask(*Def) != TII->getClampMask(MI)) in tryFoldClamp()
1115 TII = ST->getInstrInfo(); in runOnMachineFunction()
1116 TRI = &TII->getRegisterInfo(); in runOnMachineFunction()
1132 tryFoldInst(TII, &MI); in runOnMachineFunction()
[all …]
H A DR600Packetizer.cpp58 const R600InstrInfo *TII; member in __anon03439b720111::R600PacketizerList
85 if (TII->isPredicated(*BI)) in getPreviousVector()
151 TII(ST.getInstrInfo()), in R600PacketizerList()
152 TRI(TII->getRegisterInfo()) { in R600PacketizerList()
170 if (TII->isVector(MI)) in isSoloInstruction()
172 if (!TII->isALUInstr(MI.getOpcode())) in isSoloInstruction()
178 return TII->isLDSInstr(MI.getOpcode()); in isSoloInstruction()
209 TII->definesAddressRegister(*MII) || TII->definesAddressRegister(*MIJ); in isLegalToPacketizeTogether()
211 TII->usesAddressRegister(*MII) || TII->usesAddressRegister(*MIJ); in isLegalToPacketizeTogether()
231 isTransSlot = TII->isTransOnly(MI); in isBundlableWithCurrentPMI()
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H A DGCNDPPCombine.cpp64 const SIInstrInfo *TII; member in __anon2a1f81510111::GCNDPPCombine
170 OrigMI.getDebugLoc(), TII->get(DPPOp)); in createDPPInst()
173 auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst); in createDPPInst()
186 if (auto *Mod0 = TII->getNamedOperand(OrigMI, in createDPPInst()
204 if (auto *Mod1 = TII->getNamedOperand(OrigMI, in createDPPInst()
309 auto *Imm = TII->getNamedOperand(MI, OpndName); in hasNoImmOrEqual()
371 if (TII->isVOP3(OrigOp)) { in combineDPPMov()
372 if (!TII->hasVALU32BitEncoding(OrigOp)) { in combineDPPMov()
385 } else if (!TII->isVOP1(OrigOp) && !TII->isVOP2(OrigOp)) { in combineDPPMov()
402 if (TII->commuteInstruction(*NewMI)) { in combineDPPMov()
[all …]
H A DSIFrameLowering.cpp41 const SIInstrInfo *TII = ST.getInstrInfo(); in emitFlatScratchInit() local
102 const SIInstrInfo *TII, in getReservedPrivateSegmentBufferReg() argument
153 const SIInstrInfo *TII, in getReservedPrivateSegmentWaveByteOffsetReg() argument
237 const SIInstrInfo *TII = ST.getInstrInfo(); in emitEntryFunctionPrologue() local
372 const SIInstrInfo *TII = ST.getInstrInfo(); in emitEntryFunctionScratchSetup() local
541 const SIInstrInfo *TII = ST.getInstrInfo(); in emitPrologue() local
611 const SIInstrInfo *TII = ST.getInstrInfo(); in emitEpilogue() local
672 const SIInstrInfo *TII = ST.getInstrInfo(); in processFunctionBeforeFrameFinalized() local
694 if (TII->isSGPRSpill(MI)) { in processFunctionBeforeFrameFinalized()
754 const SIInstrInfo *TII = ST.getInstrInfo(); in eliminateCallFramePseudoInstr() local
[all …]
H A DSIModeRegister.cpp154 const SIInstrInfo *TII, Status InstrMode);
173 if (TII->usesFPDPRounding(MI)) { in getInstructionMode()
199 BuildMI(MBB, MI, 0, TII->get(AMDGPU::S_SETREG_IMM32_B32)) in insertSetreg()
229 const SIInstrInfo *TII) { in processBlockPhase1() argument
240 Status InstrMode = getInstructionMode(MI, TII); in processBlockPhase1()
293 insertSetreg(MBB, InsertionPoint, TII, in processBlockPhase1()
372 insertSetreg(MBB, &MBB.instr_front(), TII, Delta); in processBlockPhase3()
379 const SIInstrInfo *TII = ST.getInstrInfo(); in runOnMachineFunction() local
386 processBlockPhase1(BB, TII); in runOnMachineFunction()
394 processBlockPhase2(*Phase2List.front(), TII); in runOnMachineFunction()
[all …]
H A DSIAddIMGInit.cpp66 const SIInstrInfo *TII = ST.getInstrInfo(); in runOnMachineFunction() local
79 if (TII->isMIMG(Opcode) && !MI.mayStore()) { in runOnMachineFunction()
80 MachineOperand *TFE = TII->getNamedOperand(MI, AMDGPU::OpName::tfe); in runOnMachineFunction()
81 MachineOperand *LWE = TII->getNamedOperand(MI, AMDGPU::OpName::lwe); in runOnMachineFunction()
82 MachineOperand *D16 = TII->getNamedOperand(MI, AMDGPU::OpName::d16); in runOnMachineFunction()
104 TII->getNamedOperand(MI, AMDGPU::OpName::dmask); in runOnMachineFunction()
113 TII->isGather4(Opcode) ? 4 : countPopulation(dmask); in runOnMachineFunction()
128 RI->getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32; in runOnMachineFunction()
134 MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx)); in runOnMachineFunction()
145 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), PrevDst) in runOnMachineFunction()
[all …]
H A DR600EmitClauseMarkers.cpp50 const R600InstrInfo *TII = nullptr; member in __anon95bc98210111::R600EmitClauseMarkers
68 if (TII->isLDSRetInstr(MI.getOpcode())) in OccupiedDwords()
71 if (TII->isVector(MI) || TII->isCubeOp(MI.getOpcode()) || in OccupiedDwords()
72 TII->isReductionOp(MI.getOpcode())) in OccupiedDwords()
87 if (TII->isALUInstr(MI.getOpcode())) in isALU()
89 if (TII->isVector(MI) || TII->isCubeOp(MI.getOpcode())) in isALU()
139 TII->getSrcs(MI); in SubstituteKCacheBank()
220 if (AluInstCount >= TII->getMaxAlusPerClause()) in canClauseLocalKillFitInClause()
254 if (AluInstCount > TII->getMaxAlusPerClause()) in MakeALUClause()
277 if (TII->mustBeLastInClause(I->getOpcode())) { in MakeALUClause()
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/freebsd-12.1/contrib/llvm/lib/Target/RISCV/
H A DRISCVExpandPseudoInsts.cpp32 const RISCVInstrInfo *TII; member in __anond5e49cc90111::RISCVExpandPseudo
190 BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)) in doAtomicBinOpExpansion()
213 BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg) in insertMaskedMerge()
275 BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)) in doMaskedAtomicBinOpExpansion()
322 BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg) in insertSext()
325 BuildMI(MBB, DL, TII->get(RISCV::SRA), ValReg) in insertSext()
393 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE)) in expandAtomicMinMaxOp()
401 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE)) in expandAtomicMinMaxOp()
434 BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE)) in expandAtomicMinMaxOp()
490 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BNE)) in expandAtomicCmpXchg()
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/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DPseudoSourceValue.cpp30 AddressSpace = TII.getAddressSpaceForPseudoSourceKind(Kind); in PseudoSourceValue()
84 unsigned Kind, const TargetInstrInfo &TII) in CallEntryPseudoSourceValue() argument
85 : PseudoSourceValue(Kind, TII) {} in CallEntryPseudoSourceValue()
101 const TargetInstrInfo &TII) in GlobalValuePseudoSourceValue() argument
104 const char *ES, const TargetInstrInfo &TII) in ExternalSymbolPseudoSourceValue() argument
109 : TII(TIInfo), in PseudoSourceValueManager()
110 StackPSV(PseudoSourceValue::Stack, TII), in PseudoSourceValueManager()
111 GOTPSV(PseudoSourceValue::GOT, TII), in PseudoSourceValueManager()
112 JumpTablePSV(PseudoSourceValue::JumpTable, TII), in PseudoSourceValueManager()
113 ConstantPoolPSV(PseudoSourceValue::ConstantPool, TII) {} in PseudoSourceValueManager()
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H A DXRayInstrumentation.cpp70 const TargetInstrInfo *TII,
89 MachineFunction &MF, const TargetInstrInfo *TII, in replaceRetWithPatchableRet() argument
103 if (TII->isTailCall(T) && op.HandleTailcall) { in replaceRetWithPatchableRet()
123 MachineFunction &MF, const TargetInstrInfo *TII, in prependRetWithPatchableExit() argument
132 if (TII->isTailCall(T) && op.HandleTailcall) { in prependRetWithPatchableExit()
138 BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc)); in prependRetWithPatchableExit()
192 auto *TII = MF.getSubtarget().getInstrInfo(); in runOnMachineFunction() local
205 TII->get(TargetOpcode::PATCHABLE_FUNCTION_ENTER)); in runOnMachineFunction()
219 prependRetWithPatchableExit(MF, TII, op); in runOnMachineFunction()
227 replaceRetWithPatchableRet(MF, TII, op); in runOnMachineFunction()
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/freebsd-12.1/contrib/llvm/lib/Target/AVR/
H A DAVRFrameLowering.cpp59 const AVRInstrInfo &TII = *STI.getInstrInfo(); in emitPrologue() local
64 BuildMI(MBB, MBBI, DL, TII.get(AVR::BSETs)) in emitPrologue()
71 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHWRr)) in emitPrologue()
80 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHWRr)) in emitPrologue()
87 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr)) in emitPrologue()
90 BuildMI(MBB, MBBI, DL, TII.get(AVR::EORRdRr)) in emitPrologue()
265 BuildMI(MBB, MI, DL, TII.get(AVR::PUSHRr)) in spillCalleeSavedRegisters()
354 MI.setDesc(TII.get(STOpc)); in fixStackStores()
372 fixStackStores(MBB, MI, TII, false); in eliminateCallFramePseudoInstr()
378 int Amount = TII.getFrameSize(*MI); in eliminateCallFramePseudoInstr()
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/freebsd-12.1/contrib/llvm/lib/Target/MSP430/
H A DMSP430FrameLowering.cpp46 const MSP430InstrInfo &TII = in emitPrologue() local
67 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r)) in emitPrologue()
71 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FP) in emitPrologue()
111 const MSP430InstrInfo &TII = in emitEpilogue() local
162 TII.get(MSP430::SUB16ri), MSP430::SP) in emitEpilogue()
200 BuildMI(MBB, MI, DL, TII.get(MSP430::PUSH16r)) in spillCalleeSavedRegisters()
229 const MSP430InstrInfo &TII = in eliminateCallFramePseudoInstr() local
239 uint64_t Amount = TII.getFrameSize(Old); in eliminateCallFramePseudoInstr()
247 if (Old.getOpcode() == TII.getCallFrameSetupOpcode()) { in eliminateCallFramePseudoInstr()
255 Amount -= TII.getFramePoppedByCallee(Old); in eliminateCallFramePseudoInstr()
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/freebsd-12.1/contrib/llvm/lib/Target/XCore/
H A DXCoreFrameLowering.cpp67 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in EmitDefCfaRegister()
108 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm); in IfNeededExtSP()
111 EmitDefCfaOffset(MBB, MBBI, dl, TII, Adjusted*4); in IfNeededExtSP()
270 EmitDefCfaOffset(MBB, MBBI, dl, TII, Adjusted*4); in emitPrologue()
272 EmitCfiOffset(MBB, MBBI, dl, TII, DRegNum, 0); in emitPrologue()
290 BuildMI(MBB, MBBI, dl, TII.get(Opcode)) in emitPrologue()
310 EmitDefCfaRegister(MBB, MBBI, dl, TII, MF, in emitPrologue()
322 EmitCfiOffset(MBB, Pos, dl, TII, DRegNum, Offset); in emitPrologue()
334 EmitCfiOffset(MBB, MBBI, dl, TII, in emitPrologue()
337 EmitCfiOffset(MBB, MBBI, dl, TII, in emitPrologue()
[all …]
H A DXCoreRegisterInfo.cpp63 const XCoreInstrInfo &TII, in InsertFPImmInst() argument
77 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus)) in InsertFPImmInst()
103 TII.loadImmediate(MBB, II, ScratchOffset, Offset); in InsertFPConstInst()
113 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r)) in InsertFPConstInst()
141 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
147 BuildMI(MBB, II, dl, TII.get(NewOpcode)) in InsertSPImmInst()
154 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
190 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r)) in InsertSPConstInst()
269 const XCoreInstrInfo &TII = in eliminateFrameIndex() local
315 InsertSPImmInst(II, TII, Reg, Offset); in eliminateFrameIndex()
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/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp73 const ARMBaseInstrInfo &TII; member in __anon2f75b15d0111::ARMInstructionSelector
605 MIB->setDesc(TII.get(Opc)); in selectGlobal()
625 MIB->setDesc(TII.get(Opc)); in selectGlobal()
791 I.setDesc(TII.get(NewOpc)); in select()
847 I.setDesc(TII.get(COPY)); in select()
872 I.setDesc(TII.get(ARM::MOVi)); in select()
897 I.setDesc(TII.get(COPY)); in select()
934 I.setDesc(TII.get(ARM::ADDrr)); in select()
940 I.setDesc(TII.get(ARM::ADDri)); in select()
966 I.setDesc(TII.get(NewOpc)); in select()
[all …]
H A DARMFrameLowering.cpp771 const ARMBaseInstrInfo &TII = in emitEpilogue() local
800 if (!isCSRestore(*MBBI, TII, CSRegs)) in emitEpilogue()
1201 BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4) in emitAlignedDPRCS2Spills()
1484 FnSize += TII.getInstSizeInBytes(MI); in GetFunctionSizeInBytes()
1607 const ARMBaseInstrInfo &TII = in determineCalleeSaves() local
2036 const ARMBaseInstrInfo &TII = in eliminateCallFramePseudoInstr() local
2044 unsigned Amount = TII.getFrameSize(Old); in eliminateCallFramePseudoInstr()
2151 const ARMBaseInstrInfo &TII = in adjustForSegmentedStacks() local
2338 BuildMI(GetMBB, DL, TII.get(Opcode)) in adjustForSegmentedStacks()
2407 BuildMI(AllocMBB, DL, TII.get(ARM::tBL)) in adjustForSegmentedStacks()
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/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsBranchExpansion.cpp168 const MipsInstrInfo *TII; member in __anoncb5f2bef0111::MipsBranchExpansion
300 MBBInfos[I].Size += TII->getInstSizeInBytes(*MI); in initMBBInfo()
339 const MCInstrDesc &NewDesc = TII->get(NewOpc); in replaceBranch()
460 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)) in expandToLongBranch()
524 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::NOP)); in expandToLongBranch()
583 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SD)) in expandToLongBranch()
669 .append(BuildMI(*MFp, DL, TII->get(Mips::NOP))); in expandToLongBranch()
725 BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::V0) in emitGPDisp()
727 BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0) in emitGPDisp()
744 if (!TII->HasForbiddenSlot(*I)) in handleForbiddenSlot()
[all …]
H A DMipsInstructionSelector.cpp43 const MipsInstrInfo &TII; member in __anon937613cf0111::MipsInstructionSelector
103 return selectCopy(I, TII, MRI, TRI, RBI); in select()
117 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) in select()
124 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select()
141 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc)) in select()
189 LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)) in select()
193 ORi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ORi)) in select()
198 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) in select()
200 if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI)) in select()
214 LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)) in select()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64InstructionSelector.cpp114 const AArch64InstrInfo &TII; member in __anon162375af0111::AArch64InstructionSelector
434 I.setDesc(TII.get(AArch64::COPY)); in selectCopy()
635 .constrainAllUses(TII, TRI, RBI); in selectCompareBranch()
825 I.setDesc(TII.get(AArch64::BR)); in select()
882 I.setDesc(TII.get(MovOpc)); in select()
895 TII.get(AArch64::COPY)) in select()
941 TII.get(AArch64::COPY)) in select()
1064 I.setDesc(TII.get(NewOpc)); in select()
1126 I.setDesc(TII.get(NewOpc)); in select()
1155 I.setDesc(TII.get(NewOpc)); in select()
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