Lines Matching refs:TII
66 const SIInstrInfo *TII = ST.getInstrInfo(); in runOnMachineFunction() local
79 if (TII->isMIMG(Opcode) && !MI.mayStore()) { in runOnMachineFunction()
80 MachineOperand *TFE = TII->getNamedOperand(MI, AMDGPU::OpName::tfe); in runOnMachineFunction()
81 MachineOperand *LWE = TII->getNamedOperand(MI, AMDGPU::OpName::lwe); in runOnMachineFunction()
82 MachineOperand *D16 = TII->getNamedOperand(MI, AMDGPU::OpName::d16); in runOnMachineFunction()
104 TII->getNamedOperand(MI, AMDGPU::OpName::dmask); in runOnMachineFunction()
113 TII->isGather4(Opcode) ? 4 : countPopulation(dmask); in runOnMachineFunction()
128 RI->getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32; in runOnMachineFunction()
134 MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx)); in runOnMachineFunction()
145 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), PrevDst) in runOnMachineFunction()
149 BuildMI(MBB, MI, DL, TII->get(AMDGPU::IMPLICIT_DEF), PrevDst); in runOnMachineFunction()
152 MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx)); in runOnMachineFunction()
156 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), SubReg) in runOnMachineFunction()
159 BuildMI(MBB, I, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewDst) in runOnMachineFunction()