Lines Matching refs:TII
114 const AArch64InstrInfo &TII; member in __anon162375af0111::AArch64InstructionSelector
138 : InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()), in AArch64InstructionSelector()
335 static bool selectFP16CopyFromGPR32(MachineInstr &I, const TargetInstrInfo &TII, in selectFP16CopyFromGPR32() argument
339 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::COPY)) in selectFP16CopyFromGPR32()
343 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::COPY)) in selectFP16CopyFromGPR32()
352 static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, in selectCopy() argument
366 return selectFP16CopyFromGPR32(I, TII, MRI, SrcReg); in selectCopy()
413 TII.get(AArch64::SUBREG_TO_REG)) in selectCopy()
422 selectFP16CopyFromGPR32(I, TII, MRI, SrcReg); in selectCopy()
430 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) in selectCopy()
434 I.setDesc(TII.get(AArch64::COPY)); in selectCopy()
632 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(CBOpc)) in selectCompareBranch()
635 .constrainAllUses(TII, TRI, RBI); in selectCompareBranch()
654 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::ADDXri)) in selectVaStartDarwin()
660 constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectVaStartDarwin()
662 MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::STRXui)) in selectVaStartDarwin()
668 constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectVaStartDarwin()
685 constrainSelectedInstRegOperands(*MovZ, TII, TRI, RBI); in materializeLargeCMVal()
702 constrainSelectedInstRegOperands(*MovI, TII, TRI, RBI); in materializeLargeCMVal()
727 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in select()
754 I.setDesc(TII.get(TargetOpcode::PHI)); in select()
760 return selectCopy(I, TII, MRI, TRI, RBI); in select()
801 auto MIB = BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::TBNZW)) in select()
807 return constrainSelectedInstRegOperands(*MIB.getInstr(), TII, TRI, RBI); in select()
809 auto CMP = BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ANDSWri)) in select()
813 constrainSelectedInstRegOperands(*CMP.getInstr(), TII, TRI, RBI); in select()
815 BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::Bcc)) in select()
820 return constrainSelectedInstRegOperands(*Bcc.getInstr(), TII, TRI, RBI); in select()
825 I.setDesc(TII.get(AArch64::BR)); in select()
826 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in select()
882 I.setDesc(TII.get(MovOpc)); in select()
895 TII.get(AArch64::COPY)) in select()
916 constrainSelectedInstRegOperands(I, TII, TRI, RBI); in select()
929 I.setDesc(TII.get(SrcSize == 64 ? AArch64::UBFMXri : AArch64::UBFMWri)); in select()
936 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in select()
941 TII.get(AArch64::COPY)) in select()
948 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in select()
960 I.setDesc(TII.get(DstSize == 64 ? AArch64::BFMXri : AArch64::BFMWri)); in select()
969 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in select()
974 TII.get(AArch64::SUBREG_TO_REG)) in select()
983 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in select()
992 I.setDesc(TII.get(AArch64::ADDXri)); in select()
998 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in select()
1009 I.setDesc(TII.get(AArch64::LOADgot)); in select()
1017 I.setDesc(TII.get(AArch64::ADR)); in select()
1020 I.setDesc(TII.get(AArch64::MOVaddr)); in select()
1026 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in select()
1064 I.setDesc(TII.get(NewOpc)); in select()
1101 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in select()
1126 I.setDesc(TII.get(NewOpc)); in select()
1130 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in select()
1155 I.setDesc(TII.get(NewOpc)); in select()
1160 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in select()
1169 I.setDesc(TII.get(AArch64::ANDXri)); in select()
1172 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in select()
1223 I.setDesc(TII.get(TargetOpcode::COPY)); in select()
1227 I.setDesc(TII.get(AArch64::XTNv4i16)); in select()
1228 constrainSelectedInstRegOperands(I, TII, TRI, RBI); in select()
1270 BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::SUBREG_TO_REG)) in select()
1277 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1291 LLVM_DEBUG(dbgs() << TII.getName(I.getOpcode()) << " on bank: " << RB in select()
1300 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(Opcode) in select()
1307 BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::SUBREG_TO_REG)) in select()
1314 ExtI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc)) in select()
1321 ExtI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc)) in select()
1330 constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI); in select()
1346 I.setDesc(TII.get(NewOpc)); in select()
1347 constrainSelectedInstRegOperands(I, TII, TRI, RBI); in select()
1356 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1364 return selectCopy(I, TII, MRI, TRI, RBI); in select()
1389 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ANDSWri)) in select()
1394 MachineInstr &CSelMI = *BuildMI(MBB, I, I.getDebugLoc(), TII.get(CSelOpc)) in select()
1400 constrainSelectedInstRegOperands(TstMI, TII, TRI, RBI); in select()
1401 constrainSelectedInstRegOperands(CSelMI, TII, TRI, RBI); in select()
1434 MachineInstr &CmpMI = *BuildMI(MBB, I, I.getDebugLoc(), TII.get(CmpOpc)) in select()
1440 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CSINCWr)) in select()
1446 constrainSelectedInstRegOperands(CmpMI, TII, TRI, RBI); in select()
1447 constrainSelectedInstRegOperands(CSetMI, TII, TRI, RBI); in select()
1476 MachineInstr &CmpMI = *BuildMI(MBB, I, I.getDebugLoc(), TII.get(CmpOpc)) in select()
1486 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CSINCWr)) in select()
1495 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CSINCWr)) in select()
1501 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ORRWrr)) in select()
1505 constrainSelectedInstRegOperands(OrMI, TII, TRI, RBI); in select()
1506 constrainSelectedInstRegOperands(CSet2MI, TII, TRI, RBI); in select()
1509 constrainSelectedInstRegOperands(CmpMI, TII, TRI, RBI); in select()
1510 constrainSelectedInstRegOperands(CSetMI, TII, TRI, RBI); in select()
1523 BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::BRK)) in select()
1528 I.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF)); in select()
1543 I.setDesc(TII.get(AArch64::MOVaddrBA)); in select()
1544 auto MovMI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::MOVaddrBA), in select()
1552 return constrainSelectedInstRegOperands(*MovMI, TII, TRI, RBI); in select()
1572 TII.get(TargetOpcode::IMPLICIT_DEF)) in emitScalarToVector()
1577 TII.get(TargetOpcode::INSERT_SUBREG)) in emitScalarToVector()
1582 constrainSelectedInstRegOperands(UndefMI, TII, TRI, RBI); in emitScalarToVector()
1583 return constrainSelectedInstRegOperands(InsMI, TII, TRI, RBI); in emitScalarToVector()
1615 TII.get(TargetOpcode::SUBREG_TO_REG)) in selectMergeValues()
1623 TII.get(TargetOpcode::SUBREG_TO_REG)) in selectMergeValues()
1629 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::BFMXri)) in selectMergeValues()
1635 constrainSelectedInstRegOperands(SubRegMI, TII, TRI, RBI); in selectMergeValues()
1636 constrainSelectedInstRegOperands(SubRegMI2, TII, TRI, RBI); in selectMergeValues()
1637 constrainSelectedInstRegOperands(BFM, TII, TRI, RBI); in selectMergeValues()
1692 TII.get(TargetOpcode::IMPLICIT_DEF)) in selectBuildVector()
1696 TII.get(TargetOpcode::INSERT_SUBREG)) in selectBuildVector()
1702 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc)) in selectBuildVector()
1708 constrainSelectedInstRegOperands(ImpDefMI, TII, TRI, RBI); in selectBuildVector()
1709 constrainSelectedInstRegOperands(InsSubMI, TII, TRI, RBI); in selectBuildVector()
1710 constrainSelectedInstRegOperands(InsEltMI, TII, TRI, RBI); in selectBuildVector()
1714 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc)) in selectBuildVector()
1719 constrainSelectedInstRegOperands(InsMI, TII, TRI, RBI); in selectBuildVector()