Lines Matching refs:TII
145 void processBlockPhase1(MachineBasicBlock &MBB, const SIInstrInfo *TII);
147 void processBlockPhase2(MachineBasicBlock &MBB, const SIInstrInfo *TII);
149 void processBlockPhase3(MachineBasicBlock &MBB, const SIInstrInfo *TII);
151 Status getInstructionMode(MachineInstr &MI, const SIInstrInfo *TII);
154 const SIInstrInfo *TII, Status InstrMode);
172 const SIInstrInfo *TII) { in getInstructionMode() argument
173 if (TII->usesFPDPRounding(MI)) { in getInstructionMode()
194 const SIInstrInfo *TII, Status InstrMode) { in insertSetreg() argument
199 BuildMI(MBB, MI, 0, TII->get(AMDGPU::S_SETREG_IMM32_B32)) in insertSetreg()
229 const SIInstrInfo *TII) { in processBlockPhase1() argument
240 Status InstrMode = getInstructionMode(MI, TII); in processBlockPhase1()
246 unsigned Dst = TII->getNamedOperand(MI, AMDGPU::OpName::simm16)->getImm(); in processBlockPhase1()
260 insertSetreg(MBB, InsertionPoint, TII, IPChange.delta(NewInfo->Change)); in processBlockPhase1()
267 unsigned Val = TII->getNamedOperand(MI, AMDGPU::OpName::imm)->getImm(); in processBlockPhase1()
293 insertSetreg(MBB, InsertionPoint, TII, in processBlockPhase1()
317 insertSetreg(MBB, InsertionPoint, TII, IPChange.delta(NewInfo->Change)); in processBlockPhase1()
328 const SIInstrInfo *TII) { in processBlockPhase2() argument
364 const SIInstrInfo *TII) { in processBlockPhase3() argument
370 insertSetreg(MBB, BlockInfo[ThisBlock]->FirstInsertionPoint, TII, Delta); in processBlockPhase3()
372 insertSetreg(MBB, &MBB.instr_front(), TII, Delta); in processBlockPhase3()
379 const SIInstrInfo *TII = ST.getInstrInfo(); in runOnMachineFunction() local
386 processBlockPhase1(BB, TII); in runOnMachineFunction()
394 processBlockPhase2(*Phase2List.front(), TII); in runOnMachineFunction()
401 processBlockPhase3(BB, TII); in runOnMachineFunction()