44   TII(*ST.getInstrInfo()),  in GCNHazardRecognizer()
45   TRI(TII.getRegisterInfo()),  in GCNHazardRecognizer()
91 static bool isSendMsgTraceDataOrGDS(const SIInstrInfo &TII,  in isSendMsgTraceDataOrGDS()  argument
93   if (TII.isAlwaysGDS(MI.getOpcode()))  in isSendMsgTraceDataOrGDS()
107     if (TII.isDS(MI.getOpcode())) {  in isSendMsgTraceDataOrGDS()
117 static unsigned getHWReg(const SIInstrInfo *TII, const MachineInstr &RegInstr) {  in getHWReg()  argument
118   const MachineOperand *RegOp = TII->getNamedOperand(RegInstr,  in getHWReg()
158       (TII.isVINTRP(*MI) || isSMovRel(MI->getOpcode())) &&  in getHazardType()
162   if (ST.hasReadM0SendMsgHazard() && isSendMsgTraceDataOrGDS(TII, *MI) &&  in getHazardType()
212   if (ST.hasReadM0MovRelInterpHazard() && (TII.isVINTRP(*MI) ||  in PreEmitNoops()
216   if (ST.hasReadM0SendMsgHazard() && isSendMsgTraceDataOrGDS(TII, *MI))  in PreEmitNoops()
240   unsigned NumWaitStates = TII.getNumWaitStates(*CurrCycleInstr);  in AdvanceCycle()
337   bool IsSMRD = TII.isSMRD(*MEM);  in checkSoftClauseHazards()
392   auto IsHazardDefFn = [this] (MachineInstr *MI) { return TII.isVALU(*MI); };  in checkSMRDHazards()
393   auto IsBufferHazardDefFn = [this] (MachineInstr *MI) { return TII.isSALU(*MI); };  in checkSMRDHazards()
395   bool IsBufferSMRD = TII.isBufferSMRD(*SMRD);  in checkSMRDHazards()
431   auto IsHazardDefFn = [this] (MachineInstr *MI) { return TII.isVALU(*MI); };  in checkVMEMHazards()
446   const SIInstrInfo *TII = ST.getInstrInfo();  in checkDPPHazards()  local
452   auto IsHazardDefFn = [TII] (MachineInstr *MI) { return TII->isVALU(*MI); };  in checkDPPHazards()
470   const SIInstrInfo *TII = ST.getInstrInfo();  in checkDivFMasHazards()  local
475   auto IsHazardDefFn = [TII] (MachineInstr *MI) { return TII->isVALU(*MI); };  in checkDivFMasHazards()
482   const SIInstrInfo *TII = ST.getInstrInfo();  in checkGetRegHazards()  local
483   unsigned GetRegHWReg = getHWReg(TII, *GetRegInstr);  in checkGetRegHazards()
486   auto IsHazardFn = [TII, GetRegHWReg] (MachineInstr *MI) {  in checkGetRegHazards()
487     return GetRegHWReg == getHWReg(TII, *MI);  in checkGetRegHazards()
495   const SIInstrInfo *TII = ST.getInstrInfo();  in checkSetRegHazards()  local
496   unsigned HWReg = getHWReg(TII, *SetRegInstr);  in checkSetRegHazards()
500   auto IsHazardFn = [TII, HWReg] (MachineInstr *MI) {  in checkSetRegHazards()
501     return HWReg == getHWReg(TII, *MI);  in checkSetRegHazards()
511   const SIInstrInfo *TII = ST.getInstrInfo();  in createsVALUHazard()  local
520   if (TII->isMUBUF(MI) || TII->isMTBUF(MI)) {  in createsVALUHazard()
528         TII->getNamedOperand(MI, AMDGPU::OpName::soffset);  in createsVALUHazard()
540   if (TII->isMIMG(MI)) {  in createsVALUHazard()
547   if (TII->isFLAT(MI)) {  in createsVALUHazard()
623   const SIInstrInfo *TII = ST.getInstrInfo();  in checkRWLaneHazards()  local
628       TII->getNamedOperand(*RWLane, AMDGPU::OpName::src1);  in checkRWLaneHazards()
634   auto IsHazardFn = [TII] (MachineInstr *MI) {  in checkRWLaneHazards()
635     return TII->isVALU(*MI);  in checkRWLaneHazards()
647   const SIInstrInfo *TII = ST.getInstrInfo();  in checkRFEHazards()  local
651   auto IsHazardFn = [TII] (MachineInstr *MI) {  in checkRFEHazards()
652     return getHWReg(TII, *MI) == AMDGPU::Hwreg::ID_TRAPSTS;  in checkRFEHazards()
686   const SIInstrInfo *TII = ST.getInstrInfo();  in checkReadM0Hazards()  local
688   auto IsHazardFn = [TII] (MachineInstr *MI) {  in checkReadM0Hazards()
689     return TII->isSALU(*MI);  in checkReadM0Hazards()