41   const SIInstrInfo *TII = ST.getInstrInfo();  in emitFlatScratchInit()  local
42   const SIRegisterInfo* TRI = &TII->getRegisterInfo();  in emitFlatScratchInit()
74     BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), AMDGPU::FLAT_SCR_LO)  in emitFlatScratchInit()
77     BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADDC_U32), AMDGPU::FLAT_SCR_HI)  in emitFlatScratchInit()
85   BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), AMDGPU::FLAT_SCR_LO)  in emitFlatScratchInit()
90   BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), FlatScrInitLo)  in emitFlatScratchInit()
95   BuildMI(MBB, I, DL, TII->get(AMDGPU::S_LSHR_B32), AMDGPU::FLAT_SCR_HI)  in emitFlatScratchInit()
102   const SIInstrInfo *TII,  in getReservedPrivateSegmentBufferReg()  argument
153   const SIInstrInfo *TII,  in getReservedPrivateSegmentWaveByteOffsetReg()  argument
237   const SIInstrInfo *TII = ST.getInstrInfo();  in emitEntryFunctionPrologue()  local
238   const SIRegisterInfo *TRI = &TII->getRegisterInfo();  in emitEntryFunctionPrologue()
263       BuildMI(MBB, MBB.begin(), DL, TII->get(AMDGPU::COPY), SPReg)  in emitEntryFunctionPrologue()
266       BuildMI(MBB, MBB.begin(), DL, TII->get(AMDGPU::S_ADD_U32), SPReg)  in emitEntryFunctionPrologue()
273     = getReservedPrivateSegmentBufferReg(ST, TII, TRI, MFI, MF);  in emitEntryFunctionPrologue()
277     = getReservedPrivateSegmentWaveByteOffsetReg(ST, TII, TRI, MFI, MF);  in emitEntryFunctionPrologue()
345     BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchRsrcReg)  in emitEntryFunctionPrologue()
351     BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchWaveOffsetReg)  in emitEntryFunctionPrologue()
357     BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchRsrcReg)  in emitEntryFunctionPrologue()
372   const SIInstrInfo *TII = ST.getInstrInfo();  in emitEntryFunctionScratchSetup()  local
373   const SIRegisterInfo *TRI = &TII->getRegisterInfo();  in emitEntryFunctionScratchSetup()
384     const MCInstrDesc &SMovB32 = TII->get(AMDGPU::S_MOV_B32);  in emitEntryFunctionScratchSetup()
391       const MCInstrDesc &GetPC64 = TII->get(AMDGPU::S_GETPC_B64);  in emitEntryFunctionScratchSetup()
419     const MCInstrDesc &LoadDwordX4 = TII->get(AMDGPU::S_LOAD_DWORDX4_IMM);  in emitEntryFunctionScratchSetup()
437     const MCInstrDesc &SMovB32 = TII->get(AMDGPU::S_MOV_B32);  in emitEntryFunctionScratchSetup()
443     uint64_t Rsrc23 = TII->getScratchRsrcWords23();  in emitEntryFunctionScratchSetup()
449         const MCInstrDesc &Mov64 = TII->get(AMDGPU::S_MOV_B64);  in emitEntryFunctionScratchSetup()
455         const MCInstrDesc &LoadDwordX2 = TII->get(AMDGPU::S_LOAD_DWORDX2_IMM);  in emitEntryFunctionScratchSetup()
541   const SIInstrInfo *TII = ST.getInstrInfo();  in emitPrologue()  local
542   const SIRegisterInfo &TRI = TII->getRegisterInfo();  in emitPrologue()
568     BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_ADD_U32), ScratchSPReg)  in emitPrologue()
572     BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_AND_B32), FramePtrReg)  in emitPrologue()
582     BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::COPY), FramePtrReg)  in emitPrologue()
588     BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_ADD_U32), StackPtrReg)  in emitPrologue()
598     TII->storeRegToStackSlot(MBB, MBBI, Reg.VGPR, true,  in emitPrologue()
600                              &TII->getRegisterInfo());  in emitPrologue()
611   const SIInstrInfo *TII = ST.getInstrInfo();  in emitEpilogue()  local
618     TII->loadRegFromStackSlot(MBB, MBBI, Reg.VGPR,  in emitEpilogue()
620                               &TII->getRegisterInfo());  in emitEpilogue()
639     BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_SUB_U32), StackPtrReg)  in emitEpilogue()
672   const SIInstrInfo *TII = ST.getInstrInfo();  in processFunctionBeforeFrameFinalized()  local
673   const SIRegisterInfo &TRI = TII->getRegisterInfo();  in processFunctionBeforeFrameFinalized()
694         if (TII->isSGPRSpill(MI)) {  in processFunctionBeforeFrameFinalized()
695           int FI = TII->getNamedOperand(MI, AMDGPU::OpName::addr)->getIndex();  in processFunctionBeforeFrameFinalized()
754   const SIInstrInfo *TII = ST.getInstrInfo();  in eliminateCallFramePseudoInstr()  local
757   bool IsDestroy = Opc == TII->getCallFrameDestroyOpcode();  in eliminateCallFramePseudoInstr()
770     BuildMI(MBB, I, DL, TII->get(Op), SPReg)  in eliminateCallFramePseudoInstr()
783   const SIInstrInfo *TII = ST.getInstrInfo();  in emitDebuggerPrologue()  local
784   const SIRegisterInfo *TRI = &TII->getRegisterInfo();  in emitDebuggerPrologue()
801     BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), WorkGroupIDVGPR)  in emitDebuggerPrologue()
806     TII->storeRegToStackSlot(MBB, I, WorkGroupIDVGPR, false,  in emitDebuggerPrologue()
816     TII->storeRegToStackSlot(MBB, I, WorkItemIDVGPR, false,  in emitDebuggerPrologue()