Lines Matching refs:TII
88 const SIInstrInfo *TII; member in __anon5a94fe150111::SIFoldOperands
132 static bool isInlineConstantIfFolded(const SIInstrInfo *TII, in isInlineConstantIfFolded() argument
136 if (TII->isInlineConstant(UseMI, OpNo, OpToFold)) in isInlineConstantIfFolded()
153 const MCInstrDesc &MadDesc = TII->get(Opc); in isInlineConstantIfFolded()
154 return TII->isInlineConstant(OpToFold, MadDesc.OpInfo[OpNo].OperandType); in isInlineConstantIfFolded()
168 const SIInstrInfo &TII, in updateOperand() argument
223 MachineInstr *Inst32 = TII.buildShrunkInst(*MI, Op32); in updateOperand()
226 BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), Dst1.getReg()) in updateOperand()
239 MI->setDesc(TII.get(AMDGPU::IMPLICIT_DEF)); in updateOperand()
242 TII.commuteInstruction(*Inst32, false); in updateOperand()
284 const SIInstrInfo *TII) { in tryAddToFoldList() argument
285 if (!TII->isOperandLegal(*MI, OpNo, OpToFold)) { in tryAddToFoldList()
299 MI->setDesc(TII->get(NewOpc)); in tryAddToFoldList()
300 bool FoldAsMAD = tryAddToFoldList(FoldList, MI, OpNo, OpToFold, TII); in tryAddToFoldList()
305 MI->setDesc(TII->get(Opc)); in tryAddToFoldList()
310 MI->setDesc(TII->get(AMDGPU::S_SETREG_IMM32_B32)); in tryAddToFoldList()
327 bool CanCommute = TII->findCommutedOpIndices(*MI, CommuteIdx0, CommuteIdx1); in tryAddToFoldList()
346 !TII->commuteInstruction(*MI, false, CommuteIdx0, CommuteIdx1)) in tryAddToFoldList()
349 if (!TII->isOperandLegal(*MI, CommuteOpNo, OpToFold)) { in tryAddToFoldList()
361 !TII->getRegisterInfo().isVGPR(MRI, OtherOp.getReg())) in tryAddToFoldList()
375 TII->commuteInstruction(*MI, false, CommuteIdx0, CommuteIdx1); in tryAddToFoldList()
389 static bool isUseSafeToFold(const SIInstrInfo *TII, in isUseSafeToFold() argument
392 return !UseMO.isUndef() && !TII->isSDWA(MI); in isUseSafeToFold()
404 if (!isUseSafeToFold(TII, *UseMI, UseOp)) in foldOperand()
482 unsigned MovOp = TII->getMovOpcode(DestRC); in foldOperand()
486 UseMI->setDesc(TII->get(MovOp)); in foldOperand()
514 tryAddToFoldList(FoldList, UseMI, UseOpIdx, &OpToFold, TII); in foldOperand()
548 tryAddToFoldList(FoldList, UseMI, UseOpIdx, &ImmOp, TII); in foldOperand()
554 tryAddToFoldList(FoldList, UseMI, UseOpIdx, &OpToFold, TII); in foldOperand()
653 const SIInstrInfo *TII, in tryConstantFoldOp() argument
660 mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_NOT_B32))); in tryConstantFoldOp()
679 bool UseCopy = TII->getNamedOperand(*MI, AMDGPU::OpName::src2)->isReg(); in tryConstantFoldOp()
683 MI->setDesc(TII->get(UseCopy ? AMDGPU::COPY : AMDGPU::V_MOV_B32_e32)); in tryConstantFoldOp()
696 const SIRegisterInfo &TRI = TII->getRegisterInfo(); in tryConstantFoldOp()
703 mutateCopyOp(*MI, TII->get(getMovOpc(IsSGPR))); in tryConstantFoldOp()
722 mutateCopyOp(*MI, TII->get(AMDGPU::COPY)); in tryConstantFoldOp()
726 mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_OR_B32))); in tryConstantFoldOp()
739 mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_AND_B32))); in tryConstantFoldOp()
743 mutateCopyOp(*MI, TII->get(AMDGPU::COPY)); in tryConstantFoldOp()
757 mutateCopyOp(*MI, TII->get(AMDGPU::COPY)); in tryConstantFoldOp()
766 static bool tryFoldInst(const SIInstrInfo *TII, in tryFoldInst() argument
773 const MachineOperand *Src0 = TII->getNamedOperand(*MI, AMDGPU::OpName::src0); in tryFoldInst()
774 const MachineOperand *Src1 = TII->getNamedOperand(*MI, AMDGPU::OpName::src1); in tryFoldInst()
781 mutateCopyOp(*MI, TII->get(Src0->isReg() ? (unsigned)AMDGPU::COPY in tryFoldInst()
823 if (OpToFold.isImm() && tryConstantFoldOp(*MRI, TII, UseMI, &OpToFold)) { in foldInstOperand()
850 if (isInlineConstantIfFolded(TII, *UseMI, OpNo, OpToFold)) { in foldInstOperand()
886 if (updateOperand(Fold, *TII, *TRI)) { in foldInstOperand()
898 tryFoldInst(TII, Fold.UseMI); in foldInstOperand()
901 TII->commuteInstruction(*Fold.UseMI, false); in foldInstOperand()
915 if (!TII->getNamedOperand(MI, AMDGPU::OpName::clamp)->getImm()) in isClamp()
919 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in isClamp()
920 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in isClamp()
928 if (TII->hasModifiersSet(MI, AMDGPU::OpName::omod)) in isClamp()
932 = TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers)->getImm(); in isClamp()
934 = TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers)->getImm(); in isClamp()
970 if (TII->getClampMask(*Def) != TII->getClampMask(MI)) in tryFoldClamp()
973 MachineOperand *DefClamp = TII->getNamedOperand(*Def, AMDGPU::OpName::clamp); in tryFoldClamp()
1034 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in isOMod()
1035 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in isOMod()
1047 TII->hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers) || in isOMod()
1048 TII->hasModifiersSet(MI, AMDGPU::OpName::src1_modifiers) || in isOMod()
1049 TII->hasModifiersSet(MI, AMDGPU::OpName::omod) || in isOMod()
1050 TII->hasModifiersSet(MI, AMDGPU::OpName::clamp)) in isOMod()
1063 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in isOMod()
1064 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in isOMod()
1068 !TII->hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers) && in isOMod()
1069 !TII->hasModifiersSet(MI, AMDGPU::OpName::src1_modifiers) && in isOMod()
1070 !TII->hasModifiersSet(MI, AMDGPU::OpName::clamp) && in isOMod()
1071 !TII->hasModifiersSet(MI, AMDGPU::OpName::omod)) in isOMod()
1092 MachineOperand *DefOMod = TII->getNamedOperand(*Def, AMDGPU::OpName::omod); in tryFoldOMod()
1098 if (TII->hasModifiersSet(*Def, AMDGPU::OpName::clamp)) in tryFoldOMod()
1115 TII = ST->getInstrInfo(); in runOnMachineFunction()
1116 TRI = &TII->getRegisterInfo(); in runOnMachineFunction()
1132 tryFoldInst(TII, &MI); in runOnMachineFunction()
1134 if (!TII->isFoldableCopy(MI)) { in runOnMachineFunction()