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Searched refs:Mips (Results 1 – 25 of 103) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp51 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { in isLoadFromStackSlot()
73 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { in isStoreToStackSlot()
497 case Mips::BEQ: return Mips::BNE; in getOppositeBranchOpc()
499 case Mips::BNE: return Mips::BEQ; in getOppositeBranchOpc()
501 case Mips::BGTZ: return Mips::BLEZ; in getOppositeBranchOpc()
502 case Mips::BGEZ: return Mips::BLTZ; in getOppositeBranchOpc()
503 case Mips::BLTZ: return Mips::BGEZ; in getOppositeBranchOpc()
504 case Mips::BLEZ: return Mips::BGTZ; in getOppositeBranchOpc()
515 case Mips::BC1T: return Mips::BC1F; in getOppositeBranchOpc()
516 case Mips::BC1F: return Mips::BC1T; in getOppositeBranchOpc()
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H A DMipsInstrInfo.cpp289 case Mips::BEQ: case Mips::BEQ64: in isBranchOffsetInRange()
291 case Mips::BGEZ: case Mips::BGEZ64: in isBranchOffsetInRange()
295 case Mips::BGTZ: case Mips::BGTZ64: in isBranchOffsetInRange()
297 case Mips::BLEZ: case Mips::BLEZ64: in isBranchOffsetInRange()
299 case Mips::BLTZ: case Mips::BLTZ64: in isBranchOffsetInRange()
303 case Mips::BNE: case Mips::BNE64: in isBranchOffsetInRange()
340 case Mips::BEQC: case Mips::BEQC64: in isBranchOffsetInRange()
341 case Mips::BNEC: case Mips::BNEC64: in isBranchOffsetInRange()
342 case Mips::BGEC: case Mips::BGEC64: in isBranchOffsetInRange()
343 case Mips::BGEUC: case Mips::BGEUC64: in isBranchOffsetInRange()
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H A DMipsExpandPseudo.cpp89 I->getOpcode() == Mips::ATOMIC_CMP_SWAP_I8_POSTRA ? Mips::SEB : Mips::SEH; in expandAtomicCmpSwapSubword()
92 LL = STI->hasMips32r6() ? Mips::LL_MMR6 : Mips::LL_MM; in expandAtomicCmpSwapSubword()
93 SC = STI->hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM; in expandAtomicCmpSwapSubword()
225 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); in expandAtomicCmpSwap()
228 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); in expandAtomicCmpSwap()
236 LL = STI->hasMips64r6() ? Mips::LLD_R6 : Mips::LLD; in expandAtomicCmpSwap()
237 SC = STI->hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; in expandAtomicCmpSwap()
502 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); in expandAtomicBinOp()
505 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); in expandAtomicBinOp()
511 LL = STI->hasMips64r6() ? Mips::LLD_R6 : Mips::LLD; in expandAtomicBinOp()
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H A DMips16InstrInfo.cpp165 case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16; in getOppositeBranchOpc()
166 case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16; in getOppositeBranchOpc()
167 case Mips::BeqzRxImm16: return Mips::BnezRxImm16; in getOppositeBranchOpc()
168 case Mips::BnezRxImm16: return Mips::BeqzRxImm16; in getOppositeBranchOpc()
169 case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16; in getOppositeBranchOpc()
172 case Mips::Btnez16: return Mips::Bteqz16; in getOppositeBranchOpc()
173 case Mips::BtnezX16: return Mips::BteqzX16; in getOppositeBranchOpc()
177 case Mips::Bteqz16: return Mips::Btnez16; in getOppositeBranchOpc()
178 case Mips::BteqzX16: return Mips::BtnezX16; in getOppositeBranchOpc()
255 Mips::Restore16:Mips::RestoreX16; in restoreFrame()
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H A DMipsRegisterInfo.cpp55 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in getPointerRegClass()
59 return ABI.ArePtrs64bit() ? &Mips::SP64RegClass : &Mips::SP32RegClass; in getPointerRegClass()
61 return ABI.ArePtrs64bit() ? &Mips::GP64RegClass : &Mips::GP32RegClass; in getPointerRegClass()
153 Mips::ZERO, Mips::K0, Mips::K1, Mips::SP in getReservedRegs()
157 Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64 in getReservedRegs()
180 Reserved.set(Mips::GP); in getReservedRegs()
304 return TFI->hasFP(MF) ? Mips::S0 : Mips::SP; in getFrameRegister()
306 return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) : in getFrameRegister()
307 (IsN64 ? Mips::SP_64 : Mips::SP); in getFrameRegister()
322 unsigned FP = Subtarget.isGP32bit() ? Mips::FP : Mips::FP_64; in canRealignStack()
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H A DMicroMipsSizeReduction.cpp381 Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, in ConsecutiveRegisters()
382 Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, in ConsecutiveRegisters()
383 Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, in ConsecutiveRegisters()
384 Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, in ConsecutiveRegisters()
385 Mips::SP, Mips::FP, Mips::RA}; in ConsecutiveRegisters()
576 if (Reg == Mips::ZERO || Reg == Mips::V0 || Reg == Mips::V1 || in IsMovepSrcRegister()
577 Reg == Mips::S0 || Reg == Mips::S1 || Reg == Mips::S2 || in IsMovepSrcRegister()
578 Reg == Mips::S3 || Reg == Mips::S4) in IsMovepSrcRegister()
588 if (Reg == Mips::A0 || Reg == Mips::A1 || Reg == Mips::A2 || in IsMovepDestinationReg()
589 Reg == Mips::A3 || Reg == Mips::S5 || Reg == Mips::S6) in IsMovepDestinationReg()
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H A DMipsRegisterBankInfo.cpp25 namespace Mips { namespace
55 using namespace Mips; in getRegBankFromRegClass()
100 OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx]; in getInstrMapping()
106 getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr}); in getInstrMapping()
110 getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr, in getInstrMapping()
111 &Mips::ValueMappings[Mips::GPRIdx], in getInstrMapping()
112 &Mips::ValueMappings[Mips::GPRIdx]}); in getInstrMapping()
116 getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], in getInstrMapping()
117 &Mips::ValueMappings[Mips::GPRIdx], in getInstrMapping()
118 &Mips::ValueMappings[Mips::GPRIdx], in getInstrMapping()
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H A DMipsSERegisterInfo.cpp69 case Mips::LD_B: in getLoadStoreOffsetSizeInBits()
70 case Mips::ST_B: in getLoadStoreOffsetSizeInBits()
72 case Mips::LD_H: in getLoadStoreOffsetSizeInBits()
73 case Mips::ST_H: in getLoadStoreOffsetSizeInBits()
75 case Mips::LD_W: in getLoadStoreOffsetSizeInBits()
81 case Mips::LL: in getLoadStoreOffsetSizeInBits()
83 case Mips::LLD: in getLoadStoreOffsetSizeInBits()
84 case Mips::LLE: in getLoadStoreOffsetSizeInBits()
85 case Mips::SC: in getLoadStoreOffsetSizeInBits()
87 case Mips::SCD: in getLoadStoreOffsetSizeInBits()
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H A DMipsBranchExpansion.cpp372 unsigned JR = ABI.IsN64() ? Mips::JR64 : Mips::JR; in buildProperJumpMI()
373 unsigned JIC = ABI.IsN64() ? Mips::JIC64 : Mips::JIC; in buildProperJumpMI()
374 unsigned JR_HB = ABI.IsN64() ? Mips::JR_HB64 : Mips::JR_HB; in buildProperJumpMI()
386 unsigned ATReg = ABI.IsN64() ? Mips::AT_64 : Mips::AT; in buildProperJumpMI()
422 ? STI->inMicroMipsMode() ? Mips::BALC_MMR6 : Mips::BALC in expandToLongBranch()
457 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
503 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT) in expandToLongBranch()
506 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA) in expandToLongBranch()
617 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LD), Mips::RA_64) in expandToLongBranch()
725 BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::V0) in emitGPDisp()
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H A DMips16ISelLowering.cpp190 return emitSelT16(Mips::Bteqz16, Mips::CmpRxRy16, MI, BB); in EmitInstrWithCustomInserter()
192 return emitSelT16(Mips::Bteqz16, Mips::SltRxRy16, MI, BB); in EmitInstrWithCustomInserter()
196 return emitSelT16(Mips::Btnez16, Mips::CmpRxRy16, MI, BB); in EmitInstrWithCustomInserter()
218 Mips::Bteqz16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB); in EmitInstrWithCustomInserter()
220 Mips::Bteqz16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB); in EmitInstrWithCustomInserter()
222 Mips::Bteqz16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB); in EmitInstrWithCustomInserter()
224 Mips::Btnez16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB); in EmitInstrWithCustomInserter()
226 Mips::Btnez16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB); in EmitInstrWithCustomInserter()
228 Mips::Btnez16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB); in EmitInstrWithCustomInserter()
235 (Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB); in EmitInstrWithCustomInserter()
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H A DMipsSEFrameLowering.cpp132 expandStoreACC(MBB, I, Mips::PseudoMFHI, Mips::PseudoMFLO, 4); in expandInstr()
135 expandStoreACC(MBB, I, Mips::MFHI_DSP, Mips::MFLO_DSP, 4); in expandInstr()
320 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandBuildPairF64()
385 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandExtractElementF64()
420 unsigned AND = ABI.IsN64() ? Mips::AND64 : Mips::AND; in emitPrologue()
423 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitPrologue()
816 Reg == Mips::HI0 || Reg == Mips::HI0_64); in spillCalleeSavedRegisters()
823 Op = (Reg == Mips::HI0) ? Mips::MFHI : Mips::MFLO; in spillCalleeSavedRegisters()
826 Op = (Reg == Mips::HI0) ? Mips::MFHI64 : Mips::MFLO64; in spillCalleeSavedRegisters()
870 unsigned BP = ABI.IsN64() ? Mips::S7_64 : Mips::S7; in determineCalleeSaves()
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H A DMipsAsmPrinter.cpp920 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F14, LE); in EmitSwapFPIntParams()
924 EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE); in EmitSwapFPIntParams()
927 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE); in EmitSwapFPIntParams()
930 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE); in EmitSwapFPIntParams()
931 EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE); in EmitSwapFPIntParams()
934 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE); in EmitSwapFPIntParams()
953 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE); in EmitSwapFPIntRetval()
956 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE); in EmitSwapFPIntRetval()
959 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE); in EmitSwapFPIntRetval()
960 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F2, Mips::F3, LE); in EmitSwapFPIntRetval()
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H A DMipsFastISel.cpp309 Opc = Mips::OR; in emitLogicalOp()
374 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
716 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32; in emitCmp()
720 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32; in emitCmp()
724 Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32; in emitCmp()
728 Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32; in emitCmp()
732 Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32; in emitCmp()
736 Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32; in emitCmp()
745 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1); in emitCmp()
1329 std::array<MCPhysReg, 4> GPR32ArgRegs = {{Mips::A0, Mips::A1, Mips::A2, in fastLowerArguments()
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H A DMipsSEISelDAGToDAG.cpp103 ZeroReg = Mips::ZERO; in replaceUsesWithZeroReg()
152 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in initGlobalBaseReg()
168 .addReg(Mips::T9_64); in initGlobalBaseReg()
187 MBB.addLiveIn(Mips::T9); in initGlobalBaseReg()
196 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9); in initGlobalBaseReg()
222 MBB.addLiveIn(Mips::V0); in initGlobalBaseReg()
224 .addReg(Mips::V0).addReg(Mips::T9); in initGlobalBaseReg()
235 case Mips::RDDSP: in processFunctionAfterISel()
238 case Mips::WRDSP: in processFunctionAfterISel()
1092 const unsigned ADDiuOp = Is32BitSplat ? Mips::ADDiu : Mips::DADDiu; in trySelect()
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H A DMipsInstructionSelector.cpp84 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in selectCopy()
136 if (DestRegBank != Mips::GPRBRegBankID || OpSize != 32) in select()
139 const unsigned NewOpc = I.getOpcode() == G_STORE ? Mips::SW : Mips::LW; in select()
158 TII.get(IsSigned ? Mips::PseudoSDIV : Mips::PseudoUDIV)) in select()
166 TII.get(IsDiv ? Mips::PseudoMFLO : Mips::PseudoMFHI)) in select()
240 if (Opcode == Mips::SLTiu || Opcode == Mips::XORi) in select()
256 Instructions.emplace_back(Mips::XOR, Temp, LHS, RHS); in select()
260 Instructions.emplace_back(Mips::XOR, Temp, LHS, RHS); in select()
261 Instructions.emplace_back(Mips::SLTu, ICMPReg, Mips::ZERO, Temp); in select()
281 Instructions.emplace_back(Mips::SLT, Temp, LHS, RHS); in select()
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/freebsd-12.1/contrib/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsAsmBackend.cpp49 case Mips::fixup_Mips_LO16: in adjustFixupValue()
50 case Mips::fixup_Mips_GPREL16: in adjustFixupValue()
64 case Mips::fixup_MIPS_PCLO16: in adjustFixupValue()
74 case Mips::fixup_Mips_SUB: in adjustFixupValue()
77 case Mips::fixup_Mips_PC16: in adjustFixupValue()
97 case Mips::fixup_Mips_26: in adjustFixupValue()
103 case Mips::fixup_Mips_HI16: in adjustFixupValue()
104 case Mips::fixup_Mips_GOT: in adjustFixupValue()
109 case Mips::fixup_MIPS_PCHI16: in adjustFixupValue()
265 case Mips::fixup_Mips_16: in applyFixup()
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H A DMipsABIInfo.cpp26 static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3};
29 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
30 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64};
75 return ArePtrs64bit() ? Mips::SP_64 : Mips::SP; in GetStackPtr()
79 return ArePtrs64bit() ? Mips::FP_64 : Mips::FP; in GetFramePtr()
83 return ArePtrs64bit() ? Mips::S7_64 : Mips::S7; in GetBasePtr()
87 return ArePtrs64bit() ? Mips::GP_64 : Mips::GP; in GetGlobalPtr()
111 return ArePtrs64bit() ? Mips::AND64 : Mips::AND; in GetPtrAndOp()
115 return ArePtrs64bit() ? Mips::OR64 : Mips::OR; in GetGPRMoveOp()
120 Mips::A0, Mips::A1, Mips::A2, Mips::A3 in GetEhDataReg()
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H A DMipsMCCodeEmitter.cpp77 case Mips::DSLL: in LowerLargeShift()
80 case Mips::DSRL: in LowerLargeShift()
83 case Mips::DSRA: in LowerLargeShift()
86 case Mips::DROTR: in LowerLargeShift()
165 case Mips::DSLL: in encodeInstruction()
166 case Mips::DSRL: in encodeInstruction()
167 case Mips::DSRA: in encodeInstruction()
190 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && in encodeInstruction()
206 NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp); in encodeInstruction()
610 Mips::Fixups FixupKind = Mips::Fixups(0); in getExprOpValue()
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H A DMipsNaClELFStreamer.cpp221 case Mips::LB: in isBasePlusOffsetMemoryAccess()
222 case Mips::LBu: in isBasePlusOffsetMemoryAccess()
223 case Mips::LH: in isBasePlusOffsetMemoryAccess()
224 case Mips::LHu: in isBasePlusOffsetMemoryAccess()
225 case Mips::LW: in isBasePlusOffsetMemoryAccess()
228 case Mips::LL: in isBasePlusOffsetMemoryAccess()
236 case Mips::SB: in isBasePlusOffsetMemoryAccess()
237 case Mips::SH: in isBasePlusOffsetMemoryAccess()
238 case Mips::SW: in isBasePlusOffsetMemoryAccess()
249 case Mips::SC: in isBasePlusOffsetMemoryAccess()
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H A DMipsELFObjectWriter.cpp226 case Mips::fixup_Mips_NONE: in getRelocType()
232 case Mips::fixup_Mips_16: in getRelocType()
235 case Mips::fixup_Mips_32: in getRelocType()
281 case Mips::fixup_Mips_64: in getRelocType()
303 case Mips::fixup_Mips_26: in getRelocType()
307 case Mips::fixup_Mips_GOT: in getRelocType()
309 case Mips::fixup_Mips_HI16: in getRelocType()
311 case Mips::fixup_Mips_LO16: in getRelocType()
313 case Mips::fixup_Mips_TLSGD: in getRelocType()
365 case Mips::fixup_Mips_SUB: in getRelocType()
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H A DMipsABIFlagsSection.h33 Mips::AFL_REG GPRSize = Mips::AFL_REG_NONE;
35 Mips::AFL_REG CPR1Size = Mips::AFL_REG_NONE;
37 Mips::AFL_REG CPR2Size = Mips::AFL_REG_NONE;
39 Mips::AFL_EXT ISAExtension = Mips::AFL_EXT_NONE;
128 GPRSize = P.isGP64bit() ? Mips::AFL_REG_64 : Mips::AFL_REG_32; in setGPRSizeFromPredicates()
136 CPR1Size = Mips::AFL_REG_128; in setCPR1SizeFromPredicates()
138 CPR1Size = P.isFP64bit() ? Mips::AFL_REG_64 : Mips::AFL_REG_32; in setCPR1SizeFromPredicates()
153 ASESet |= Mips::AFL_ASE_DSP; in setASESetFromPredicates()
157 ASESet |= Mips::AFL_ASE_MSA; in setASESetFromPredicates()
163 ASESet |= Mips::AFL_ASE_MT; in setASESetFromPredicates()
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H A DMipsTargetStreamer.cpp245 emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI); in emitEmptyDelaySlot()
247 emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI); in emitEmptyDelaySlot()
253 emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI); in emitNop()
255 emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI); in emitNop()
261 emitLoadWithImmOffset(Mips::LW, Mips::GP, Mips::SP, Offset, Mips::GP, IDLoc, in emitGPRestore()
1188 emitStoreWithImmOffset(Mips::SW, Mips::GP, Mips::SP, Offset, GetATReg, IDLoc, in emitDirectiveCpRestore()
1209 emitRRR(Mips::OR64, RegOrOffset, Mips::GP, Mips::ZERO, SMLoc(), &STI); in emitDirectiveCpsetup()
1212 emitRRI(Mips::SD, Mips::GP, Mips::SP, RegOrOffset, SMLoc(), &STI); in emitDirectiveCpsetup()
1228 emitRRX(Mips::ADDiu, Mips::GP, Mips::GP, MCOperand::createExpr(LoExpr), in emitDirectiveCpsetup()
1245 emitRRX(Mips::ADDiu, Mips::GP, Mips::GP, MCOperand::createExpr(LoExpr), in emitDirectiveCpsetup()
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/freebsd-12.1/contrib/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp120 Mips::FeatureMips1, Mips::FeatureMips2, Mips::FeatureMips3,
125 Mips::FeatureMips64, Mips::FeatureMips64r2, Mips::FeatureMips64r3,
126 Mips::FeatureMips64r5, Mips::FeatureMips64r6, Mips::FeatureCnMips,
127 Mips::FeatureFP64Bit, Mips::FeatureGP64Bit, Mips::FeatureNaN2008
2043 TOut.emitRRX(Mips::LW, Mips::T9, Mips::GP, in processInstruction()
2045 TOut.emitRRX(Mips::ADDiu, Mips::T9, Mips::T9, in processInstruction()
2068 TOut.emitRRX(ABI.ArePtrs64bit() ? Mips::LD : Mips::LW, Mips::T9, Mips::GP, in processInstruction()
2511 case Mips::ORi: case Mips::ORi_MM: case Mips::ORi64: in tryExpandInstruction()
3818 TOut.emitRRX(Mips::BNE, Mips::ZERO, Mips::ZERO, in expandCondBranches()
3825 TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO, in expandCondBranches()
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/freebsd-12.1/contrib/llvm/lib/Target/Mips/InstPrinter/
H A DMipsInstPrinter.cpp37 const char* Mips::MipsFCCToString(Mips::CondCode CC) { in MipsFCCToString()
84 case Mips::RDHWR: in printInst()
89 case Mips::Save16: in printInst()
119 case Mips::RDHWR: in printInst()
222 case Mips::BEQ: in printAlias()
232 case Mips::BNE: in printAlias()
242 case Mips::BC1T: in printAlias()
245 case Mips::BC1F: in printAlias()
248 case Mips::JALR: in printAlias()
254 case Mips::NOR: in printAlias()
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/freebsd-12.1/contrib/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp1719 case Mips::LD_B: in DecodeMSA128Mem()
1720 case Mips::ST_B: in DecodeMSA128Mem()
1723 case Mips::LD_H: in DecodeMSA128Mem()
1724 case Mips::ST_H: in DecodeMSA128Mem()
1727 case Mips::LD_W: in DecodeMSA128Mem()
1728 case Mips::ST_W: in DecodeMSA128Mem()
1731 case Mips::LD_D: in DecodeMSA128Mem()
1732 case Mips::ST_D: in DecodeMSA128Mem()
2407 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, in DecodeRegListOperand()
2408 Mips::S6, Mips::S7, Mips::FP}; in DecodeRegListOperand()
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