Lines Matching refs:Mips
306 Opc = Mips::AND; in emitLogicalOp()
309 Opc = Mips::OR; in emitLogicalOp()
312 Opc = Mips::XOR; in emitLogicalOp()
330 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLogicalOp()
346 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in fastMaterializeAlloca()
347 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu), in fastMaterializeAlloca()
360 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeInt()
370 unsigned Opc = Mips::ADDiu; in materialize32BitInt()
371 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
374 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
382 emitInst(Mips::LUi, TmpReg).addImm(Hi); in materialize32BitInt()
383 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo); in materialize32BitInt()
385 emitInst(Mips::LUi, ResultReg).addImm(Hi); in materialize32BitInt()
395 const TargetRegisterClass *RC = &Mips::FGR32RegClass; in materializeFP()
397 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass); in materializeFP()
398 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
401 const TargetRegisterClass *RC = &Mips::AFGR64RegClass; in materializeFP()
403 unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass); in materializeFP()
405 materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass); in materializeFP()
406 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1); in materializeFP()
416 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeGV()
423 emitInst(Mips::LW, DestReg) in materializeGV()
429 emitInst(Mips::ADDiu, TempReg) in materializeGV()
438 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeExternalCallSym()
440 emitInst(Mips::LW, DestReg) in materializeExternalCallSym()
654 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
655 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
656 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
660 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
661 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
662 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg); in emitCmp()
666 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
669 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
672 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
673 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
674 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
678 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
679 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
680 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
684 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
687 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
690 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
691 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
692 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
696 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
697 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
698 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
716 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32; in emitCmp()
717 CondMovOpc = Mips::MOVT_I; in emitCmp()
720 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32; in emitCmp()
721 CondMovOpc = Mips::MOVF_I; in emitCmp()
724 Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32; in emitCmp()
725 CondMovOpc = Mips::MOVT_I; in emitCmp()
728 Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32; in emitCmp()
729 CondMovOpc = Mips::MOVT_I; in emitCmp()
732 Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32; in emitCmp()
733 CondMovOpc = Mips::MOVF_I; in emitCmp()
736 Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32; in emitCmp()
737 CondMovOpc = Mips::MOVF_I; in emitCmp()
742 unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass); in emitCmp()
743 unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass); in emitCmp()
744 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0); in emitCmp()
745 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1); in emitCmp()
746 emitInst(Opc).addReg(Mips::FCC0, RegState::Define).addReg(LeftReg) in emitCmp()
750 .addReg(Mips::FCC0) in emitCmp()
766 ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLoad()
767 Opc = Mips::LW; in emitLoad()
770 ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLoad()
771 Opc = Mips::LHu; in emitLoad()
774 ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLoad()
775 Opc = Mips::LBu; in emitLoad()
780 ResultReg = createResultReg(&Mips::FGR32RegClass); in emitLoad()
781 Opc = Mips::LWC1; in emitLoad()
786 ResultReg = createResultReg(&Mips::AFGR64RegClass); in emitLoad()
787 Opc = Mips::LDC1; in emitLoad()
822 Opc = Mips::SB; in emitStore()
825 Opc = Mips::SH; in emitStore()
828 Opc = Mips::SW; in emitStore()
833 Opc = Mips::SWC1; in emitStore()
838 Opc = Mips::SDC1; in emitStore()
963 ZExtCondReg = createResultReg(&Mips::GPR32RegClass); in selectBranch()
980 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ)) in selectBranch()
989 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in selectCmp()
1013 unsigned DestReg = createResultReg(&Mips::AFGR64RegClass); in selectFPExt()
1014 emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg); in selectFPExt()
1035 CondMovOpc = Mips::MOVN_I_I; in selectSelect()
1036 RC = &Mips::GPR32RegClass; in selectSelect()
1038 CondMovOpc = Mips::MOVN_I_S; in selectSelect()
1039 RC = &Mips::FGR32RegClass; in selectSelect()
1041 CondMovOpc = Mips::MOVN_I_D32; in selectSelect()
1042 RC = &Mips::AFGR64RegClass; in selectSelect()
1055 unsigned ZExtCondReg = createResultReg(&Mips::GPR32RegClass); in selectSelect()
1090 unsigned DestReg = createResultReg(&Mips::FGR32RegClass); in selectFPTrunc()
1094 emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg); in selectFPTrunc()
1128 unsigned DestReg = createResultReg(&Mips::GPR32RegClass); in selectFPToInt()
1129 unsigned TempReg = createResultReg(&Mips::FGR32RegClass); in selectFPToInt()
1130 unsigned Opc = (SrcVT == MVT::f32) ? Mips::TRUNC_W_S : Mips::TRUNC_W_D32; in selectFPToInt()
1134 emitInst(Mips::MFC1, DestReg).addReg(TempReg); in selectFPToInt()
1153 emitInst(Mips::ADJCALLSTACKDOWN).addImm(16).addImm(0); in processCallArgs()
1164 VA.convertToReg(Mips::F12); in processCallArgs()
1166 VA.convertToReg(Mips::D6); in processCallArgs()
1171 VA.convertToReg(Mips::F14); in processCallArgs()
1173 VA.convertToReg(Mips::D7); in processCallArgs()
1182 VA.convertToReg(Mips::A0); in processCallArgs()
1185 VA.convertToReg(Mips::A1); in processCallArgs()
1188 VA.convertToReg(Mips::A2); in processCallArgs()
1191 VA.convertToReg(Mips::A3); in processCallArgs()
1258 Addr.setReg(Mips::SP); in processCallArgs()
1277 emitInst(Mips::ADJCALLSTACKUP).addImm(16).addImm(0); in finishCall()
1329 std::array<MCPhysReg, 4> GPR32ArgRegs = {{Mips::A0, Mips::A1, Mips::A2, in fastLowerArguments()
1330 Mips::A3}}; in fastLowerArguments()
1331 std::array<MCPhysReg, 2> FGR32ArgRegs = {{Mips::F12, Mips::F14}}; in fastLowerArguments()
1332 std::array<MCPhysReg, 2> AFGR64ArgRegs = {{Mips::D6, Mips::D7}}; in fastLowerArguments()
1387 Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++); in fastLowerArguments()
1407 Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++); in fastLowerArguments()
1424 Allocation.emplace_back(&Mips::FGR32RegClass, *NextFGR32++); in fastLowerArguments()
1443 Allocation.emplace_back(&Mips::AFGR64RegClass, *NextAFGR64++); in fastLowerArguments()
1555 emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress); in fastLowerCall()
1557 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR), in fastLowerCall()
1558 Mips::RA).addReg(Mips::T9); in fastLowerCall()
1598 unsigned DestReg = createResultReg(&Mips::GPR32RegClass); in fastLowerIntrinsicCall()
1603 emitInst(Mips::WSBH, DestReg).addReg(SrcReg); in fastLowerIntrinsicCall()
1609 TempReg[i] = createResultReg(&Mips::GPR32RegClass); in fastLowerIntrinsicCall()
1613 emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8); in fastLowerIntrinsicCall()
1614 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8); in fastLowerIntrinsicCall()
1615 emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]); in fastLowerIntrinsicCall()
1616 emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF); in fastLowerIntrinsicCall()
1622 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in fastLowerIntrinsicCall()
1623 emitInst(Mips::WSBH, TempReg).addReg(SrcReg); in fastLowerIntrinsicCall()
1624 emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16); in fastLowerIntrinsicCall()
1630 TempReg[i] = createResultReg(&Mips::GPR32RegClass); in fastLowerIntrinsicCall()
1635 emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8); in fastLowerIntrinsicCall()
1636 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24); in fastLowerIntrinsicCall()
1637 emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00); in fastLowerIntrinsicCall()
1638 emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]); in fastLowerIntrinsicCall()
1640 emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00); in fastLowerIntrinsicCall()
1641 emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8); in fastLowerIntrinsicCall()
1643 emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24); in fastLowerIntrinsicCall()
1644 emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]); in fastLowerIntrinsicCall()
1645 emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]); in fastLowerIntrinsicCall()
1769 MachineInstrBuilder MIB = emitInst(Mips::RetRA); in selectRet()
1819 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in selectIntExt()
1840 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitIntSExt32r1()
1841 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt); in emitIntSExt32r1()
1842 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt); in emitIntSExt32r1()
1852 emitInst(Mips::SEB, DestReg).addReg(SrcReg); in emitIntSExt32r2()
1855 emitInst(Mips::SEH, DestReg).addReg(SrcReg); in emitIntSExt32r2()
1888 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm); in emitIntZExt()
1908 unsigned DestReg = createResultReg(&Mips::GPR32RegClass); in emitIntExt()
1928 DivOpc = Mips::SDIV; in selectDivRem()
1932 DivOpc = Mips::UDIV; in selectDivRem()
1942 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7); in selectDivRem()
1944 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in selectDivRem()
1949 ? Mips::MFHI in selectDivRem()
1950 : Mips::MFLO; in selectDivRem()
1963 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in selectShift()
1975 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in selectShift()
1994 Opcode = Mips::SLL; in selectShift()
1997 Opcode = Mips::SRA; in selectShift()
2000 Opcode = Mips::SRL; in selectShift()
2017 Opcode = Mips::SLLV; in selectShift()
2020 Opcode = Mips::SRAV; in selectShift()
2023 Opcode = Mips::SRLV; in selectShift()
2101 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in getRegEnsuringSimpleIntegerWidening()
2112 materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass); in simplifyAddress()
2113 unsigned DestReg = createResultReg(&Mips::GPR32RegClass); in simplifyAddress()
2114 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg()); in simplifyAddress()
2130 if (MachineInstOpcode == Mips::MUL) { in fastEmitInst_rr()
2138 .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead) in fastEmitInst_rr()
2139 .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead); in fastEmitInst_rr()
2149 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo, in createFastISel()