30     return STI.isPositionIndependent() ? Mips::B_MM : Mips::J_MM;  in getUnconditionalBranch()
31   return STI.isPositionIndependent() ? Mips::B : Mips::J;  in getUnconditionalBranch()
50   if ((Opc == Mips::LW)   || (Opc == Mips::LD)   ||  in isLoadFromStackSlot()
51       (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {  in isLoadFromStackSlot()
72   if ((Opc == Mips::SW)   || (Opc == Mips::SD)   ||  in isStoreToStackSlot()
73       (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) {  in isStoreToStackSlot()
91   if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.  in copyPhysReg()
92     if (Mips::GPR32RegClass.contains(SrcReg)) {  in copyPhysReg()
94         Opc = Mips::MOVE16_MM;  in copyPhysReg()
96         Opc = Mips::OR, ZeroReg = Mips::ZERO;  in copyPhysReg()
97     } else if (Mips::CCRRegClass.contains(SrcReg))  in copyPhysReg()
98       Opc = Mips::CFC1;  in copyPhysReg()
99     else if (Mips::FGR32RegClass.contains(SrcReg))  in copyPhysReg()
100       Opc = Mips::MFC1;  in copyPhysReg()
101     else if (Mips::HI32RegClass.contains(SrcReg)) {  in copyPhysReg()
102       Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;  in copyPhysReg()
104     } else if (Mips::LO32RegClass.contains(SrcReg)) {  in copyPhysReg()
105       Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;  in copyPhysReg()
107     } else if (Mips::HI32DSPRegClass.contains(SrcReg))  in copyPhysReg()
108       Opc = Mips::MFHI_DSP;  in copyPhysReg()
109     else if (Mips::LO32DSPRegClass.contains(SrcReg))  in copyPhysReg()
110       Opc = Mips::MFLO_DSP;  in copyPhysReg()
111     else if (Mips::DSPCCRegClass.contains(SrcReg)) {  in copyPhysReg()
112       BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)  in copyPhysReg()
116     else if (Mips::MSACtrlRegClass.contains(SrcReg))  in copyPhysReg()
117       Opc = Mips::CFCMSA;  in copyPhysReg()
119   else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.  in copyPhysReg()
120     if (Mips::CCRRegClass.contains(DestReg))  in copyPhysReg()
121       Opc = Mips::CTC1;  in copyPhysReg()
122     else if (Mips::FGR32RegClass.contains(DestReg))  in copyPhysReg()
123       Opc = Mips::MTC1;  in copyPhysReg()
124     else if (Mips::HI32RegClass.contains(DestReg))  in copyPhysReg()
125       Opc = Mips::MTHI, DestReg = 0;  in copyPhysReg()
126     else if (Mips::LO32RegClass.contains(DestReg))  in copyPhysReg()
127       Opc = Mips::MTLO, DestReg = 0;  in copyPhysReg()
128     else if (Mips::HI32DSPRegClass.contains(DestReg))  in copyPhysReg()
129       Opc = Mips::MTHI_DSP;  in copyPhysReg()
130     else if (Mips::LO32DSPRegClass.contains(DestReg))  in copyPhysReg()
131       Opc = Mips::MTLO_DSP;  in copyPhysReg()
132     else if (Mips::DSPCCRegClass.contains(DestReg)) {  in copyPhysReg()
133       BuildMI(MBB, I, DL, get(Mips::WRDSP))  in copyPhysReg()
137     } else if (Mips::MSACtrlRegClass.contains(DestReg)) {  in copyPhysReg()
138       BuildMI(MBB, I, DL, get(Mips::CTCMSA))  in copyPhysReg()
144   else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))  in copyPhysReg()
145     Opc = Mips::FMOV_S;  in copyPhysReg()
146   else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))  in copyPhysReg()
147     Opc = Mips::FMOV_D32;  in copyPhysReg()
148   else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))  in copyPhysReg()
149     Opc = Mips::FMOV_D64;  in copyPhysReg()
150   else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.  in copyPhysReg()
151     if (Mips::GPR64RegClass.contains(SrcReg))  in copyPhysReg()
152       Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;  in copyPhysReg()
153     else if (Mips::HI64RegClass.contains(SrcReg))  in copyPhysReg()
154       Opc = Mips::MFHI64, SrcReg = 0;  in copyPhysReg()
155     else if (Mips::LO64RegClass.contains(SrcReg))  in copyPhysReg()
156       Opc = Mips::MFLO64, SrcReg = 0;  in copyPhysReg()
157     else if (Mips::FGR64RegClass.contains(SrcReg))  in copyPhysReg()
158       Opc = Mips::DMFC1;  in copyPhysReg()
160   else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.  in copyPhysReg()
161     if (Mips::HI64RegClass.contains(DestReg))  in copyPhysReg()
162       Opc = Mips::MTHI64, DestReg = 0;  in copyPhysReg()
163     else if (Mips::LO64RegClass.contains(DestReg))  in copyPhysReg()
164       Opc = Mips::MTLO64, DestReg = 0;  in copyPhysReg()
165     else if (Mips::FGR64RegClass.contains(DestReg))  in copyPhysReg()
166       Opc = Mips::DMTC1;  in copyPhysReg()
168   else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg  in copyPhysReg()
169     if (Mips::MSA128BRegClass.contains(SrcReg))  in copyPhysReg()
170       Opc = Mips::MOVE_V;  in copyPhysReg()
191   case Mips::OR_MM:  in isORCopyInst()
192   case Mips::OR:  in isORCopyInst()
193     if (MI.getOperand(2).getReg() == Mips::ZERO)  in isORCopyInst()
196   case Mips::OR64:  in isORCopyInst()
197     if (MI.getOperand(2).getReg() == Mips::ZERO_64)  in isORCopyInst()
210   case Mips::WRDSP:  in isReadOrWriteToDSPReg()
211   case Mips::WRDSP_MM:  in isReadOrWriteToDSPReg()
214   case Mips::RDDSP:  in isReadOrWriteToDSPReg()
215   case Mips::RDDSP_MM:  in isReadOrWriteToDSPReg()
260   if (Mips::GPR32RegClass.hasSubClassEq(RC))  in storeRegToStack()
261     Opc = Mips::SW;  in storeRegToStack()
262   else if (Mips::GPR64RegClass.hasSubClassEq(RC))  in storeRegToStack()
263     Opc = Mips::SD;  in storeRegToStack()
264   else if (Mips::ACC64RegClass.hasSubClassEq(RC))  in storeRegToStack()
265     Opc = Mips::STORE_ACC64;  in storeRegToStack()
266   else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))  in storeRegToStack()
267     Opc = Mips::STORE_ACC64DSP;  in storeRegToStack()
268   else if (Mips::ACC128RegClass.hasSubClassEq(RC))  in storeRegToStack()
269     Opc = Mips::STORE_ACC128;  in storeRegToStack()
270   else if (Mips::DSPCCRegClass.hasSubClassEq(RC))  in storeRegToStack()
271     Opc = Mips::STORE_CCOND_DSP;  in storeRegToStack()
272   else if (Mips::FGR32RegClass.hasSubClassEq(RC))  in storeRegToStack()
273     Opc = Mips::SWC1;  in storeRegToStack()
274   else if (Mips::AFGR64RegClass.hasSubClassEq(RC))  in storeRegToStack()
275     Opc = Mips::SDC1;  in storeRegToStack()
276   else if (Mips::FGR64RegClass.hasSubClassEq(RC))  in storeRegToStack()
277     Opc = Mips::SDC164;  in storeRegToStack()
279     Opc = Mips::ST_B;  in storeRegToStack()
282     Opc = Mips::ST_H;  in storeRegToStack()
285     Opc = Mips::ST_W;  in storeRegToStack()
288     Opc = Mips::ST_D;  in storeRegToStack()
289   else if (Mips::LO32RegClass.hasSubClassEq(RC))  in storeRegToStack()
290     Opc = Mips::SW;  in storeRegToStack()
291   else if (Mips::LO64RegClass.hasSubClassEq(RC))  in storeRegToStack()
292     Opc = Mips::SD;  in storeRegToStack()
293   else if (Mips::HI32RegClass.hasSubClassEq(RC))  in storeRegToStack()
294     Opc = Mips::SW;  in storeRegToStack()
295   else if (Mips::HI64RegClass.hasSubClassEq(RC))  in storeRegToStack()
296     Opc = Mips::SD;  in storeRegToStack()
297   else if (Mips::DSPRRegClass.hasSubClassEq(RC))  in storeRegToStack()
298     Opc = Mips::SWDSP;  in storeRegToStack()
304     if (Mips::HI32RegClass.hasSubClassEq(RC)) {  in storeRegToStack()
305       BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0);  in storeRegToStack()
306       SrcReg = Mips::K0;  in storeRegToStack()
307     } else if (Mips::HI64RegClass.hasSubClassEq(RC)) {  in storeRegToStack()
308       BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64);  in storeRegToStack()
309       SrcReg = Mips::K0_64;  in storeRegToStack()
310     } else if (Mips::LO32RegClass.hasSubClassEq(RC)) {  in storeRegToStack()
311       BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0);  in storeRegToStack()
312       SrcReg = Mips::K0;  in storeRegToStack()
313     } else if (Mips::LO64RegClass.hasSubClassEq(RC)) {  in storeRegToStack()
314       BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64);  in storeRegToStack()
315       SrcReg = Mips::K0_64;  in storeRegToStack()
335                          (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 ||  in loadRegFromStack()
336                           DestReg == Mips::HI0 || DestReg == Mips::HI0_64);  in loadRegFromStack()
338   if (Mips::GPR32RegClass.hasSubClassEq(RC))  in loadRegFromStack()
339     Opc = Mips::LW;  in loadRegFromStack()
340   else if (Mips::GPR64RegClass.hasSubClassEq(RC))  in loadRegFromStack()
341     Opc = Mips::LD;  in loadRegFromStack()
342   else if (Mips::ACC64RegClass.hasSubClassEq(RC))  in loadRegFromStack()
343     Opc = Mips::LOAD_ACC64;  in loadRegFromStack()
344   else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))  in loadRegFromStack()
345     Opc = Mips::LOAD_ACC64DSP;  in loadRegFromStack()
346   else if (Mips::ACC128RegClass.hasSubClassEq(RC))  in loadRegFromStack()
347     Opc = Mips::LOAD_ACC128;  in loadRegFromStack()
348   else if (Mips::DSPCCRegClass.hasSubClassEq(RC))  in loadRegFromStack()
349     Opc = Mips::LOAD_CCOND_DSP;  in loadRegFromStack()
350   else if (Mips::FGR32RegClass.hasSubClassEq(RC))  in loadRegFromStack()
351     Opc = Mips::LWC1;  in loadRegFromStack()
352   else if (Mips::AFGR64RegClass.hasSubClassEq(RC))  in loadRegFromStack()
353     Opc = Mips::LDC1;  in loadRegFromStack()
354   else if (Mips::FGR64RegClass.hasSubClassEq(RC))  in loadRegFromStack()
355     Opc = Mips::LDC164;  in loadRegFromStack()
357     Opc = Mips::LD_B;  in loadRegFromStack()
360     Opc = Mips::LD_H;  in loadRegFromStack()
363     Opc = Mips::LD_W;  in loadRegFromStack()
366     Opc = Mips::LD_D;  in loadRegFromStack()
367   else if (Mips::HI32RegClass.hasSubClassEq(RC))  in loadRegFromStack()
368     Opc = Mips::LW;  in loadRegFromStack()
369   else if (Mips::HI64RegClass.hasSubClassEq(RC))  in loadRegFromStack()
370     Opc = Mips::LD;  in loadRegFromStack()
371   else if (Mips::LO32RegClass.hasSubClassEq(RC))  in loadRegFromStack()
372     Opc = Mips::LW;  in loadRegFromStack()
373   else if (Mips::LO64RegClass.hasSubClassEq(RC))  in loadRegFromStack()
374     Opc = Mips::LD;  in loadRegFromStack()
375   else if (Mips::DSPRRegClass.hasSubClassEq(RC))  in loadRegFromStack()
376     Opc = Mips::LWDSP;  in loadRegFromStack()
388     unsigned Reg = Mips::K0;  in loadRegFromStack()
389     unsigned LdOp = Mips::MTLO;  in loadRegFromStack()
390     if (DestReg == Mips::HI0)  in loadRegFromStack()
391       LdOp = Mips::MTHI;  in loadRegFromStack()
394       Reg = Mips::K0_64;  in loadRegFromStack()
395       if (DestReg == Mips::HI0_64)  in loadRegFromStack()
396         LdOp = Mips::MTHI64;  in loadRegFromStack()
398         LdOp = Mips::MTLO64;  in loadRegFromStack()
417   case Mips::RetRA:  in expandPostRAPseudo()
420   case Mips::ERet:  in expandPostRAPseudo()
423   case Mips::PseudoMFHI:  in expandPostRAPseudo()
424     expandPseudoMFHiLo(MBB, MI, Mips::MFHI);  in expandPostRAPseudo()
426   case Mips::PseudoMFHI_MM:  in expandPostRAPseudo()
427     expandPseudoMFHiLo(MBB, MI, Mips::MFHI16_MM);  in expandPostRAPseudo()
429   case Mips::PseudoMFLO:  in expandPostRAPseudo()
430     expandPseudoMFHiLo(MBB, MI, Mips::MFLO);  in expandPostRAPseudo()
432   case Mips::PseudoMFLO_MM:  in expandPostRAPseudo()
433     expandPseudoMFHiLo(MBB, MI, Mips::MFLO16_MM);  in expandPostRAPseudo()
435   case Mips::PseudoMFHI64:  in expandPostRAPseudo()
436     expandPseudoMFHiLo(MBB, MI, Mips::MFHI64);  in expandPostRAPseudo()
438   case Mips::PseudoMFLO64:  in expandPostRAPseudo()
439     expandPseudoMFHiLo(MBB, MI, Mips::MFLO64);  in expandPostRAPseudo()
441   case Mips::PseudoMTLOHI:  in expandPostRAPseudo()
442     expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI, false);  in expandPostRAPseudo()
444   case Mips::PseudoMTLOHI64:  in expandPostRAPseudo()
445     expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64, false);  in expandPostRAPseudo()
447   case Mips::PseudoMTLOHI_DSP:  in expandPostRAPseudo()
448     expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true);  in expandPostRAPseudo()
450   case Mips::PseudoMTLOHI_MM:  in expandPostRAPseudo()
451     expandPseudoMTLoHi(MBB, MI, Mips::MTLO_MM, Mips::MTHI_MM, false);  in expandPostRAPseudo()
453   case Mips::PseudoCVT_S_W:  in expandPostRAPseudo()
454     expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);  in expandPostRAPseudo()
456   case Mips::PseudoCVT_D32_W:  in expandPostRAPseudo()
457     Opc = isMicroMips ? Mips::CVT_D32_W_MM : Mips::CVT_D32_W;  in expandPostRAPseudo()
458     expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, false);  in expandPostRAPseudo()
460   case Mips::PseudoCVT_S_L:  in expandPostRAPseudo()
461     expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);  in expandPostRAPseudo()
463   case Mips::PseudoCVT_D64_W:  in expandPostRAPseudo()
464     Opc = isMicroMips ? Mips::CVT_D64_W_MM : Mips::CVT_D64_W;  in expandPostRAPseudo()
465     expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, true);  in expandPostRAPseudo()
467   case Mips::PseudoCVT_D64_L:  in expandPostRAPseudo()
468     expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);  in expandPostRAPseudo()
470   case Mips::BuildPairF64:  in expandPostRAPseudo()
473   case Mips::BuildPairF64_64:  in expandPostRAPseudo()
476   case Mips::ExtractElementF64:  in expandPostRAPseudo()
479   case Mips::ExtractElementF64_64:  in expandPostRAPseudo()
482   case Mips::MIPSeh_return32:  in expandPostRAPseudo()
483   case Mips::MIPSeh_return64:  in expandPostRAPseudo()
497   case Mips::BEQ:    return Mips::BNE;  in getOppositeBranchOpc()
498   case Mips::BEQ_MM: return Mips::BNE_MM;  in getOppositeBranchOpc()
499   case Mips::BNE:    return Mips::BEQ;  in getOppositeBranchOpc()
500   case Mips::BNE_MM: return Mips::BEQ_MM;  in getOppositeBranchOpc()
501   case Mips::BGTZ:   return Mips::BLEZ;  in getOppositeBranchOpc()
502   case Mips::BGEZ:   return Mips::BLTZ;  in getOppositeBranchOpc()
503   case Mips::BLTZ:   return Mips::BGEZ;  in getOppositeBranchOpc()
504   case Mips::BLEZ:   return Mips::BGTZ;  in getOppositeBranchOpc()
505   case Mips::BGTZ_MM:   return Mips::BLEZ_MM;  in getOppositeBranchOpc()
506   case Mips::BGEZ_MM:   return Mips::BLTZ_MM;  in getOppositeBranchOpc()
507   case Mips::BLTZ_MM:   return Mips::BGEZ_MM;  in getOppositeBranchOpc()
508   case Mips::BLEZ_MM:   return Mips::BGTZ_MM;  in getOppositeBranchOpc()
509   case Mips::BEQ64:  return Mips::BNE64;  in getOppositeBranchOpc()
510   case Mips::BNE64:  return Mips::BEQ64;  in getOppositeBranchOpc()
511   case Mips::BGTZ64: return Mips::BLEZ64;  in getOppositeBranchOpc()
512   case Mips::BGEZ64: return Mips::BLTZ64;  in getOppositeBranchOpc()
513   case Mips::BLTZ64: return Mips::BGEZ64;  in getOppositeBranchOpc()
514   case Mips::BLEZ64: return Mips::BGTZ64;  in getOppositeBranchOpc()
515   case Mips::BC1T:   return Mips::BC1F;  in getOppositeBranchOpc()
516   case Mips::BC1F:   return Mips::BC1T;  in getOppositeBranchOpc()
517   case Mips::BC1T_MM:   return Mips::BC1F_MM;  in getOppositeBranchOpc()
518   case Mips::BC1F_MM:   return Mips::BC1T_MM;  in getOppositeBranchOpc()
519   case Mips::BEQZ16_MM: return Mips::BNEZ16_MM;  in getOppositeBranchOpc()
520   case Mips::BNEZ16_MM: return Mips::BEQZ16_MM;  in getOppositeBranchOpc()
521   case Mips::BEQZC_MM:  return Mips::BNEZC_MM;  in getOppositeBranchOpc()
522   case Mips::BNEZC_MM:  return Mips::BEQZC_MM;  in getOppositeBranchOpc()
523   case Mips::BEQZC:  return Mips::BNEZC;  in getOppositeBranchOpc()
524   case Mips::BNEZC:  return Mips::BEQZC;  in getOppositeBranchOpc()
525   case Mips::BLEZC:  return Mips::BGTZC;  in getOppositeBranchOpc()
526   case Mips::BGEZC:  return Mips::BLTZC;  in getOppositeBranchOpc()
527   case Mips::BGEC:   return Mips::BLTC;  in getOppositeBranchOpc()
528   case Mips::BGTZC:  return Mips::BLEZC;  in getOppositeBranchOpc()
529   case Mips::BLTZC:  return Mips::BGEZC;  in getOppositeBranchOpc()
530   case Mips::BLTC:   return Mips::BGEC;  in getOppositeBranchOpc()
531   case Mips::BGEUC:  return Mips::BLTUC;  in getOppositeBranchOpc()
532   case Mips::BLTUC:  return Mips::BGEUC;  in getOppositeBranchOpc()
533   case Mips::BEQC:   return Mips::BNEC;  in getOppositeBranchOpc()
534   case Mips::BNEC:   return Mips::BEQC;  in getOppositeBranchOpc()
535   case Mips::BC1EQZ: return Mips::BC1NEZ;  in getOppositeBranchOpc()
536   case Mips::BC1NEZ: return Mips::BC1EQZ;  in getOppositeBranchOpc()
537   case Mips::BEQZC_MMR6:  return Mips::BNEZC_MMR6;  in getOppositeBranchOpc()
538   case Mips::BNEZC_MMR6:  return Mips::BEQZC_MMR6;  in getOppositeBranchOpc()
539   case Mips::BLEZC_MMR6:  return Mips::BGTZC_MMR6;  in getOppositeBranchOpc()
540   case Mips::BGEZC_MMR6:  return Mips::BLTZC_MMR6;  in getOppositeBranchOpc()
541   case Mips::BGEC_MMR6:   return Mips::BLTC_MMR6;  in getOppositeBranchOpc()
542   case Mips::BGTZC_MMR6:  return Mips::BLEZC_MMR6;  in getOppositeBranchOpc()
543   case Mips::BLTZC_MMR6:  return Mips::BGEZC_MMR6;  in getOppositeBranchOpc()
544   case Mips::BLTC_MMR6:   return Mips::BGEC_MMR6;  in getOppositeBranchOpc()
545   case Mips::BGEUC_MMR6:  return Mips::BLTUC_MMR6;  in getOppositeBranchOpc()
546   case Mips::BLTUC_MMR6:  return Mips::BGEUC_MMR6;  in getOppositeBranchOpc()
547   case Mips::BEQC_MMR6:   return Mips::BNEC_MMR6;  in getOppositeBranchOpc()
548   case Mips::BNEC_MMR6:   return Mips::BEQC_MMR6;  in getOppositeBranchOpc()
549   case Mips::BC1EQZC_MMR6: return Mips::BC1NEZC_MMR6;  in getOppositeBranchOpc()
550   case Mips::BC1NEZC_MMR6: return Mips::BC1EQZC_MMR6;  in getOppositeBranchOpc()
551   case Mips::BEQZC64:  return Mips::BNEZC64;  in getOppositeBranchOpc()
552   case Mips::BNEZC64:  return Mips::BEQZC64;  in getOppositeBranchOpc()
553   case Mips::BEQC64:   return Mips::BNEC64;  in getOppositeBranchOpc()
554   case Mips::BNEC64:   return Mips::BEQC64;  in getOppositeBranchOpc()
555   case Mips::BGEC64:   return Mips::BLTC64;  in getOppositeBranchOpc()
556   case Mips::BGEUC64:  return Mips::BLTUC64;  in getOppositeBranchOpc()
557   case Mips::BLTC64:   return Mips::BGEC64;  in getOppositeBranchOpc()
558   case Mips::BLTUC64:  return Mips::BGEUC64;  in getOppositeBranchOpc()
559   case Mips::BGTZC64:  return Mips::BLEZC64;  in getOppositeBranchOpc()
560   case Mips::BGEZC64:  return Mips::BLTZC64;  in getOppositeBranchOpc()
561   case Mips::BLTZC64:  return Mips::BGEZC64;  in getOppositeBranchOpc()
562   case Mips::BLEZC64:  return Mips::BGTZC64;  in getOppositeBranchOpc()
563   case Mips::BBIT0:  return Mips::BBIT1;  in getOppositeBranchOpc()
564   case Mips::BBIT1:  return Mips::BBIT0;  in getOppositeBranchOpc()
565   case Mips::BBIT032:  return Mips::BBIT132;  in getOppositeBranchOpc()
566   case Mips::BBIT132:  return Mips::BBIT032;  in getOppositeBranchOpc()
567   case Mips::BZ_B:   return Mips::BNZ_B;  in getOppositeBranchOpc()
568   case Mips::BZ_H:   return Mips::BNZ_H;  in getOppositeBranchOpc()
569   case Mips::BZ_W:   return Mips::BNZ_W;  in getOppositeBranchOpc()
570   case Mips::BZ_D:   return Mips::BNZ_D;  in getOppositeBranchOpc()
571   case Mips::BZ_V:   return Mips::BNZ_V;  in getOppositeBranchOpc()
572   case Mips::BNZ_B:  return Mips::BZ_B;  in getOppositeBranchOpc()
573   case Mips::BNZ_H:  return Mips::BZ_H;  in getOppositeBranchOpc()
574   case Mips::BNZ_W:  return Mips::BZ_W;  in getOppositeBranchOpc()
575   case Mips::BNZ_D:  return Mips::BZ_D;  in getOppositeBranchOpc()
576   case Mips::BNZ_V:  return Mips::BZ_V;  in getOppositeBranchOpc()
617   unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;  in loadImmediate()
618   unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;  in loadImmediate()
620     &Mips::GPR64RegClass : &Mips::GPR32RegClass;  in loadImmediate()
652   return (Opc == Mips::BEQ    || Opc == Mips::BEQ_MM || Opc == Mips::BNE    ||  in getAnalyzableBrOpc()
653           Opc == Mips::BNE_MM || Opc == Mips::BGTZ   || Opc == Mips::BGEZ   ||  in getAnalyzableBrOpc()
654           Opc == Mips::BLTZ   || Opc == Mips::BLEZ   || Opc == Mips::BEQ64  ||  in getAnalyzableBrOpc()
655           Opc == Mips::BNE64  || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 ||  in getAnalyzableBrOpc()
656           Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T   ||  in getAnalyzableBrOpc()
657           Opc == Mips::BC1F   || Opc == Mips::B      || Opc == Mips::J      ||  in getAnalyzableBrOpc()
658           Opc == Mips::J_MM   || Opc == Mips::B_MM   || Opc == Mips::BEQZC_MM ||  in getAnalyzableBrOpc()
659           Opc == Mips::BNEZC_MM || Opc == Mips::BEQC || Opc == Mips::BNEC   ||  in getAnalyzableBrOpc()
660           Opc == Mips::BLTC   || Opc == Mips::BGEC   || Opc == Mips::BLTUC  ||  in getAnalyzableBrOpc()
661           Opc == Mips::BGEUC  || Opc == Mips::BGTZC  || Opc == Mips::BLEZC  ||  in getAnalyzableBrOpc()
662           Opc == Mips::BGEZC  || Opc == Mips::BLTZC  || Opc == Mips::BEQZC  ||  in getAnalyzableBrOpc()
663           Opc == Mips::BNEZC  || Opc == Mips::BEQZC64 || Opc == Mips::BNEZC64 ||  in getAnalyzableBrOpc()
664           Opc == Mips::BEQC64 || Opc == Mips::BNEC64 || Opc == Mips::BGEC64 ||  in getAnalyzableBrOpc()
665           Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 || Opc == Mips::BLTUC64 ||  in getAnalyzableBrOpc()
666           Opc == Mips::BGTZC64 || Opc == Mips::BGEZC64 ||  in getAnalyzableBrOpc()
667           Opc == Mips::BLTZC64 || Opc == Mips::BLEZC64 || Opc == Mips::BC ||  in getAnalyzableBrOpc()
668           Opc == Mips::BBIT0 || Opc == Mips::BBIT1 || Opc == Mips::BBIT032 ||  in getAnalyzableBrOpc()
669           Opc == Mips::BBIT132 ||  Opc == Mips::BC_MMR6 ||  in getAnalyzableBrOpc()
670           Opc == Mips::BEQC_MMR6 || Opc == Mips::BNEC_MMR6 ||  in getAnalyzableBrOpc()
671           Opc == Mips::BLTC_MMR6 || Opc == Mips::BGEC_MMR6 ||  in getAnalyzableBrOpc()
672           Opc == Mips::BLTUC_MMR6 || Opc == Mips::BGEUC_MMR6 ||  in getAnalyzableBrOpc()
673           Opc == Mips::BGTZC_MMR6 || Opc == Mips::BLEZC_MMR6 ||  in getAnalyzableBrOpc()
674           Opc == Mips::BGEZC_MMR6 || Opc == Mips::BLTZC_MMR6 ||  in getAnalyzableBrOpc()
675           Opc == Mips::BEQZC_MMR6 || Opc == Mips::BNEZC_MMR6) ? Opc : 0;  in getAnalyzableBrOpc()
683     MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64))  in expandRetRA()
684               .addReg(Mips::RA_64, RegState::Undef);  in expandRetRA()
686     MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn))  in expandRetRA()
687               .addReg(Mips::RA, RegState::Undef);  in expandRetRA()
698   BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET));  in expandERet()
739     unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);  in expandPseudoMTLoHi()
740     unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);  in expandPseudoMTLoHi()
764     TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);  in expandCvtFPInt()
767     DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);  in expandCvtFPInt()
783   unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;  in expandExtractElementF64()
794   if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) {  in expandExtractElementF64()
808             get(isMicroMips ? (FP64 ? Mips::MFHC1_D64_MM : Mips::MFHC1_D32_MM)  in expandExtractElementF64()
809                             : (FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32)),  in expandExtractElementF64()
813     BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);  in expandExtractElementF64()
821   const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);  in expandBuildPairF64()
848   BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))  in expandBuildPairF64()
864             get(isMicroMips ? (FP64 ? Mips::MTHC1_D64_MM : Mips::MTHC1_D32_MM)  in expandBuildPairF64()
865                             : (FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32)),  in expandBuildPairF64()
872     BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))  in expandBuildPairF64()
883   unsigned SP = Subtarget.isGP64bit() ? Mips::SP_64 : Mips::SP;  in expandEhReturn()
884   unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA;  in expandEhReturn()
885   unsigned T9 = Subtarget.isGP64bit() ? Mips::T9_64 : Mips::T9;  in expandEhReturn()
886   unsigned ZERO = Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;  in expandEhReturn()