122     TmpInst0.setOpcode(Mips::JALR64);  in emitPseudoIndirectBranch()
127       TmpInst0.setOpcode(Mips::JRC16_MMR6);  in emitPseudoIndirectBranch()
129       TmpInst0.setOpcode(Mips::JALR);  in emitPseudoIndirectBranch()
134     TmpInst0.setOpcode(Mips::JR_MM);  in emitPseudoIndirectBranch()
137     TmpInst0.setOpcode(Mips::JR);  in emitPseudoIndirectBranch()
143     unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;  in emitPseudoIndirectBranch()
203   if (InConstantPool && Opc != Mips::CONSTPOOL_ENTRY) {  in EmitInstruction()
207   if (Opc == Mips::CONSTPOOL_ENTRY) {  in EmitInstruction()
235   case Mips::PATCHABLE_FUNCTION_ENTER:  in EmitInstruction()
238   case Mips::PATCHABLE_FUNCTION_EXIT:  in EmitInstruction()
241   case Mips::PATCHABLE_TAIL_CALL:  in EmitInstruction()
259     if (I->getOpcode() == Mips::PseudoReturn ||  in EmitInstruction()
260         I->getOpcode() == Mips::PseudoReturn64 ||  in EmitInstruction()
261         I->getOpcode() == Mips::PseudoIndirectBranch ||  in EmitInstruction()
262         I->getOpcode() == Mips::PseudoIndirectBranch64 ||  in EmitInstruction()
263         I->getOpcode() == Mips::TAILCALLREG ||  in EmitInstruction()
264         I->getOpcode() == Mips::TAILCALLREG64) {  in EmitInstruction()
333   unsigned CPURegSize = TRI->getRegSizeInBits(Mips::GPR32RegClass) / 8;  in printSavedRegsBitmask()
334   unsigned FGR32RegSize = TRI->getRegSizeInBits(Mips::FGR32RegClass) / 8;  in printSavedRegsBitmask()
335   unsigned AFGR64RegSize = TRI->getRegSizeInBits(Mips::AFGR64RegClass) / 8;  in printSavedRegsBitmask()
345     if (Mips::FGR32RegClass.contains(Reg)) {  in printSavedRegsBitmask()
348     } else if (Mips::AFGR64RegClass.contains(Reg)) {  in printSavedRegsBitmask()
352     } else if (Mips::GPR32RegClass.contains(Reg))  in printSavedRegsBitmask()
731   case Mips::SWM32_MM:  in printMemOperand()
732   case Mips::LWM32_MM:  in printMemOperand()
756   O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());  in printFCCOperand()
851   I.setOpcode(Mips::JAL);  in EmitJal()
874   if (Opcode == Mips::MTC1) {  in EmitInstrRegReg()
914   unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;  in EmitSwapFPIntParams()
917     EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);  in EmitSwapFPIntParams()
920     EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F14, LE);  in EmitSwapFPIntParams()
923     EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);  in EmitSwapFPIntParams()
924     EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);  in EmitSwapFPIntParams()
927     EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);  in EmitSwapFPIntParams()
930     EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);  in EmitSwapFPIntParams()
931     EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);  in EmitSwapFPIntParams()
934     EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);  in EmitSwapFPIntParams()
935     EmitInstrRegReg(STI, MovOpc, Mips::A2, Mips::F14);  in EmitSwapFPIntParams()
947   unsigned MovOpc = Mips::MFC1;  in EmitSwapFPIntRetval()
950     EmitInstrRegReg(STI, MovOpc, Mips::V0, Mips::F0);  in EmitSwapFPIntRetval()
953     EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);  in EmitSwapFPIntRetval()
956     EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);  in EmitSwapFPIntRetval()
959     EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);  in EmitSwapFPIntRetval()
960     EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F2, Mips::F3, LE);  in EmitSwapFPIntRetval()
1089   EmitInstrRegRegReg(*STI, Mips::OR, Mips::S2, Mips::RA, Mips::ZERO);  in EmitFPCallStub()
1104   EmitInstrReg(*STI, Mips::JR, Mips::S2);  in EmitFPCallStub()
1206   EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::BEQ)  in EmitSled()
1207                                    .addReg(Mips::ZERO)  in EmitSled()
1208                                    .addReg(Mips::ZERO)  in EmitSled()
1212     EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::SLL)  in EmitSled()
1213                                      .addReg(Mips::ZERO)  in EmitSled()
1214                                      .addReg(Mips::ZERO)  in EmitSled()
1221                    MCInstBuilder(Mips::ADDiu)  in EmitSled()
1222                        .addReg(Mips::T9)  in EmitSled()
1223                        .addReg(Mips::T9)  in EmitSled()
1290   return (Opcode == Mips::LONG_BRANCH_LUi  in isLongBranchPseudo()
1291           || Opcode == Mips::LONG_BRANCH_LUi2Op  in isLongBranchPseudo()
1292           || Opcode == Mips::LONG_BRANCH_LUi2Op_64  in isLongBranchPseudo()
1293           || Opcode == Mips::LONG_BRANCH_ADDiu  in isLongBranchPseudo()
1294           || Opcode == Mips::LONG_BRANCH_ADDiu2Op  in isLongBranchPseudo()
1295           || Opcode == Mips::LONG_BRANCH_DADDiu  in isLongBranchPseudo()
1296           || Opcode == Mips::LONG_BRANCH_DADDiu2Op);  in isLongBranchPseudo()