Lines Matching refs:Mips
51 if (Mips::ACC64RegClass.contains(Src)) in getMFHiLoOpc()
52 return std::make_pair((unsigned)Mips::PseudoMFHI, in getMFHiLoOpc()
53 (unsigned)Mips::PseudoMFLO); in getMFHiLoOpc()
55 if (Mips::ACC64DSPRegClass.contains(Src)) in getMFHiLoOpc()
56 return std::make_pair((unsigned)Mips::MFHI_DSP, (unsigned)Mips::MFLO_DSP); in getMFHiLoOpc()
58 if (Mips::ACC128RegClass.contains(Src)) in getMFHiLoOpc()
59 return std::make_pair((unsigned)Mips::PseudoMFHI64, in getMFHiLoOpc()
60 (unsigned)Mips::PseudoMFLO64); in getMFHiLoOpc()
118 case Mips::LOAD_CCOND_DSP: in expandInstr()
121 case Mips::STORE_CCOND_DSP: in expandInstr()
124 case Mips::LOAD_ACC64: in expandInstr()
125 case Mips::LOAD_ACC64DSP: in expandInstr()
128 case Mips::LOAD_ACC128: in expandInstr()
131 case Mips::STORE_ACC64: in expandInstr()
132 expandStoreACC(MBB, I, Mips::PseudoMFHI, Mips::PseudoMFLO, 4); in expandInstr()
134 case Mips::STORE_ACC64DSP: in expandInstr()
135 expandStoreACC(MBB, I, Mips::MFHI_DSP, Mips::MFLO_DSP, 4); in expandInstr()
137 case Mips::STORE_ACC128: in expandInstr()
138 expandStoreACC(MBB, I, Mips::PseudoMFHI64, Mips::PseudoMFLO64, 8); in expandInstr()
140 case Mips::BuildPairF64: in expandInstr()
144 case Mips::BuildPairF64_64: in expandInstr()
148 case Mips::ExtractElementF64: in expandInstr()
152 case Mips::ExtractElementF64_64: in expandInstr()
211 unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandLoadACC()
212 unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandLoadACC()
269 unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandCopyACC()
270 unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandCopyACC()
307 && I->getOperand(3).getReg() == Mips::SP) { in expandBuildPairF64()
318 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in expandBuildPairF64()
320 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandBuildPairF64()
351 BuildMI(MBB, I, I->getDebugLoc(), TII.get(Mips::IMPLICIT_DEF), DstReg); in expandExtractElementF64()
372 && I->getOperand(3).getReg() == Mips::SP) { in expandExtractElementF64()
385 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandExtractElementF64()
386 const TargetRegisterClass *RC2 = &Mips::GPR32RegClass; in expandExtractElementF64()
420 unsigned AND = ABI.IsN64() ? Mips::AND64 : Mips::AND; in emitPrologue()
423 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitPrologue()
463 if (Mips::AFGR64RegClass.contains(Reg)) { in emitPrologue()
465 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true); in emitPrologue()
467 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true); in emitPrologue()
481 } else if (Mips::FGR64RegClass.contains(Reg)) { in emitPrologue()
552 unsigned BP = STI.isABI_N64() ? Mips::S7_64 : Mips::S7; in emitPrologue()
592 const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass; in emitInterruptPrologueStub()
598 MBB.addLiveIn(Mips::COP013); in emitInterruptPrologueStub()
599 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K0) in emitInterruptPrologueStub()
600 .addReg(Mips::COP013) in emitInterruptPrologueStub()
604 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EXT), Mips::K0) in emitInterruptPrologueStub()
605 .addReg(Mips::K0) in emitInterruptPrologueStub()
612 MBB.addLiveIn(Mips::COP014); in emitInterruptPrologueStub()
613 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1) in emitInterruptPrologueStub()
614 .addReg(Mips::COP014) in emitInterruptPrologueStub()
618 STI.getInstrInfo()->storeRegToStack(MBB, MBBI, Mips::K1, false, in emitInterruptPrologueStub()
623 MBB.addLiveIn(Mips::COP012); in emitInterruptPrologueStub()
624 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1) in emitInterruptPrologueStub()
625 .addReg(Mips::COP012) in emitInterruptPrologueStub()
629 STI.getInstrInfo()->storeRegToStack(MBB, MBBI, Mips::K1, false, in emitInterruptPrologueStub()
637 unsigned SrcReg = Mips::ZERO; in emitInterruptPrologueStub()
642 SrcReg = Mips::K0; in emitInterruptPrologueStub()
658 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1) in emitInterruptPrologueStub()
662 .addReg(Mips::K1) in emitInterruptPrologueStub()
666 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1) in emitInterruptPrologueStub()
667 .addReg(Mips::ZERO) in emitInterruptPrologueStub()
670 .addReg(Mips::K1) in emitInterruptPrologueStub()
675 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1) in emitInterruptPrologueStub()
676 .addReg(Mips::ZERO) in emitInterruptPrologueStub()
679 .addReg(Mips::K1) in emitInterruptPrologueStub()
683 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012) in emitInterruptPrologueStub()
684 .addReg(Mips::K1) in emitInterruptPrologueStub()
721 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitEpilogue()
755 const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass; in emitInterruptEpilogueStub()
758 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::DI), Mips::ZERO); in emitInterruptEpilogueStub()
759 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EHB)); in emitInterruptEpilogueStub()
762 STI.getInstrInfo()->loadRegFromStackSlot(MBB, MBBI, Mips::K1, in emitInterruptEpilogueStub()
765 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP014) in emitInterruptEpilogueStub()
766 .addReg(Mips::K1) in emitInterruptEpilogueStub()
770 STI.getInstrInfo()->loadRegFromStackSlot(MBB, MBBI, Mips::K1, in emitInterruptEpilogueStub()
773 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012) in emitInterruptEpilogueStub()
774 .addReg(Mips::K1) in emitInterruptEpilogueStub()
808 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64) in spillCalleeSavedRegisters()
815 bool IsLOHI = (Reg == Mips::LO0 || Reg == Mips::LO0_64 || in spillCalleeSavedRegisters()
816 Reg == Mips::HI0 || Reg == Mips::HI0_64); in spillCalleeSavedRegisters()
823 Op = (Reg == Mips::HI0) ? Mips::MFHI : Mips::MFLO; in spillCalleeSavedRegisters()
824 Reg = Mips::K0; in spillCalleeSavedRegisters()
826 Op = (Reg == Mips::HI0) ? Mips::MFHI64 : Mips::MFLO64; in spillCalleeSavedRegisters()
827 Reg = Mips::K0_64; in spillCalleeSavedRegisters()
829 BuildMI(MBB, MI, DL, TII.get(Op), Mips::K0) in spillCalleeSavedRegisters()
870 unsigned BP = ABI.IsN64() ? Mips::S7_64 : Mips::S7; in determineCalleeSaves()
894 Mips::GPR64RegClass : Mips::GPR32RegClass; in determineCalleeSaves()
911 ABI.ArePtrs64bit() ? Mips::GPR64RegClass : Mips::GPR32RegClass; in determineCalleeSaves()