Lines Matching refs:Mips
120 Mips::FeatureMips1, Mips::FeatureMips2, Mips::FeatureMips3,
121 Mips::FeatureMips3_32, Mips::FeatureMips3_32r2, Mips::FeatureMips4,
122 Mips::FeatureMips4_32, Mips::FeatureMips4_32r2, Mips::FeatureMips5,
123 Mips::FeatureMips5_32r2, Mips::FeatureMips32, Mips::FeatureMips32r2,
124 Mips::FeatureMips32r3, Mips::FeatureMips32r5, Mips::FeatureMips32r6,
125 Mips::FeatureMips64, Mips::FeatureMips64r2, Mips::FeatureMips64r3,
126 Mips::FeatureMips64r5, Mips::FeatureMips64r6, Mips::FeatureCnMips,
127 Mips::FeatureFP64Bit, Mips::FeatureGP64Bit, Mips::FeatureNaN2008
532 return getSTI().getFeatureBits()[Mips::FeatureGP64Bit]; in isGP64bit()
536 return getSTI().getFeatureBits()[Mips::FeatureFP64Bit]; in isFP64bit()
544 return getSTI().getFeatureBits()[Mips::FeatureFPXX]; in isABI_FPXX()
548 return !(getSTI().getFeatureBits()[Mips::FeatureNoOddSPReg]); in useOddSPReg()
552 return getSTI().getFeatureBits()[Mips::FeatureMicroMips]; in inMicroMipsMode()
556 return getSTI().getFeatureBits()[Mips::FeatureMips1]; in hasMips1()
560 return getSTI().getFeatureBits()[Mips::FeatureMips2]; in hasMips2()
564 return getSTI().getFeatureBits()[Mips::FeatureMips3]; in hasMips3()
568 return getSTI().getFeatureBits()[Mips::FeatureMips4]; in hasMips4()
572 return getSTI().getFeatureBits()[Mips::FeatureMips5]; in hasMips5()
576 return getSTI().getFeatureBits()[Mips::FeatureMips32]; in hasMips32()
580 return getSTI().getFeatureBits()[Mips::FeatureMips64]; in hasMips64()
584 return getSTI().getFeatureBits()[Mips::FeatureMips32r2]; in hasMips32r2()
588 return getSTI().getFeatureBits()[Mips::FeatureMips64r2]; in hasMips64r2()
592 return (getSTI().getFeatureBits()[Mips::FeatureMips32r3]); in hasMips32r3()
596 return (getSTI().getFeatureBits()[Mips::FeatureMips64r3]); in hasMips64r3()
600 return (getSTI().getFeatureBits()[Mips::FeatureMips32r5]); in hasMips32r5()
604 return (getSTI().getFeatureBits()[Mips::FeatureMips64r5]); in hasMips64r5()
608 return getSTI().getFeatureBits()[Mips::FeatureMips32r6]; in hasMips32r6()
612 return getSTI().getFeatureBits()[Mips::FeatureMips64r6]; in hasMips64r6()
616 return getSTI().getFeatureBits()[Mips::FeatureDSP]; in hasDSP()
620 return getSTI().getFeatureBits()[Mips::FeatureDSPR2]; in hasDSPR2()
624 return getSTI().getFeatureBits()[Mips::FeatureDSPR3]; in hasDSPR3()
628 return getSTI().getFeatureBits()[Mips::FeatureMSA]; in hasMSA()
632 return (getSTI().getFeatureBits()[Mips::FeatureCnMips]); in hasCnMips()
640 return getSTI().getFeatureBits()[Mips::FeatureMips16]; in inMips16Mode()
644 return getSTI().getFeatureBits()[Mips::FeatureUseTCCInDIV]; in useTraps()
648 return getSTI().getFeatureBits()[Mips::FeatureSoftFloat]; in useSoftFloat()
651 return getSTI().getFeatureBits()[Mips::FeatureMT]; in hasMT()
655 return getSTI().getFeatureBits()[Mips::FeatureCRC]; in hasCRC()
659 return getSTI().getFeatureBits()[Mips::FeatureVirt]; in hasVirt()
663 return getSTI().getFeatureBits()[Mips::FeatureGINV]; in hasGINV()
848 unsigned ClassID = Mips::GPR32RegClassID; in getGPR32Reg()
856 unsigned ClassID = Mips::GPR32RegClassID; in getGPRMM16Reg()
864 unsigned ClassID = Mips::GPR64RegClassID; in getGPR64Reg()
875 return RegIdx.RegInfo->getRegClass(Mips::AFGR64RegClassID) in getAFGR64Reg()
883 return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID) in getFGR64Reg()
891 return RegIdx.RegInfo->getRegClass(Mips::FGR32RegClassID) in getFGR32Reg()
899 return RegIdx.RegInfo->getRegClass(Mips::FGRH32RegClassID) in getFGRH32Reg()
907 return RegIdx.RegInfo->getRegClass(Mips::FCCRegClassID) in getFCCReg()
917 unsigned ClassID = Mips::MSA128BRegClassID; in getMSA128Reg()
925 unsigned ClassID = Mips::MSACtrlRegClassID; in getMSACtrlReg()
933 unsigned ClassID = Mips::COP0RegClassID; in getCOP0Reg()
941 unsigned ClassID = Mips::COP2RegClassID; in getCOP2Reg()
949 unsigned ClassID = Mips::COP3RegClassID; in getCOP3Reg()
957 unsigned ClassID = Mips::ACC64DSPRegClassID; in getACC64DSPReg()
965 unsigned ClassID = Mips::HI32DSPRegClassID; in getHI32DSPReg()
973 unsigned ClassID = Mips::LO32DSPRegClassID; in getLO32DSPReg()
981 unsigned ClassID = Mips::CCRRegClassID; in getCCRReg()
989 unsigned ClassID = Mips::HWRegsRegClassID; in getHWRegsReg()
1326 && getMemBase()->isRegIdx() && (getMemBase()->getGPR32Reg() == Mips::SP); in isMemWithUimmOffsetSP()
1332 && (getMemBase()->getGPR32Reg() == Mips::SP); in isMemWithUimmWordAlignedOffsetSP()
1338 && (getMemBase()->getGPR32Reg() == Mips::GP); in isMemWithSimmWordAlignedOffsetGP()
1371 if (!((R0 == Mips::S0 && R1 == Mips::RA) || in isRegList16()
1372 (R0 == Mips::S0_64 && R1 == Mips::RA_64))) in isRegList16()
1713 case Mips::BEQ_MM: in hasShortDelaySlot()
1714 case Mips::BNE_MM: in hasShortDelaySlot()
1715 case Mips::BLTZ_MM: in hasShortDelaySlot()
1716 case Mips::BGEZ_MM: in hasShortDelaySlot()
1717 case Mips::BLEZ_MM: in hasShortDelaySlot()
1718 case Mips::BGTZ_MM: in hasShortDelaySlot()
1719 case Mips::JRC16_MM: in hasShortDelaySlot()
1720 case Mips::JALS_MM: in hasShortDelaySlot()
1721 case Mips::JALRS_MM: in hasShortDelaySlot()
1722 case Mips::JALRS16_MM: in hasShortDelaySlot()
1723 case Mips::BGEZALS_MM: in hasShortDelaySlot()
1724 case Mips::BLTZALS_MM: in hasShortDelaySlot()
1726 case Mips::J_MM: in hasShortDelaySlot()
1787 case Mips::BBIT0: in processInstruction()
1788 case Mips::BBIT032: in processInstruction()
1789 case Mips::BBIT1: in processInstruction()
1790 case Mips::BBIT132: in processInstruction()
1794 case Mips::BEQ: in processInstruction()
1795 case Mips::BNE: in processInstruction()
1796 case Mips::BEQ_MM: in processInstruction()
1797 case Mips::BNE_MM: in processInstruction()
1808 case Mips::BGEZ: in processInstruction()
1809 case Mips::BGTZ: in processInstruction()
1810 case Mips::BLEZ: in processInstruction()
1811 case Mips::BLTZ: in processInstruction()
1812 case Mips::BGEZAL: in processInstruction()
1813 case Mips::BLTZAL: in processInstruction()
1814 case Mips::BC1F: in processInstruction()
1815 case Mips::BC1T: in processInstruction()
1816 case Mips::BGEZ_MM: in processInstruction()
1817 case Mips::BGTZ_MM: in processInstruction()
1818 case Mips::BLEZ_MM: in processInstruction()
1819 case Mips::BLTZ_MM: in processInstruction()
1820 case Mips::BGEZAL_MM: in processInstruction()
1821 case Mips::BLTZAL_MM: in processInstruction()
1822 case Mips::BC1F_MM: in processInstruction()
1823 case Mips::BC1T_MM: in processInstruction()
1824 case Mips::BC1EQZC_MMR6: in processInstruction()
1825 case Mips::BC1NEZC_MMR6: in processInstruction()
1826 case Mips::BC2EQZC_MMR6: in processInstruction()
1827 case Mips::BC2NEZC_MMR6: in processInstruction()
1838 case Mips::BGEC: case Mips::BGEC_MMR6: in processInstruction()
1839 case Mips::BLTC: case Mips::BLTC_MMR6: in processInstruction()
1840 case Mips::BGEUC: case Mips::BGEUC_MMR6: in processInstruction()
1841 case Mips::BLTUC: case Mips::BLTUC_MMR6: in processInstruction()
1842 case Mips::BEQC: case Mips::BEQC_MMR6: in processInstruction()
1843 case Mips::BNEC: case Mips::BNEC_MMR6: in processInstruction()
1853 case Mips::BLEZC: case Mips::BLEZC_MMR6: in processInstruction()
1854 case Mips::BGEZC: case Mips::BGEZC_MMR6: in processInstruction()
1855 case Mips::BGTZC: case Mips::BGTZC_MMR6: in processInstruction()
1856 case Mips::BLTZC: case Mips::BLTZC_MMR6: in processInstruction()
1866 case Mips::BEQZC: case Mips::BEQZC_MMR6: in processInstruction()
1867 case Mips::BNEZC: case Mips::BNEZC_MMR6: in processInstruction()
1877 case Mips::BEQZ16_MM: in processInstruction()
1878 case Mips::BEQZC16_MMR6: in processInstruction()
1879 case Mips::BNEZ16_MM: in processInstruction()
1880 case Mips::BNEZC16_MMR6: in processInstruction()
1895 if (hasMips32r6() && Inst.getOpcode() == Mips::SSNOP) { in processInstruction()
1910 case Mips::BBIT0: in processInstruction()
1911 case Mips::BBIT032: in processInstruction()
1912 case Mips::BBIT1: in processInstruction()
1913 case Mips::BBIT132: in processInstruction()
1920 if (Imm < 0 || Imm > (Opcode == Mips::BBIT0 || in processInstruction()
1921 Opcode == Mips::BBIT1 ? 63 : 31)) in processInstruction()
1924 Inst.setOpcode(Opcode == Mips::BBIT0 ? Mips::BBIT032 in processInstruction()
1925 : Mips::BBIT132); in processInstruction()
1930 case Mips::SEQi: in processInstruction()
1931 case Mips::SNEi: in processInstruction()
1955 case Mips::SDivIMacro: in processInstruction()
1956 case Mips::UDivIMacro: in processInstruction()
1957 case Mips::DSDivIMacro: in processInstruction()
1958 case Mips::DUDivIMacro: in processInstruction()
1960 if (Inst.getOperand(1).getReg() == Mips::ZERO || in processInstruction()
1961 Inst.getOperand(1).getReg() == Mips::ZERO_64) in processInstruction()
1967 case Mips::DSDIV: in processInstruction()
1968 case Mips::SDIV: in processInstruction()
1969 case Mips::UDIV: in processInstruction()
1970 case Mips::DUDIV: in processInstruction()
1971 case Mips::UDIV_MM: in processInstruction()
1972 case Mips::SDIV_MM: in processInstruction()
1976 case Mips::SDivMacro: in processInstruction()
1977 case Mips::DSDivMacro: in processInstruction()
1978 case Mips::UDivMacro: in processInstruction()
1979 case Mips::DUDivMacro: in processInstruction()
1980 case Mips::DIV: in processInstruction()
1981 case Mips::DIVU: in processInstruction()
1982 case Mips::DDIV: in processInstruction()
1983 case Mips::DDIVU: in processInstruction()
1984 case Mips::DIVU_MMR6: in processInstruction()
1985 case Mips::DIV_MMR6: in processInstruction()
1986 if (Inst.getOperand(SecondOp).getReg() == Mips::ZERO || in processInstruction()
1987 Inst.getOperand(SecondOp).getReg() == Mips::ZERO_64) { in processInstruction()
1988 if (Inst.getOperand(FirstOp).getReg() == Mips::ZERO || in processInstruction()
1989 Inst.getOperand(FirstOp).getReg() == Mips::ZERO_64) in processInstruction()
1998 if ((Inst.getOpcode() == Mips::J || Inst.getOpcode() == Mips::J_MM) && in processInstruction()
2001 BInst.setOpcode(inMicroMipsMode() ? Mips::BEQ_MM : Mips::BEQ); in processInstruction()
2002 BInst.addOperand(MCOperand::createReg(Mips::ZERO)); in processInstruction()
2003 BInst.addOperand(MCOperand::createReg(Mips::ZERO)); in processInstruction()
2010 if ((Inst.getOpcode() == Mips::JAL || Inst.getOpcode() == Mips::JAL_MM) && in processInstruction()
2043 TOut.emitRRX(Mips::LW, Mips::T9, Mips::GP, in processInstruction()
2045 TOut.emitRRX(Mips::ADDiu, Mips::T9, Mips::T9, in processInstruction()
2056 TOut.emitRRX(ABI.ArePtrs64bit() ? Mips::LD : Mips::LW, Mips::T9, in processInstruction()
2057 Mips::GP, MCOperand::createExpr(GotDispRelocExpr), IDLoc, in processInstruction()
2068 TOut.emitRRX(ABI.ArePtrs64bit() ? Mips::LD : Mips::LW, Mips::T9, Mips::GP, in processInstruction()
2074 JalrInst.setOpcode(Mips::JALRS_MM); in processInstruction()
2076 JalrInst.setOpcode(inMicroMipsMode() ? Mips::JALR_MM : Mips::JALR); in processInstruction()
2077 JalrInst.addOperand(MCOperand::createReg(Mips::RA)); in processInstruction()
2078 JalrInst.addOperand(MCOperand::createReg(Mips::T9)); in processInstruction()
2136 if (MCID.mayLoad() && Inst.getOpcode() != Mips::LWP_MM) { in processInstruction()
2149 Mips::GPRMM16RegClassID).contains(DstReg.getReg()) && in processInstruction()
2150 (BaseReg.getReg() == Mips::GP || in processInstruction()
2151 BaseReg.getReg() == Mips::GP_64)) { in processInstruction()
2153 TOut.emitRRI(Mips::LWGP_MM, DstReg.getReg(), Mips::GP, MemOffset, in processInstruction()
2170 case Mips::ADDIUSP_MM: in processInstruction()
2179 case Mips::SLL16_MM: in processInstruction()
2180 case Mips::SRL16_MM: in processInstruction()
2188 case Mips::LI16_MM: in processInstruction()
2196 case Mips::ADDIUR2_MM: in processInstruction()
2205 case Mips::ANDI16_MM: in processInstruction()
2215 case Mips::LBU16_MM: in processInstruction()
2223 case Mips::SB16_MM: in processInstruction()
2224 case Mips::SB16_MMR6: in processInstruction()
2232 case Mips::LHU16_MM: in processInstruction()
2233 case Mips::SH16_MM: in processInstruction()
2234 case Mips::SH16_MMR6: in processInstruction()
2242 case Mips::LW16_MM: in processInstruction()
2243 case Mips::SW16_MM: in processInstruction()
2244 case Mips::SW16_MMR6: in processInstruction()
2252 case Mips::ADDIUPC_MM: in processInstruction()
2260 case Mips::LWP_MM: in processInstruction()
2261 case Mips::SWP_MM: in processInstruction()
2262 if (Inst.getOperand(0).getReg() == Mips::RA) in processInstruction()
2265 case Mips::MOVEP_MM: in processInstruction()
2266 case Mips::MOVEP_MMR6: { in processInstruction()
2269 bool RegPair = ((R0 == Mips::A1 && R1 == Mips::A2) || in processInstruction()
2270 (R0 == Mips::A1 && R1 == Mips::A3) || in processInstruction()
2271 (R0 == Mips::A2 && R1 == Mips::A3) || in processInstruction()
2272 (R0 == Mips::A0 && R1 == Mips::S5) || in processInstruction()
2273 (R0 == Mips::A0 && R1 == Mips::S6) || in processInstruction()
2274 (R0 == Mips::A0 && R1 == Mips::A1) || in processInstruction()
2275 (R0 == Mips::A0 && R1 == Mips::A2) || in processInstruction()
2276 (R0 == Mips::A0 && R1 == Mips::A3)); in processInstruction()
2315 if ((Inst.getOpcode() == Mips::JalOneReg || in processInstruction()
2316 Inst.getOpcode() == Mips::JalTwoReg || ExpandedJalSym) && in processInstruction()
2341 case Mips::LoadImm32: in tryExpandInstruction()
2343 case Mips::LoadImm64: in tryExpandInstruction()
2345 case Mips::LoadAddrImm32: in tryExpandInstruction()
2346 case Mips::LoadAddrImm64: in tryExpandInstruction()
2351 return expandLoadAddress(Inst.getOperand(0).getReg(), Mips::NoRegister, in tryExpandInstruction()
2353 Inst.getOpcode() == Mips::LoadAddrImm32, IDLoc, in tryExpandInstruction()
2357 case Mips::LoadAddrReg32: in tryExpandInstruction()
2358 case Mips::LoadAddrReg64: in tryExpandInstruction()
2366 Inst.getOpcode() == Mips::LoadAddrReg32, IDLoc, in tryExpandInstruction()
2370 case Mips::B_MM_Pseudo: in tryExpandInstruction()
2371 case Mips::B_MMR6_Pseudo: in tryExpandInstruction()
2374 case Mips::SWM_MM: in tryExpandInstruction()
2375 case Mips::LWM_MM: in tryExpandInstruction()
2378 case Mips::JalOneReg: in tryExpandInstruction()
2379 case Mips::JalTwoReg: in tryExpandInstruction()
2381 case Mips::BneImm: in tryExpandInstruction()
2382 case Mips::BeqImm: in tryExpandInstruction()
2383 case Mips::BEQLImmMacro: in tryExpandInstruction()
2384 case Mips::BNELImmMacro: in tryExpandInstruction()
2386 case Mips::BLT: in tryExpandInstruction()
2387 case Mips::BLE: in tryExpandInstruction()
2388 case Mips::BGE: in tryExpandInstruction()
2389 case Mips::BGT: in tryExpandInstruction()
2390 case Mips::BLTU: in tryExpandInstruction()
2391 case Mips::BLEU: in tryExpandInstruction()
2392 case Mips::BGEU: in tryExpandInstruction()
2393 case Mips::BGTU: in tryExpandInstruction()
2394 case Mips::BLTL: in tryExpandInstruction()
2395 case Mips::BLEL: in tryExpandInstruction()
2396 case Mips::BGEL: in tryExpandInstruction()
2397 case Mips::BGTL: in tryExpandInstruction()
2398 case Mips::BLTUL: in tryExpandInstruction()
2399 case Mips::BLEUL: in tryExpandInstruction()
2400 case Mips::BGEUL: in tryExpandInstruction()
2401 case Mips::BGTUL: in tryExpandInstruction()
2402 case Mips::BLTImmMacro: in tryExpandInstruction()
2403 case Mips::BLEImmMacro: in tryExpandInstruction()
2404 case Mips::BGEImmMacro: in tryExpandInstruction()
2405 case Mips::BGTImmMacro: in tryExpandInstruction()
2406 case Mips::BLTUImmMacro: in tryExpandInstruction()
2407 case Mips::BLEUImmMacro: in tryExpandInstruction()
2408 case Mips::BGEUImmMacro: in tryExpandInstruction()
2409 case Mips::BGTUImmMacro: in tryExpandInstruction()
2410 case Mips::BLTLImmMacro: in tryExpandInstruction()
2411 case Mips::BLELImmMacro: in tryExpandInstruction()
2412 case Mips::BGELImmMacro: in tryExpandInstruction()
2413 case Mips::BGTLImmMacro: in tryExpandInstruction()
2414 case Mips::BLTULImmMacro: in tryExpandInstruction()
2415 case Mips::BLEULImmMacro: in tryExpandInstruction()
2416 case Mips::BGEULImmMacro: in tryExpandInstruction()
2417 case Mips::BGTULImmMacro: in tryExpandInstruction()
2419 case Mips::SDivMacro: in tryExpandInstruction()
2420 case Mips::SDivIMacro: in tryExpandInstruction()
2421 case Mips::SRemMacro: in tryExpandInstruction()
2422 case Mips::SRemIMacro: in tryExpandInstruction()
2425 case Mips::DSDivMacro: in tryExpandInstruction()
2426 case Mips::DSDivIMacro: in tryExpandInstruction()
2427 case Mips::DSRemMacro: in tryExpandInstruction()
2428 case Mips::DSRemIMacro: in tryExpandInstruction()
2431 case Mips::UDivMacro: in tryExpandInstruction()
2432 case Mips::UDivIMacro: in tryExpandInstruction()
2433 case Mips::URemMacro: in tryExpandInstruction()
2434 case Mips::URemIMacro: in tryExpandInstruction()
2437 case Mips::DUDivMacro: in tryExpandInstruction()
2438 case Mips::DUDivIMacro: in tryExpandInstruction()
2439 case Mips::DURemMacro: in tryExpandInstruction()
2440 case Mips::DURemIMacro: in tryExpandInstruction()
2443 case Mips::PseudoTRUNC_W_S: in tryExpandInstruction()
2446 case Mips::PseudoTRUNC_W_D32: in tryExpandInstruction()
2449 case Mips::PseudoTRUNC_W_D: in tryExpandInstruction()
2453 case Mips::LoadImmSingleGPR: in tryExpandInstruction()
2457 case Mips::LoadImmSingleFGR: in tryExpandInstruction()
2461 case Mips::LoadImmDoubleGPR: in tryExpandInstruction()
2465 case Mips::LoadImmDoubleFGR: in tryExpandInstruction()
2469 case Mips::LoadImmDoubleFGR_32: in tryExpandInstruction()
2473 case Mips::Ulh: in tryExpandInstruction()
2475 case Mips::Ulhu: in tryExpandInstruction()
2477 case Mips::Ush: in tryExpandInstruction()
2479 case Mips::Ulw: in tryExpandInstruction()
2480 case Mips::Usw: in tryExpandInstruction()
2482 case Mips::NORImm: in tryExpandInstruction()
2483 case Mips::NORImm64: in tryExpandInstruction()
2485 case Mips::SLTImm64: in tryExpandInstruction()
2487 Inst.setOpcode(Mips::SLTi64); in tryExpandInstruction()
2491 case Mips::SLTUImm64: in tryExpandInstruction()
2493 Inst.setOpcode(Mips::SLTiu64); in tryExpandInstruction()
2497 case Mips::ADDi: case Mips::ADDi_MM: in tryExpandInstruction()
2498 case Mips::ADDiu: case Mips::ADDiu_MM: in tryExpandInstruction()
2499 case Mips::SLTi: case Mips::SLTi_MM: in tryExpandInstruction()
2500 case Mips::SLTiu: case Mips::SLTiu_MM: in tryExpandInstruction()
2510 case Mips::ANDi: case Mips::ANDi_MM: case Mips::ANDi64: in tryExpandInstruction()
2511 case Mips::ORi: case Mips::ORi_MM: case Mips::ORi64: in tryExpandInstruction()
2512 case Mips::XORi: case Mips::XORi_MM: case Mips::XORi64: in tryExpandInstruction()
2522 case Mips::ROL: in tryExpandInstruction()
2523 case Mips::ROR: in tryExpandInstruction()
2525 case Mips::ROLImm: in tryExpandInstruction()
2526 case Mips::RORImm: in tryExpandInstruction()
2528 case Mips::DROL: in tryExpandInstruction()
2529 case Mips::DROR: in tryExpandInstruction()
2531 case Mips::DROLImm: in tryExpandInstruction()
2532 case Mips::DRORImm: in tryExpandInstruction()
2534 case Mips::ABSMacro: in tryExpandInstruction()
2536 case Mips::MULImmMacro: in tryExpandInstruction()
2537 case Mips::DMULImmMacro: in tryExpandInstruction()
2539 case Mips::MULOMacro: in tryExpandInstruction()
2540 case Mips::DMULOMacro: in tryExpandInstruction()
2542 case Mips::MULOUMacro: in tryExpandInstruction()
2543 case Mips::DMULOUMacro: in tryExpandInstruction()
2545 case Mips::DMULMacro: in tryExpandInstruction()
2547 case Mips::LDMacro: in tryExpandInstruction()
2548 case Mips::SDMacro: in tryExpandInstruction()
2550 Inst.getOpcode() == Mips::LDMacro) in tryExpandInstruction()
2553 case Mips::SEQMacro: in tryExpandInstruction()
2555 case Mips::SEQIMacro: in tryExpandInstruction()
2557 case Mips::MFTC0: case Mips::MTTC0: in tryExpandInstruction()
2558 case Mips::MFTGPR: case Mips::MTTGPR: in tryExpandInstruction()
2559 case Mips::MFTLO: case Mips::MTTLO: in tryExpandInstruction()
2560 case Mips::MFTHI: case Mips::MTTHI: in tryExpandInstruction()
2561 case Mips::MFTACX: case Mips::MTTACX: in tryExpandInstruction()
2562 case Mips::MFTDSP: case Mips::MTTDSP: in tryExpandInstruction()
2563 case Mips::MFTC1: case Mips::MTTC1: in tryExpandInstruction()
2564 case Mips::MFTHC1: case Mips::MTTHC1: in tryExpandInstruction()
2565 case Mips::CFTC1: case Mips::CTTC1: in tryExpandInstruction()
2581 if (Opcode == Mips::JalOneReg) { in expandJalWithRegs()
2584 JalrInst.setOpcode(Mips::JALRS16_MM); in expandJalWithRegs()
2587 JalrInst.setOpcode(hasMips32r6() ? Mips::JALRC16_MMR6 : Mips::JALR16_MM); in expandJalWithRegs()
2590 JalrInst.setOpcode(Mips::JALR); in expandJalWithRegs()
2591 JalrInst.addOperand(MCOperand::createReg(Mips::RA)); in expandJalWithRegs()
2594 } else if (Opcode == Mips::JalTwoReg) { in expandJalWithRegs()
2597 JalrInst.setOpcode(Mips::JALRS_MM); in expandJalWithRegs()
2599 JalrInst.setOpcode(inMicroMipsMode() ? Mips::JALR_MM : Mips::JALR); in expandJalWithRegs()
2657 unsigned AdduOp = !Is32BitImm ? Mips::DADDu : Mips::ADDu; in loadImmediate()
2660 if (SrcReg != Mips::NoRegister) in loadImmediate()
2682 TOut.emitRRI(Mips::DADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI); in loadImmediate()
2686 TOut.emitRRI(Mips::ADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI); in loadImmediate()
2698 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI); in loadImmediate()
2713 TOut.emitRI(Mips::LUi, TmpReg, 0xffff, IDLoc, STI); in loadImmediate()
2714 TOut.emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, STI); in loadImmediate()
2722 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, STI); in loadImmediate()
2723 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI); in loadImmediate()
2725 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, STI); in loadImmediate()
2731 TOut.emitRI(Mips::LUi, TmpReg, Bits31To16, IDLoc, STI); in loadImmediate()
2733 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, STI); in loadImmediate()
2751 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, STI); in loadImmediate()
2752 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, ShiftAmount, IDLoc, STI); in loadImmediate()
2767 if (loadImmediate(ImmValue >> 32, TmpReg, Mips::NoRegister, true, false, in loadImmediate()
2779 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, ImmChunk, IDLoc, STI); in loadImmediate()
2804 if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister, in expandLoadImm()
2853 bool UseSrcReg = SrcReg != Mips::NoRegister; in loadAndAddSymbolAddress()
2870 if ((DstReg == Mips::T9 || DstReg == Mips::T9_64) && !UseSrcReg && in loadAndAddSymbolAddress()
2879 TOut.emitRRX(Mips::LW, DstReg, ABI.GetGlobalPtr(), in loadAndAddSymbolAddress()
2919 TOut.emitRRX(Mips::LW, TmpReg, ABI.GetGlobalPtr(), in loadAndAddSymbolAddress()
2923 TOut.emitRRX(Mips::ADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr), in loadAndAddSymbolAddress()
2927 TOut.emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
2946 if ((DstReg == Mips::T9 || DstReg == Mips::T9_64) && !UseSrcReg && in loadAndAddSymbolAddress()
2955 TOut.emitRRX(Mips::LD, DstReg, ABI.GetGlobalPtr(), in loadAndAddSymbolAddress()
2998 TOut.emitRRX(Mips::LD, TmpReg, ABI.GetGlobalPtr(), in loadAndAddSymbolAddress()
3002 TOut.emitRRX(Mips::DADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr), in loadAndAddSymbolAddress()
3006 TOut.emitRRR(Mips::DADDu, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3044 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc, in loadAndAddSymbolAddress()
3046 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, in loadAndAddSymbolAddress()
3048 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); in loadAndAddSymbolAddress()
3049 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(HiExpr), in loadAndAddSymbolAddress()
3051 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); in loadAndAddSymbolAddress()
3052 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr), in loadAndAddSymbolAddress()
3054 TOut.emitRRR(Mips::DADDu, DstReg, ATReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3071 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc, in loadAndAddSymbolAddress()
3073 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, STI); in loadAndAddSymbolAddress()
3074 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, in loadAndAddSymbolAddress()
3076 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr), in loadAndAddSymbolAddress()
3078 TOut.emitRRI(Mips::DSLL32, DstReg, DstReg, 0, IDLoc, STI); in loadAndAddSymbolAddress()
3079 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, ATReg, IDLoc, STI); in loadAndAddSymbolAddress()
3081 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3093 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc, in loadAndAddSymbolAddress()
3095 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, in loadAndAddSymbolAddress()
3097 TOut.emitRRI(Mips::DSLL, DstReg, DstReg, 16, IDLoc, STI); in loadAndAddSymbolAddress()
3098 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, in loadAndAddSymbolAddress()
3100 TOut.emitRRI(Mips::DSLL, DstReg, DstReg, 16, IDLoc, STI); in loadAndAddSymbolAddress()
3101 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, in loadAndAddSymbolAddress()
3104 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3138 TOut.emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(HiExpr), IDLoc, STI); in loadAndAddSymbolAddress()
3139 TOut.emitRRX(Mips::ADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr), in loadAndAddSymbolAddress()
3143 TOut.emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3155 if (MipsMCRegisterClasses[Mips::FGR32RegClassID].contains(Reg)) in nextReg()
3156 return Reg == (unsigned)Mips::F31 ? (unsigned)Mips::F0 : Reg + 1; in nextReg()
3159 case Mips::ZERO: return Mips::AT; in nextReg()
3160 case Mips::AT: return Mips::V0; in nextReg()
3161 case Mips::V0: return Mips::V1; in nextReg()
3162 case Mips::V1: return Mips::A0; in nextReg()
3163 case Mips::A0: return Mips::A1; in nextReg()
3164 case Mips::A1: return Mips::A2; in nextReg()
3165 case Mips::A2: return Mips::A3; in nextReg()
3166 case Mips::A3: return Mips::T0; in nextReg()
3167 case Mips::T0: return Mips::T1; in nextReg()
3168 case Mips::T1: return Mips::T2; in nextReg()
3169 case Mips::T2: return Mips::T3; in nextReg()
3170 case Mips::T3: return Mips::T4; in nextReg()
3171 case Mips::T4: return Mips::T5; in nextReg()
3172 case Mips::T5: return Mips::T6; in nextReg()
3173 case Mips::T6: return Mips::T7; in nextReg()
3174 case Mips::T7: return Mips::S0; in nextReg()
3175 case Mips::S0: return Mips::S1; in nextReg()
3176 case Mips::S1: return Mips::S2; in nextReg()
3177 case Mips::S2: return Mips::S3; in nextReg()
3178 case Mips::S3: return Mips::S4; in nextReg()
3179 case Mips::S4: return Mips::S5; in nextReg()
3180 case Mips::S5: return Mips::S6; in nextReg()
3181 case Mips::S6: return Mips::S7; in nextReg()
3182 case Mips::S7: return Mips::T8; in nextReg()
3183 case Mips::T8: return Mips::T9; in nextReg()
3184 case Mips::T9: return Mips::K0; in nextReg()
3185 case Mips::K0: return Mips::K1; in nextReg()
3186 case Mips::K1: return Mips::GP; in nextReg()
3187 case Mips::GP: return Mips::SP; in nextReg()
3188 case Mips::SP: return Mips::FP; in nextReg()
3189 case Mips::FP: return Mips::RA; in nextReg()
3190 case Mips::RA: return Mips::ZERO; in nextReg()
3191 case Mips::D0: return Mips::F1; in nextReg()
3192 case Mips::D1: return Mips::F3; in nextReg()
3193 case Mips::D2: return Mips::F5; in nextReg()
3194 case Mips::D3: return Mips::F7; in nextReg()
3195 case Mips::D4: return Mips::F9; in nextReg()
3196 case Mips::D5: return Mips::F11; in nextReg()
3197 case Mips::D6: return Mips::F13; in nextReg()
3198 case Mips::D7: return Mips::F15; in nextReg()
3199 case Mips::D8: return Mips::F17; in nextReg()
3200 case Mips::D9: return Mips::F19; in nextReg()
3201 case Mips::D10: return Mips::F21; in nextReg()
3202 case Mips::D11: return Mips::F23; in nextReg()
3203 case Mips::D12: return Mips::F25; in nextReg()
3204 case Mips::D13: return Mips::F27; in nextReg()
3205 case Mips::D14: return Mips::F29; in nextReg()
3206 case Mips::D15: return Mips::F31; in nextReg()
3229 TOut.emitRRX(Mips::LW, ATReg, Mips::GP, MCOperand::createExpr(GotExpr), in emitPartialAddress()
3232 TOut.emitRRX(Mips::LD, ATReg, Mips::GP, MCOperand::createExpr(GotExpr), in emitPartialAddress()
3248 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, STI); in emitPartialAddress()
3259 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc, in emitPartialAddress()
3261 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, in emitPartialAddress()
3263 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); in emitPartialAddress()
3264 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(HiExpr), in emitPartialAddress()
3266 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); in emitPartialAddress()
3304 if (loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, true, IDLoc, in expandLoadImmReal()
3313 if (loadImmediate(ImmOp32, ATReg, Mips::NoRegister, true, true, IDLoc, in expandLoadImmReal()
3316 TOut.emitRR(Mips::MTC1, FirstReg, ATReg, IDLoc, STI); in expandLoadImmReal()
3339 TOut.emitRRX(Mips::LWC1, FirstReg, ATReg, in expandLoadImmReal()
3353 if (loadImmediate(HiImmOp64, FirstReg, Mips::NoRegister, false, true, in expandLoadImmReal()
3358 if (loadImmediate(HiImmOp64, FirstReg, Mips::NoRegister, true, true, in expandLoadImmReal()
3362 if (loadImmediate(0, nextReg(FirstReg), Mips::NoRegister, true, true, in expandLoadImmReal()
3388 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, in expandLoadImmReal()
3391 TOut.emitRRX(Mips::ADDiu, ATReg, ATReg, in expandLoadImmReal()
3395 TOut.emitRRI(Mips::LD, FirstReg, ATReg, 0, IDLoc, STI); in expandLoadImmReal()
3397 TOut.emitRRI(Mips::LW, FirstReg, ATReg, 0, IDLoc, STI); in expandLoadImmReal()
3398 TOut.emitRRI(Mips::LW, nextReg(FirstReg), ATReg, 4, IDLoc, STI); in expandLoadImmReal()
3406 if (loadImmediate(HiImmOp64, ATReg, Mips::NoRegister, true, true, IDLoc, in expandLoadImmReal()
3410 TOut.emitRR(Mips::DMTC1, FirstReg, ATReg, IDLoc, STI); in expandLoadImmReal()
3412 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI); in expandLoadImmReal()
3413 TOut.emitRRR(Mips::MTHC1_D32, FirstReg, FirstReg, ATReg, IDLoc, STI); in expandLoadImmReal()
3415 TOut.emitRR(Mips::MTC1, nextReg(FirstReg), ATReg, IDLoc, STI); in expandLoadImmReal()
3416 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI); in expandLoadImmReal()
3441 TOut.emitRRX(Is64FPU ? Mips::LDC164 : Mips::LDC1, FirstReg, ATReg, in expandLoadImmReal()
3458 Inst.setOpcode(Mips::BEQ_MM); in expandUncondBranchMMPseudo()
3459 Inst.addOperand(MCOperand::createReg(Mips::ZERO)); in expandUncondBranchMMPseudo()
3460 Inst.addOperand(MCOperand::createReg(Mips::ZERO)); in expandUncondBranchMMPseudo()
3468 Inst.setOpcode(hasMips32r6() ? Mips::BC16_MMR6 : Mips::B16_MM); in expandUncondBranchMMPseudo()
3475 Inst.setOpcode(Mips::BEQ_MM); in expandUncondBranchMMPseudo()
3476 Inst.addOperand(MCOperand::createReg(Mips::ZERO)); in expandUncondBranchMMPseudo()
3477 Inst.addOperand(MCOperand::createReg(Mips::ZERO)); in expandUncondBranchMMPseudo()
3509 case Mips::BneImm: in expandBranchImm()
3510 OpCode = Mips::BNE; in expandBranchImm()
3512 case Mips::BeqImm: in expandBranchImm()
3513 OpCode = Mips::BEQ; in expandBranchImm()
3515 case Mips::BEQLImmMacro: in expandBranchImm()
3516 OpCode = Mips::BEQL; in expandBranchImm()
3519 case Mips::BNELImmMacro: in expandBranchImm()
3520 OpCode = Mips::BNEL; in expandBranchImm()
3531 TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, in expandBranchImm()
3533 TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI); in expandBranchImm()
3535 TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc, in expandBranchImm()
3544 if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, !isGP64bit(), true, in expandBranchImm()
3551 TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI); in expandBranchImm()
3575 bool IsGPR = (DstRegClassID == Mips::GPR32RegClassID) || in expandMemInst()
3576 (DstRegClassID == Mips::GPR64RegClassID); in expandMemInst()
3599 if (loadImmediate(HiOffset, TmpReg, Mips::NoRegister, Is32BitImm, true, in expandMemInst()
3604 if (BaseReg != Mips::ZERO && BaseReg != Mips::ZERO_64) in expandMemInst()
3605 TOut.emitRRR(isGP64bit() ? Mips::DADDu : Mips::ADDu, TmpReg, TmpReg, in expandMemInst()
3630 unsigned NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM32_MM : Mips::LWM32_MM; in expandLoadStoreMultiple()
3638 (Inst.getOperand(OpNum - 2).getReg() == Mips::SP || in expandLoadStoreMultiple()
3639 Inst.getOperand(OpNum - 2).getReg() == Mips::SP_64) && in expandLoadStoreMultiple()
3640 (Inst.getOperand(OpNum - 3).getReg() == Mips::RA || in expandLoadStoreMultiple()
3641 Inst.getOperand(OpNum - 3).getReg() == Mips::RA_64)) { in expandLoadStoreMultiple()
3644 NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MMR6 : Mips::LWM16_MMR6; in expandLoadStoreMultiple()
3646 NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MM : Mips::LWM16_MM; in expandLoadStoreMultiple()
3681 case Mips::BLTImmMacro: in expandCondBranches()
3682 PseudoOpcode = Mips::BLT; in expandCondBranches()
3684 case Mips::BLEImmMacro: in expandCondBranches()
3685 PseudoOpcode = Mips::BLE; in expandCondBranches()
3687 case Mips::BGEImmMacro: in expandCondBranches()
3688 PseudoOpcode = Mips::BGE; in expandCondBranches()
3690 case Mips::BGTImmMacro: in expandCondBranches()
3691 PseudoOpcode = Mips::BGT; in expandCondBranches()
3693 case Mips::BLTUImmMacro: in expandCondBranches()
3694 PseudoOpcode = Mips::BLTU; in expandCondBranches()
3696 case Mips::BLEUImmMacro: in expandCondBranches()
3697 PseudoOpcode = Mips::BLEU; in expandCondBranches()
3699 case Mips::BGEUImmMacro: in expandCondBranches()
3700 PseudoOpcode = Mips::BGEU; in expandCondBranches()
3702 case Mips::BGTUImmMacro: in expandCondBranches()
3703 PseudoOpcode = Mips::BGTU; in expandCondBranches()
3705 case Mips::BLTLImmMacro: in expandCondBranches()
3706 PseudoOpcode = Mips::BLTL; in expandCondBranches()
3708 case Mips::BLELImmMacro: in expandCondBranches()
3709 PseudoOpcode = Mips::BLEL; in expandCondBranches()
3711 case Mips::BGELImmMacro: in expandCondBranches()
3712 PseudoOpcode = Mips::BGEL; in expandCondBranches()
3714 case Mips::BGTLImmMacro: in expandCondBranches()
3715 PseudoOpcode = Mips::BGTL; in expandCondBranches()
3717 case Mips::BLTULImmMacro: in expandCondBranches()
3718 PseudoOpcode = Mips::BLTUL; in expandCondBranches()
3720 case Mips::BLEULImmMacro: in expandCondBranches()
3721 PseudoOpcode = Mips::BLEUL; in expandCondBranches()
3723 case Mips::BGEULImmMacro: in expandCondBranches()
3724 PseudoOpcode = Mips::BGEUL; in expandCondBranches()
3726 case Mips::BGTULImmMacro: in expandCondBranches()
3727 PseudoOpcode = Mips::BGTUL; in expandCondBranches()
3731 if (loadImmediate(TrgOp.getImm(), TrgReg, Mips::NoRegister, !isGP64bit(), in expandCondBranches()
3737 case Mips::BLT: in expandCondBranches()
3738 case Mips::BLTU: in expandCondBranches()
3739 case Mips::BLTL: in expandCondBranches()
3740 case Mips::BLTUL: in expandCondBranches()
3744 ((PseudoOpcode == Mips::BLTU) || (PseudoOpcode == Mips::BLTUL)); in expandCondBranches()
3745 IsLikely = ((PseudoOpcode == Mips::BLTL) || (PseudoOpcode == Mips::BLTUL)); in expandCondBranches()
3746 ZeroSrcOpcode = Mips::BGTZ; in expandCondBranches()
3747 ZeroTrgOpcode = Mips::BLTZ; in expandCondBranches()
3749 case Mips::BLE: in expandCondBranches()
3750 case Mips::BLEU: in expandCondBranches()
3751 case Mips::BLEL: in expandCondBranches()
3752 case Mips::BLEUL: in expandCondBranches()
3756 ((PseudoOpcode == Mips::BLEU) || (PseudoOpcode == Mips::BLEUL)); in expandCondBranches()
3757 IsLikely = ((PseudoOpcode == Mips::BLEL) || (PseudoOpcode == Mips::BLEUL)); in expandCondBranches()
3758 ZeroSrcOpcode = Mips::BGEZ; in expandCondBranches()
3759 ZeroTrgOpcode = Mips::BLEZ; in expandCondBranches()
3761 case Mips::BGE: in expandCondBranches()
3762 case Mips::BGEU: in expandCondBranches()
3763 case Mips::BGEL: in expandCondBranches()
3764 case Mips::BGEUL: in expandCondBranches()
3768 ((PseudoOpcode == Mips::BGEU) || (PseudoOpcode == Mips::BGEUL)); in expandCondBranches()
3769 IsLikely = ((PseudoOpcode == Mips::BGEL) || (PseudoOpcode == Mips::BGEUL)); in expandCondBranches()
3770 ZeroSrcOpcode = Mips::BLEZ; in expandCondBranches()
3771 ZeroTrgOpcode = Mips::BGEZ; in expandCondBranches()
3773 case Mips::BGT: in expandCondBranches()
3774 case Mips::BGTU: in expandCondBranches()
3775 case Mips::BGTL: in expandCondBranches()
3776 case Mips::BGTUL: in expandCondBranches()
3780 ((PseudoOpcode == Mips::BGTU) || (PseudoOpcode == Mips::BGTUL)); in expandCondBranches()
3781 IsLikely = ((PseudoOpcode == Mips::BGTL) || (PseudoOpcode == Mips::BGTUL)); in expandCondBranches()
3782 ZeroSrcOpcode = Mips::BLTZ; in expandCondBranches()
3783 ZeroTrgOpcode = Mips::BGTZ; in expandCondBranches()
3789 bool IsTrgRegZero = (TrgReg == Mips::ZERO); in expandCondBranches()
3790 bool IsSrcRegZero = (SrcReg == Mips::ZERO); in expandCondBranches()
3795 if (PseudoOpcode == Mips::BLT) { in expandCondBranches()
3796 TOut.emitRX(Mips::BLTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr), in expandCondBranches()
3800 if (PseudoOpcode == Mips::BLE) { in expandCondBranches()
3801 TOut.emitRX(Mips::BLEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr), in expandCondBranches()
3806 if (PseudoOpcode == Mips::BGE) { in expandCondBranches()
3807 TOut.emitRX(Mips::BGEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr), in expandCondBranches()
3812 if (PseudoOpcode == Mips::BGT) { in expandCondBranches()
3813 TOut.emitRX(Mips::BGTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr), in expandCondBranches()
3817 if (PseudoOpcode == Mips::BGTU) { in expandCondBranches()
3818 TOut.emitRRX(Mips::BNE, Mips::ZERO, Mips::ZERO, in expandCondBranches()
3825 TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO, in expandCondBranches()
3835 if ((IsSrcRegZero && PseudoOpcode == Mips::BGTU) || in expandCondBranches()
3836 (IsTrgRegZero && PseudoOpcode == Mips::BLTU)) { in expandCondBranches()
3843 if ((IsSrcRegZero && PseudoOpcode == Mips::BLEU) || in expandCondBranches()
3844 (IsTrgRegZero && PseudoOpcode == Mips::BGEU)) { in expandCondBranches()
3850 TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO, in expandCondBranches()
3868 TOut.emitRRX(AcceptsEquality ? Mips::BEQ : Mips::BNE, in expandCondBranches()
3869 IsSrcRegZero ? TrgReg : SrcReg, Mips::ZERO, in expandCondBranches()
3906 TOut.emitRRR(IsUnsigned ? Mips::SLTu : Mips::SLT, ATRegNum, in expandCondBranches()
3910 TOut.emitRRX(IsLikely ? (AcceptsEquality ? Mips::BEQL : Mips::BNEL) in expandCondBranches()
3911 : (AcceptsEquality ? Mips::BEQ : Mips::BNE), in expandCondBranches()
3912 ATRegNum, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc, in expandCondBranches()
3956 DivOp = Signed ? Mips::DSDIV : Mips::DUDIV; in expandDivRem()
3957 ZeroReg = Mips::ZERO_64; in expandDivRem()
3958 SubOp = Mips::DSUB; in expandDivRem()
3960 DivOp = Signed ? Mips::SDIV : Mips::UDIV; in expandDivRem()
3961 ZeroReg = Mips::ZERO; in expandDivRem()
3962 SubOp = Mips::SUB; in expandDivRem()
3968 bool isDiv = Opcode == Mips::SDivMacro || Opcode == Mips::SDivIMacro || in expandDivRem()
3969 Opcode == Mips::UDivMacro || Opcode == Mips::UDivIMacro || in expandDivRem()
3970 Opcode == Mips::DSDivMacro || Opcode == Mips::DSDivIMacro || in expandDivRem()
3971 Opcode == Mips::DUDivMacro || Opcode == Mips::DUDivIMacro; in expandDivRem()
3973 bool isRem = Opcode == Mips::SRemMacro || Opcode == Mips::SRemIMacro || in expandDivRem()
3974 Opcode == Mips::URemMacro || Opcode == Mips::URemIMacro || in expandDivRem()
3975 Opcode == Mips::DSRemMacro || Opcode == Mips::DSRemIMacro || in expandDivRem()
3976 Opcode == Mips::DURemMacro || Opcode == Mips::DURemIMacro; in expandDivRem()
3985 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
3987 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI); in expandDivRem()
3992 TOut.emitRRR(Mips::OR, RdReg, ZeroReg, ZeroReg, IDLoc, STI); in expandDivRem()
3995 TOut.emitRRR(Mips::OR, RdReg, RsReg, Mips::ZERO, IDLoc, STI); in expandDivRem()
4001 if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, isInt<32>(ImmValue), in expandDivRem()
4005 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4015 if (RtReg == Mips::ZERO || RtReg == Mips::ZERO_64) { in expandDivRem()
4017 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4020 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI); in expandDivRem()
4026 if (isRem && (RdReg == Mips::ZERO || RdReg == Mips::ZERO_64)) { in expandDivRem()
4037 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4042 TOut.emitRRX(Mips::BNE, RtReg, ZeroReg, LabelOp, IDLoc, STI); in expandDivRem()
4048 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI); in expandDivRem()
4054 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4065 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, STI); in expandDivRem()
4073 TOut.emitRRX(Mips::BNE, RtReg, ATReg, LabelOpEnd, IDLoc, STI); in expandDivRem()
4076 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, 1, IDLoc, STI); in expandDivRem()
4079 TOut.emitRI(Mips::LUi, ATReg, (uint16_t)0x8000, IDLoc, STI); in expandDivRem()
4083 TOut.emitRRI(Mips::TEQ, RsReg, ATReg, 0x6, IDLoc, STI); in expandDivRem()
4086 TOut.emitRRX(Mips::BNE, RsReg, ATReg, LabelOpEnd, IDLoc, STI); in expandDivRem()
4088 TOut.emitII(Mips::BREAK, 0x6, 0, IDLoc, STI); in expandDivRem()
4092 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4113 TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI); in expandTrunc()
4114 TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI); in expandTrunc()
4116 TOut.emitRRI(Mips::ORi, ATReg, ThirdReg, 0x3, IDLoc, STI); in expandTrunc()
4117 TOut.emitRRI(Mips::XORi, ATReg, ATReg, 0x2, IDLoc, STI); in expandTrunc()
4118 TOut.emitRR(Mips::CTC1, Mips::RA, ATReg, IDLoc, STI); in expandTrunc()
4120 TOut.emitRR(IsDouble ? (Is64FPU ? Mips::CVT_W_D64 : Mips::CVT_W_D32) in expandTrunc()
4121 : Mips::CVT_W_S, in expandTrunc()
4123 TOut.emitRR(Mips::CTC1, Mips::RA, ThirdReg, IDLoc, STI); in expandTrunc()
4128 TOut.emitRR(IsDouble ? (Is64FPU ? Mips::TRUNC_W_D64 : Mips::TRUNC_W_D32) in expandTrunc()
4129 : Mips::TRUNC_W_S, in expandTrunc()
4178 TOut.emitRRI(Signed ? Mips::LB : Mips::LBu, FirstLbuDstReg, LbuSrcReg, in expandUlh()
4180 TOut.emitRRI(Mips::LBu, SecondLbuDstReg, LbuSrcReg, SecondOffset, IDLoc, STI); in expandUlh()
4181 TOut.emitRRI(Mips::SLL, SllReg, SllReg, 8, IDLoc, STI); in expandUlh()
4182 TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI); in expandUlh()
4223 TOut.emitRRI(Mips::SB, DstReg, ATReg, FirstOffset, IDLoc, STI); in expandUsh()
4224 TOut.emitRRI(Mips::SRL, DstReg, DstReg, 8, IDLoc, STI); in expandUsh()
4225 TOut.emitRRI(Mips::SB, DstReg, ATReg, SecondOffset, IDLoc, STI); in expandUsh()
4226 TOut.emitRRI(Mips::LBu, ATReg, ATReg, 0, IDLoc, STI); in expandUsh()
4227 TOut.emitRRI(Mips::SLL, DstReg, DstReg, 8, IDLoc, STI); in expandUsh()
4228 TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI); in expandUsh()
4230 TOut.emitRRI(Mips::SB, DstReg, SrcReg, FirstOffset, IDLoc, STI); in expandUsh()
4231 TOut.emitRRI(Mips::SRL, ATReg, DstReg, 8, IDLoc, STI); in expandUsh()
4232 TOut.emitRRI(Mips::SB, ATReg, SrcReg, SecondOffset, IDLoc, STI); in expandUsh()
4263 bool IsLoadInst = (Inst.getOpcode() == Mips::Ulw); in expandUxw()
4282 unsigned XWL = IsLoadInst ? Mips::LWL : Mips::SWL; in expandUxw()
4283 unsigned XWR = IsLoadInst ? Mips::LWR : Mips::SWR; in expandUxw()
4288 TOut.emitRRR(Mips::OR, TmpReg, DstReg, Mips::ZERO, IDLoc, STI); in expandUxw()
4303 unsigned ATReg = Mips::NoRegister; in expandAliasImmediate()
4304 unsigned FinalDstReg = Mips::NoRegister; in expandAliasImmediate()
4321 if (!loadImmediate(ImmValue, DstReg, Mips::NoRegister, Is32Bit, false, in expandAliasImmediate()
4326 case Mips::ADDi: in expandAliasImmediate()
4327 FinalOpcode = Mips::ADD; in expandAliasImmediate()
4329 case Mips::ADDiu: in expandAliasImmediate()
4330 FinalOpcode = Mips::ADDu; in expandAliasImmediate()
4332 case Mips::ANDi: in expandAliasImmediate()
4333 FinalOpcode = Mips::AND; in expandAliasImmediate()
4335 case Mips::NORImm: in expandAliasImmediate()
4336 FinalOpcode = Mips::NOR; in expandAliasImmediate()
4338 case Mips::ORi: in expandAliasImmediate()
4339 FinalOpcode = Mips::OR; in expandAliasImmediate()
4341 case Mips::SLTi: in expandAliasImmediate()
4342 FinalOpcode = Mips::SLT; in expandAliasImmediate()
4344 case Mips::SLTiu: in expandAliasImmediate()
4345 FinalOpcode = Mips::SLTu; in expandAliasImmediate()
4347 case Mips::XORi: in expandAliasImmediate()
4348 FinalOpcode = Mips::XOR; in expandAliasImmediate()
4350 case Mips::ADDi_MM: in expandAliasImmediate()
4351 FinalOpcode = Mips::ADD_MM; in expandAliasImmediate()
4353 case Mips::ADDiu_MM: in expandAliasImmediate()
4354 FinalOpcode = Mips::ADDu_MM; in expandAliasImmediate()
4356 case Mips::ANDi_MM: in expandAliasImmediate()
4357 FinalOpcode = Mips::AND_MM; in expandAliasImmediate()
4359 case Mips::ORi_MM: in expandAliasImmediate()
4360 FinalOpcode = Mips::OR_MM; in expandAliasImmediate()
4362 case Mips::SLTi_MM: in expandAliasImmediate()
4363 FinalOpcode = Mips::SLT_MM; in expandAliasImmediate()
4365 case Mips::SLTiu_MM: in expandAliasImmediate()
4366 FinalOpcode = Mips::SLTu_MM; in expandAliasImmediate()
4368 case Mips::XORi_MM: in expandAliasImmediate()
4369 FinalOpcode = Mips::XOR_MM; in expandAliasImmediate()
4371 case Mips::ANDi64: in expandAliasImmediate()
4372 FinalOpcode = Mips::AND64; in expandAliasImmediate()
4374 case Mips::NORImm64: in expandAliasImmediate()
4375 FinalOpcode = Mips::NOR64; in expandAliasImmediate()
4377 case Mips::ORi64: in expandAliasImmediate()
4378 FinalOpcode = Mips::OR64; in expandAliasImmediate()
4380 case Mips::SLTImm64: in expandAliasImmediate()
4381 FinalOpcode = Mips::SLT64; in expandAliasImmediate()
4383 case Mips::SLTUImm64: in expandAliasImmediate()
4384 FinalOpcode = Mips::SLTu64; in expandAliasImmediate()
4386 case Mips::XORi64: in expandAliasImmediate()
4387 FinalOpcode = Mips::XOR64; in expandAliasImmediate()
4391 if (FinalDstReg == Mips::NoRegister) in expandAliasImmediate()
4403 unsigned ATReg = Mips::NoRegister; in expandRotation()
4409 unsigned FirstShift = Mips::NOP; in expandRotation()
4410 unsigned SecondShift = Mips::NOP; in expandRotation()
4419 if (Inst.getOpcode() == Mips::ROL) { in expandRotation()
4420 TOut.emitRRR(Mips::SUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandRotation()
4421 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI); in expandRotation()
4425 if (Inst.getOpcode() == Mips::ROR) { in expandRotation()
4426 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
4437 case Mips::ROL: in expandRotation()
4438 FirstShift = Mips::SRLV; in expandRotation()
4439 SecondShift = Mips::SLLV; in expandRotation()
4441 case Mips::ROR: in expandRotation()
4442 FirstShift = Mips::SLLV; in expandRotation()
4443 SecondShift = Mips::SRLV; in expandRotation()
4451 TOut.emitRRR(Mips::SUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandRotation()
4454 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI); in expandRotation()
4466 unsigned ATReg = Mips::NoRegister; in expandRotationImm()
4471 unsigned FirstShift = Mips::NOP; in expandRotationImm()
4472 unsigned SecondShift = Mips::NOP; in expandRotationImm()
4475 if (Inst.getOpcode() == Mips::ROLImm) { in expandRotationImm()
4480 TOut.emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), STI); in expandRotationImm()
4484 if (Inst.getOpcode() == Mips::RORImm) { in expandRotationImm()
4485 TOut.emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), STI); in expandRotationImm()
4494 TOut.emitRRI(Mips::SRL, DReg, SReg, 0, Inst.getLoc(), STI); in expandRotationImm()
4501 case Mips::ROLImm: in expandRotationImm()
4502 FirstShift = Mips::SLL; in expandRotationImm()
4503 SecondShift = Mips::SRL; in expandRotationImm()
4505 case Mips::RORImm: in expandRotationImm()
4506 FirstShift = Mips::SRL; in expandRotationImm()
4507 SecondShift = Mips::SLL; in expandRotationImm()
4517 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI); in expandRotationImm()
4528 unsigned ATReg = Mips::NoRegister; in expandDRotation()
4534 unsigned FirstShift = Mips::NOP; in expandDRotation()
4535 unsigned SecondShift = Mips::NOP; in expandDRotation()
4544 if (Inst.getOpcode() == Mips::DROL) { in expandDRotation()
4545 TOut.emitRRR(Mips::DSUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandDRotation()
4546 TOut.emitRRR(Mips::DROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI); in expandDRotation()
4550 if (Inst.getOpcode() == Mips::DROR) { in expandDRotation()
4551 TOut.emitRRR(Mips::DROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); in expandDRotation()
4562 case Mips::DROL: in expandDRotation()
4563 FirstShift = Mips::DSRLV; in expandDRotation()
4564 SecondShift = Mips::DSLLV; in expandDRotation()
4566 case Mips::DROR: in expandDRotation()
4567 FirstShift = Mips::DSLLV; in expandDRotation()
4568 SecondShift = Mips::DSRLV; in expandDRotation()
4576 TOut.emitRRR(Mips::DSUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandDRotation()
4579 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI); in expandDRotation()
4591 unsigned ATReg = Mips::NoRegister; in expandDRotationImm()
4596 unsigned FirstShift = Mips::NOP; in expandDRotationImm()
4597 unsigned SecondShift = Mips::NOP; in expandDRotationImm()
4602 unsigned FinalOpcode = Mips::NOP; in expandDRotationImm()
4604 FinalOpcode = Mips::DROTR; in expandDRotationImm()
4606 FinalOpcode = Mips::DROTR32; in expandDRotationImm()
4608 if (Inst.getOpcode() == Mips::DROLImm) in expandDRotationImm()
4609 FinalOpcode = Mips::DROTR32; in expandDRotationImm()
4611 FinalOpcode = Mips::DROTR; in expandDRotationImm()
4613 if (Inst.getOpcode() == Mips::DROLImm) in expandDRotationImm()
4614 FinalOpcode = Mips::DROTR; in expandDRotationImm()
4616 FinalOpcode = Mips::DROTR32; in expandDRotationImm()
4620 if (Inst.getOpcode() == Mips::DROLImm) in expandDRotationImm()
4630 TOut.emitRRI(Mips::DSRL, DReg, SReg, 0, Inst.getLoc(), STI); in expandDRotationImm()
4637 case Mips::DROLImm: in expandDRotationImm()
4639 FirstShift = Mips::DSLL; in expandDRotationImm()
4640 SecondShift = Mips::DSRL32; in expandDRotationImm()
4643 FirstShift = Mips::DSLL32; in expandDRotationImm()
4644 SecondShift = Mips::DSRL32; in expandDRotationImm()
4647 FirstShift = Mips::DSLL32; in expandDRotationImm()
4648 SecondShift = Mips::DSRL; in expandDRotationImm()
4651 case Mips::DRORImm: in expandDRotationImm()
4653 FirstShift = Mips::DSRL; in expandDRotationImm()
4654 SecondShift = Mips::DSLL32; in expandDRotationImm()
4657 FirstShift = Mips::DSRL32; in expandDRotationImm()
4658 SecondShift = Mips::DSLL32; in expandDRotationImm()
4661 FirstShift = Mips::DSRL32; in expandDRotationImm()
4662 SecondShift = Mips::DSLL; in expandDRotationImm()
4674 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI); in expandDRotationImm()
4688 TOut.emitRI(Mips::BGEZ, SecondRegOp, 8, IDLoc, STI); in expandAbs()
4690 TOut.emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::ZERO, IDLoc, STI); in expandAbs()
4693 TOut.emitRRR(Mips::SUB, FirstRegOp, Mips::ZERO, SecondRegOp, IDLoc, STI); in expandAbs()
4701 unsigned ATReg = Mips::NoRegister; in expandMulImm()
4710 loadImmediate(ImmValue, ATReg, Mips::NoRegister, true, false, IDLoc, Out, in expandMulImm()
4713 TOut.emitRR(Inst.getOpcode() == Mips::MULImmMacro ? Mips::MULT : Mips::DMULT, in expandMulImm()
4716 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulImm()
4724 unsigned ATReg = Mips::NoRegister; in expandMulO()
4733 TOut.emitRR(Inst.getOpcode() == Mips::MULOMacro ? Mips::MULT : Mips::DMULT, in expandMulO()
4736 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulO()
4738 TOut.emitRRI(Inst.getOpcode() == Mips::MULOMacro ? Mips::SRA : Mips::DSRA32, in expandMulO()
4741 TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI); in expandMulO()
4744 TOut.emitRRI(Mips::TNE, DstReg, ATReg, 6, IDLoc, STI); in expandMulO()
4751 TOut.emitRRX(Mips::BEQ, DstReg, ATReg, LabelOp, IDLoc, STI); in expandMulO()
4754 TOut.emitII(Mips::BREAK, 6, 0, IDLoc, STI); in expandMulO()
4758 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulO()
4766 unsigned ATReg = Mips::NoRegister; in expandMulOU()
4775 TOut.emitRR(Inst.getOpcode() == Mips::MULOUMacro ? Mips::MULTu : Mips::DMULTu, in expandMulOU()
4778 TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI); in expandMulOU()
4779 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulOU()
4781 TOut.emitRRI(Mips::TNE, ATReg, Mips::ZERO, 6, IDLoc, STI); in expandMulOU()
4788 TOut.emitRRX(Mips::BEQ, ATReg, Mips::ZERO, LabelOp, IDLoc, STI); in expandMulOU()
4791 TOut.emitII(Mips::BREAK, 6, 0, IDLoc, STI); in expandMulOU()
4806 TOut.emitRR(Mips::DMULTu, SrcReg, TmpReg, IDLoc, STI); in expandDMULMacro()
4807 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandDMULMacro()
4827 unsigned Opcode = IsLoad ? Mips::LW : Mips::SW; in expandLoadStoreDMacro()
4865 if (Inst.getOperand(1).getReg() != Mips::ZERO && in expandSeq()
4866 Inst.getOperand(2).getReg() != Mips::ZERO) { in expandSeq()
4867 TOut.emitRRR(Mips::XOR, Inst.getOperand(0).getReg(), in expandSeq()
4870 TOut.emitRRI(Mips::SLTiu, Inst.getOperand(0).getReg(), in expandSeq()
4876 if (Inst.getOperand(1).getReg() == Mips::ZERO) { in expandSeq()
4881 TOut.emitRRI(Mips::SLTiu, Inst.getOperand(0).getReg(), Reg, 1, IDLoc, STI); in expandSeq()
4895 TOut.emitRRI(Mips::SLTiu, Inst.getOperand(0).getReg(), in expandSeqI()
4900 if (Reg == Mips::ZERO) { in expandSeqI()
4902 TOut.emitRRR(isGP64bit() ? Mips::DADDu : Mips::ADDu, in expandSeqI()
4909 Opc = isGP64bit() ? Mips::DADDiu : Mips::ADDiu; in expandSeqI()
4911 Opc = Mips::XORi; in expandSeqI()
4919 if (loadImmediate(Imm, ATReg, Mips::NoRegister, true, isGP64bit(), IDLoc, in expandSeqI()
4923 TOut.emitRRR(Mips::XOR, Inst.getOperand(0).getReg(), in expandSeqI()
4925 TOut.emitRRI(Mips::SLTiu, Inst.getOperand(0).getReg(), in expandSeqI()
4932 TOut.emitRRI(Mips::SLTiu, Inst.getOperand(0).getReg(), in expandSeqI()
4942 case Mips::MFTLO: in getRegisterForMxtrDSP()
4943 case Mips::MTTLO: in getRegisterForMxtrDSP()
4945 case Mips::AC0: in getRegisterForMxtrDSP()
4946 return Mips::ZERO; in getRegisterForMxtrDSP()
4947 case Mips::AC1: in getRegisterForMxtrDSP()
4948 return Mips::A0; in getRegisterForMxtrDSP()
4949 case Mips::AC2: in getRegisterForMxtrDSP()
4950 return Mips::T0; in getRegisterForMxtrDSP()
4951 case Mips::AC3: in getRegisterForMxtrDSP()
4952 return Mips::T4; in getRegisterForMxtrDSP()
4956 case Mips::MFTHI: in getRegisterForMxtrDSP()
4957 case Mips::MTTHI: in getRegisterForMxtrDSP()
4959 case Mips::AC0: in getRegisterForMxtrDSP()
4960 return Mips::AT; in getRegisterForMxtrDSP()
4961 case Mips::AC1: in getRegisterForMxtrDSP()
4962 return Mips::A1; in getRegisterForMxtrDSP()
4963 case Mips::AC2: in getRegisterForMxtrDSP()
4964 return Mips::T1; in getRegisterForMxtrDSP()
4965 case Mips::AC3: in getRegisterForMxtrDSP()
4966 return Mips::T5; in getRegisterForMxtrDSP()
4970 case Mips::MFTACX: in getRegisterForMxtrDSP()
4971 case Mips::MTTACX: in getRegisterForMxtrDSP()
4973 case Mips::AC0: in getRegisterForMxtrDSP()
4974 return Mips::V0; in getRegisterForMxtrDSP()
4975 case Mips::AC1: in getRegisterForMxtrDSP()
4976 return Mips::A2; in getRegisterForMxtrDSP()
4977 case Mips::AC2: in getRegisterForMxtrDSP()
4978 return Mips::T2; in getRegisterForMxtrDSP()
4979 case Mips::AC3: in getRegisterForMxtrDSP()
4980 return Mips::T6; in getRegisterForMxtrDSP()
4984 case Mips::MFTDSP: in getRegisterForMxtrDSP()
4985 case Mips::MTTDSP: in getRegisterForMxtrDSP()
4986 return Mips::S0; in getRegisterForMxtrDSP()
4996 case Mips::F0: return Mips::ZERO; in getRegisterForMxtrFP()
4997 case Mips::F1: return Mips::AT; in getRegisterForMxtrFP()
4998 case Mips::F2: return Mips::V0; in getRegisterForMxtrFP()
4999 case Mips::F3: return Mips::V1; in getRegisterForMxtrFP()
5000 case Mips::F4: return Mips::A0; in getRegisterForMxtrFP()
5001 case Mips::F5: return Mips::A1; in getRegisterForMxtrFP()
5002 case Mips::F6: return Mips::A2; in getRegisterForMxtrFP()
5003 case Mips::F7: return Mips::A3; in getRegisterForMxtrFP()
5004 case Mips::F8: return Mips::T0; in getRegisterForMxtrFP()
5005 case Mips::F9: return Mips::T1; in getRegisterForMxtrFP()
5006 case Mips::F10: return Mips::T2; in getRegisterForMxtrFP()
5007 case Mips::F11: return Mips::T3; in getRegisterForMxtrFP()
5008 case Mips::F12: return Mips::T4; in getRegisterForMxtrFP()
5009 case Mips::F13: return Mips::T5; in getRegisterForMxtrFP()
5010 case Mips::F14: return Mips::T6; in getRegisterForMxtrFP()
5011 case Mips::F15: return Mips::T7; in getRegisterForMxtrFP()
5012 case Mips::F16: return Mips::S0; in getRegisterForMxtrFP()
5013 case Mips::F17: return Mips::S1; in getRegisterForMxtrFP()
5014 case Mips::F18: return Mips::S2; in getRegisterForMxtrFP()
5015 case Mips::F19: return Mips::S3; in getRegisterForMxtrFP()
5016 case Mips::F20: return Mips::S4; in getRegisterForMxtrFP()
5017 case Mips::F21: return Mips::S5; in getRegisterForMxtrFP()
5018 case Mips::F22: return Mips::S6; in getRegisterForMxtrFP()
5019 case Mips::F23: return Mips::S7; in getRegisterForMxtrFP()
5020 case Mips::F24: return Mips::T8; in getRegisterForMxtrFP()
5021 case Mips::F25: return Mips::T9; in getRegisterForMxtrFP()
5022 case Mips::F26: return Mips::K0; in getRegisterForMxtrFP()
5023 case Mips::F27: return Mips::K1; in getRegisterForMxtrFP()
5024 case Mips::F28: return Mips::GP; in getRegisterForMxtrFP()
5025 case Mips::F29: return Mips::SP; in getRegisterForMxtrFP()
5026 case Mips::F30: return Mips::FP; in getRegisterForMxtrFP()
5027 case Mips::F31: return Mips::RA; in getRegisterForMxtrFP()
5035 case Mips::COP00: return Mips::ZERO; in getRegisterForMxtrC0()
5036 case Mips::COP01: return Mips::AT; in getRegisterForMxtrC0()
5037 case Mips::COP02: return Mips::V0; in getRegisterForMxtrC0()
5038 case Mips::COP03: return Mips::V1; in getRegisterForMxtrC0()
5039 case Mips::COP04: return Mips::A0; in getRegisterForMxtrC0()
5040 case Mips::COP05: return Mips::A1; in getRegisterForMxtrC0()
5041 case Mips::COP06: return Mips::A2; in getRegisterForMxtrC0()
5042 case Mips::COP07: return Mips::A3; in getRegisterForMxtrC0()
5043 case Mips::COP08: return Mips::T0; in getRegisterForMxtrC0()
5044 case Mips::COP09: return Mips::T1; in getRegisterForMxtrC0()
5045 case Mips::COP010: return Mips::T2; in getRegisterForMxtrC0()
5046 case Mips::COP011: return Mips::T3; in getRegisterForMxtrC0()
5047 case Mips::COP012: return Mips::T4; in getRegisterForMxtrC0()
5048 case Mips::COP013: return Mips::T5; in getRegisterForMxtrC0()
5049 case Mips::COP014: return Mips::T6; in getRegisterForMxtrC0()
5050 case Mips::COP015: return Mips::T7; in getRegisterForMxtrC0()
5051 case Mips::COP016: return Mips::S0; in getRegisterForMxtrC0()
5052 case Mips::COP017: return Mips::S1; in getRegisterForMxtrC0()
5053 case Mips::COP018: return Mips::S2; in getRegisterForMxtrC0()
5054 case Mips::COP019: return Mips::S3; in getRegisterForMxtrC0()
5055 case Mips::COP020: return Mips::S4; in getRegisterForMxtrC0()
5056 case Mips::COP021: return Mips::S5; in getRegisterForMxtrC0()
5057 case Mips::COP022: return Mips::S6; in getRegisterForMxtrC0()
5058 case Mips::COP023: return Mips::S7; in getRegisterForMxtrC0()
5059 case Mips::COP024: return Mips::T8; in getRegisterForMxtrC0()
5060 case Mips::COP025: return Mips::T9; in getRegisterForMxtrC0()
5061 case Mips::COP026: return Mips::K0; in getRegisterForMxtrC0()
5062 case Mips::COP027: return Mips::K1; in getRegisterForMxtrC0()
5063 case Mips::COP028: return Mips::GP; in getRegisterForMxtrC0()
5064 case Mips::COP029: return Mips::SP; in getRegisterForMxtrC0()
5065 case Mips::COP030: return Mips::FP; in getRegisterForMxtrC0()
5066 case Mips::COP031: return Mips::RA; in getRegisterForMxtrC0()
5082 case Mips::MFTC0: in expandMXTRAlias()
5085 case Mips::MTTC0: in expandMXTRAlias()
5090 case Mips::MFTGPR: in expandMXTRAlias()
5093 case Mips::MTTGPR: in expandMXTRAlias()
5096 case Mips::MFTLO: in expandMXTRAlias()
5097 case Mips::MFTHI: in expandMXTRAlias()
5098 case Mips::MFTACX: in expandMXTRAlias()
5099 case Mips::MFTDSP: in expandMXTRAlias()
5102 case Mips::MTTLO: in expandMXTRAlias()
5103 case Mips::MTTHI: in expandMXTRAlias()
5104 case Mips::MTTACX: in expandMXTRAlias()
5105 case Mips::MTTDSP: in expandMXTRAlias()
5109 case Mips::MFTHC1: in expandMXTRAlias()
5112 case Mips::MFTC1: in expandMXTRAlias()
5117 case Mips::MTTHC1: in expandMXTRAlias()
5120 case Mips::MTTC1: in expandMXTRAlias()
5124 case Mips::CFTC1: in expandMXTRAlias()
5127 case Mips::CTTC1: in expandMXTRAlias()
5135 : (Inst.getOpcode() != Mips::MTTDSP ? Inst.getOperand(1).getReg() in expandMXTRAlias()
5138 TOut.emitRRIII(IsMFTR ? Mips::MFTR : Mips::MTTR, Op0, Op1, u, sel, h, IDLoc, in expandMXTRAlias()
5149 case Mips::DATI: in checkEarlyTargetMatchPredicate()
5150 case Mips::DAHI: in checkEarlyTargetMatchPredicate()
5162 case Mips::DAUI: in checkTargetMatchPredicate()
5163 if (Inst.getOperand(1).getReg() == Mips::ZERO || in checkTargetMatchPredicate()
5164 Inst.getOperand(1).getReg() == Mips::ZERO_64) in checkTargetMatchPredicate()
5171 case Mips::JALR_HB: in checkTargetMatchPredicate()
5172 case Mips::JALR_HB64: in checkTargetMatchPredicate()
5173 case Mips::JALRC_HB_MMR6: in checkTargetMatchPredicate()
5174 case Mips::JALRC_MMR6: in checkTargetMatchPredicate()
5178 case Mips::LWP_MM: in checkTargetMatchPredicate()
5182 case Mips::SYNC: in checkTargetMatchPredicate()
5186 case Mips::MFC0: in checkTargetMatchPredicate()
5187 case Mips::MTC0: in checkTargetMatchPredicate()
5188 case Mips::MTC2: in checkTargetMatchPredicate()
5189 case Mips::MFC2: in checkTargetMatchPredicate()
5205 case Mips::BLEZC: case Mips::BLEZC_MMR6: in checkTargetMatchPredicate()
5206 case Mips::BGEZC: case Mips::BGEZC_MMR6: in checkTargetMatchPredicate()
5207 case Mips::BGTZC: case Mips::BGTZC_MMR6: in checkTargetMatchPredicate()
5208 case Mips::BLTZC: case Mips::BLTZC_MMR6: in checkTargetMatchPredicate()
5209 case Mips::BEQZC: case Mips::BEQZC_MMR6: in checkTargetMatchPredicate()
5210 case Mips::BNEZC: case Mips::BNEZC_MMR6: in checkTargetMatchPredicate()
5211 case Mips::BLEZC64: in checkTargetMatchPredicate()
5212 case Mips::BGEZC64: in checkTargetMatchPredicate()
5213 case Mips::BGTZC64: in checkTargetMatchPredicate()
5214 case Mips::BLTZC64: in checkTargetMatchPredicate()
5215 case Mips::BEQZC64: in checkTargetMatchPredicate()
5216 case Mips::BNEZC64: in checkTargetMatchPredicate()
5217 if (Inst.getOperand(0).getReg() == Mips::ZERO || in checkTargetMatchPredicate()
5218 Inst.getOperand(0).getReg() == Mips::ZERO_64) in checkTargetMatchPredicate()
5221 case Mips::BGEC: case Mips::BGEC_MMR6: in checkTargetMatchPredicate()
5222 case Mips::BLTC: case Mips::BLTC_MMR6: in checkTargetMatchPredicate()
5223 case Mips::BGEUC: case Mips::BGEUC_MMR6: in checkTargetMatchPredicate()
5224 case Mips::BLTUC: case Mips::BLTUC_MMR6: in checkTargetMatchPredicate()
5225 case Mips::BEQC: case Mips::BEQC_MMR6: in checkTargetMatchPredicate()
5226 case Mips::BNEC: case Mips::BNEC_MMR6: in checkTargetMatchPredicate()
5227 case Mips::BGEC64: in checkTargetMatchPredicate()
5228 case Mips::BLTC64: in checkTargetMatchPredicate()
5229 case Mips::BGEUC64: in checkTargetMatchPredicate()
5230 case Mips::BLTUC64: in checkTargetMatchPredicate()
5231 case Mips::BEQC64: in checkTargetMatchPredicate()
5232 case Mips::BNEC64: in checkTargetMatchPredicate()
5233 if (Inst.getOperand(0).getReg() == Mips::ZERO || in checkTargetMatchPredicate()
5234 Inst.getOperand(0).getReg() == Mips::ZERO_64) in checkTargetMatchPredicate()
5236 if (Inst.getOperand(1).getReg() == Mips::ZERO || in checkTargetMatchPredicate()
5237 Inst.getOperand(1).getReg() == Mips::ZERO_64) in checkTargetMatchPredicate()
5242 case Mips::DINS: { in checkTargetMatchPredicate()
5251 case Mips::DINSM: in checkTargetMatchPredicate()
5252 case Mips::DINSU: { in checkTargetMatchPredicate()
5261 case Mips::DEXT: { in checkTargetMatchPredicate()
5270 case Mips::DEXTM: in checkTargetMatchPredicate()
5271 case Mips::DEXTU: { in checkTargetMatchPredicate()
5280 case Mips::CRC32B: case Mips::CRC32CB: in checkTargetMatchPredicate()
5281 case Mips::CRC32H: case Mips::CRC32CH: in checkTargetMatchPredicate()
5282 case Mips::CRC32W: case Mips::CRC32CW: in checkTargetMatchPredicate()
5283 case Mips::CRC32D: case Mips::CRC32CD: in checkTargetMatchPredicate()
5291 (Inst.getOperand(0).getReg() != Mips::FCC0) && !hasEightFccRegisters()) in checkTargetMatchPredicate()
5522 (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) && in ConvertXWPOperands()
5710 (isGP64bit()) ? Mips::GPR64RegClassID : Mips::GPR32RegClassID, ATIndex); in getATReg()
6190 unsigned PrevReg = Mips::NoRegister; in parseRegisterList()
6205 if ((isGP64bit() && RegNo == Mips::RA_64) || in parseRegisterList()
6206 (!isGP64bit() && RegNo == Mips::RA)) { in parseRegisterList()
6211 if ((((TmpReg < Mips::S0) || (TmpReg > Mips::S7)) && !isGP64bit()) || in parseRegisterList()
6212 (((TmpReg < Mips::S0_64) || (TmpReg > Mips::S7_64)) && in parseRegisterList()
6225 if ((PrevReg == Mips::NoRegister) && in parseRegisterList()
6226 ((isGP64bit() && (RegNo != Mips::S0_64) && (RegNo != Mips::RA_64)) || in parseRegisterList()
6227 (!isGP64bit() && (RegNo != Mips::S0) && (RegNo != Mips::RA)))) { in parseRegisterList()
6230 } else if (!(((RegNo == Mips::FP || RegNo == Mips::RA || in parseRegisterList()
6231 (RegNo >= Mips::S0 && RegNo <= Mips::S7)) && in parseRegisterList()
6233 ((RegNo == Mips::FP_64 || RegNo == Mips::RA_64 || in parseRegisterList()
6234 (RegNo >= Mips::S0_64 && RegNo <= Mips::S7_64)) && in parseRegisterList()
6238 } else if ((PrevReg != Mips::NoRegister) && (RegNo != PrevReg + 1) && in parseRegisterList()
6239 ((RegNo != Mips::FP && RegNo != Mips::RA && !isGP64bit()) || in parseRegisterList()
6240 (RegNo != Mips::FP_64 && RegNo != Mips::RA_64 && in parseRegisterList()
6542 setFeatureBits(Mips::FeatureMSA, "msa"); in parseSetMsaDirective()
6555 clearFeatureBits(Mips::FeatureMSA, "msa"); in parseSetNoMsaDirective()
6570 clearFeatureBits(Mips::FeatureDSP, "dsp"); in parseSetNoDspDirective()
6585 setFeatureBits(Mips::FeatureMips16, "mips16"); in parseSetMips16Directive()
6601 clearFeatureBits(Mips::FeatureMips16, "mips16"); in parseSetNoMips16Directive()
6643 clearFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg"); in parseSetOddSPRegDirective()
6657 setFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg"); in parseSetNoOddSPRegDirective()
6672 setFeatureBits(Mips::FeatureMT, "mt"); in parseSetMtDirective()
6688 clearFeatureBits(Mips::FeatureMT, "mt"); in parseSetNoMtDirective()
6705 clearFeatureBits(Mips::FeatureCRC, "crc"); in parseSetNoCRCDirective()
6722 clearFeatureBits(Mips::FeatureVirt, "virt"); in parseSetNoVirtDirective()
6739 clearFeatureBits(Mips::FeatureGINV, "ginv"); in parseSetNoGINVDirective()
6789 setFeatureBits(Mips::FeatureSoftFloat, "soft-float"); in parseSetSoftFloatDirective()
6800 clearFeatureBits(Mips::FeatureSoftFloat, "soft-float"); in parseSetHardFloatDirective()
6908 case Mips::FeatureDSP: in parseSetFeature()
6909 setFeatureBits(Mips::FeatureDSP, "dsp"); in parseSetFeature()
6912 case Mips::FeatureDSPR2: in parseSetFeature()
6913 setFeatureBits(Mips::FeatureDSPR2, "dspr2"); in parseSetFeature()
6916 case Mips::FeatureMicroMips: in parseSetFeature()
6917 setFeatureBits(Mips::FeatureMicroMips, "micromips"); in parseSetFeature()
6920 case Mips::FeatureMips1: in parseSetFeature()
6924 case Mips::FeatureMips2: in parseSetFeature()
6928 case Mips::FeatureMips3: in parseSetFeature()
6932 case Mips::FeatureMips4: in parseSetFeature()
6936 case Mips::FeatureMips5: in parseSetFeature()
6940 case Mips::FeatureMips32: in parseSetFeature()
6944 case Mips::FeatureMips32r2: in parseSetFeature()
6948 case Mips::FeatureMips32r3: in parseSetFeature()
6952 case Mips::FeatureMips32r5: in parseSetFeature()
6956 case Mips::FeatureMips32r6: in parseSetFeature()
6960 case Mips::FeatureMips64: in parseSetFeature()
6964 case Mips::FeatureMips64r2: in parseSetFeature()
6968 case Mips::FeatureMips64r3: in parseSetFeature()
6972 case Mips::FeatureMips64r5: in parseSetFeature()
6976 case Mips::FeatureMips64r6: in parseSetFeature()
6980 case Mips::FeatureCRC: in parseSetFeature()
6981 setFeatureBits(Mips::FeatureCRC, "crc"); in parseSetFeature()
6984 case Mips::FeatureVirt: in parseSetFeature()
6985 setFeatureBits(Mips::FeatureVirt, "virt"); in parseSetFeature()
6988 case Mips::FeatureGINV: in parseSetFeature()
6989 setFeatureBits(Mips::FeatureGINV, "ginv"); in parseSetFeature()
7234 clearFeatureBits(Mips::FeatureMicroMips, "micromips"); in parseDirectiveSet()
7244 return parseSetFeature(Mips::FeatureMicroMips); in parseDirectiveSet()
7249 return parseSetFeature(Mips::FeatureMips1); in parseDirectiveSet()
7251 return parseSetFeature(Mips::FeatureMips2); in parseDirectiveSet()
7253 return parseSetFeature(Mips::FeatureMips3); in parseDirectiveSet()
7255 return parseSetFeature(Mips::FeatureMips4); in parseDirectiveSet()
7257 return parseSetFeature(Mips::FeatureMips5); in parseDirectiveSet()
7259 return parseSetFeature(Mips::FeatureMips32); in parseDirectiveSet()
7261 return parseSetFeature(Mips::FeatureMips32r2); in parseDirectiveSet()
7263 return parseSetFeature(Mips::FeatureMips32r3); in parseDirectiveSet()
7265 return parseSetFeature(Mips::FeatureMips32r5); in parseDirectiveSet()
7267 return parseSetFeature(Mips::FeatureMips32r6); in parseDirectiveSet()
7269 return parseSetFeature(Mips::FeatureMips64); in parseDirectiveSet()
7271 return parseSetFeature(Mips::FeatureMips64r2); in parseDirectiveSet()
7273 return parseSetFeature(Mips::FeatureMips64r3); in parseDirectiveSet()
7275 return parseSetFeature(Mips::FeatureMips64r5); in parseDirectiveSet()
7281 return parseSetFeature(Mips::FeatureMips64r6); in parseDirectiveSet()
7284 return parseSetFeature(Mips::FeatureDSP); in parseDirectiveSet()
7286 return parseSetFeature(Mips::FeatureDSPR2); in parseDirectiveSet()
7302 return parseSetFeature(Mips::FeatureCRC); in parseDirectiveSet()
7306 return parseSetFeature(Mips::FeatureVirt); in parseDirectiveSet()
7310 return parseSetFeature(Mips::FeatureGINV); in parseDirectiveSet()
7554 clearModuleFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg"); in parseDirectiveModule()
7577 setModuleFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg"); in parseDirectiveModule()
7598 setModuleFeatureBits(Mips::FeatureSoftFloat, "soft-float"); in parseDirectiveModule()
7617 clearModuleFeatureBits(Mips::FeatureSoftFloat, "soft-float"); in parseDirectiveModule()
7636 setModuleFeatureBits(Mips::FeatureMT, "mt"); in parseDirectiveModule()
7655 setModuleFeatureBits(Mips::FeatureCRC, "crc"); in parseDirectiveModule()
7674 clearModuleFeatureBits(Mips::FeatureCRC, "crc"); in parseDirectiveModule()
7693 setModuleFeatureBits(Mips::FeatureVirt, "virt"); in parseDirectiveModule()
7712 clearModuleFeatureBits(Mips::FeatureVirt, "virt"); in parseDirectiveModule()
7731 setModuleFeatureBits(Mips::FeatureGINV, "ginv"); in parseDirectiveModule()
7750 clearModuleFeatureBits(Mips::FeatureGINV, "ginv"); in parseDirectiveModule()
7831 setModuleFeatureBits(Mips::FeatureFPXX, "fpxx"); in parseFpABIValue()
7832 clearModuleFeatureBits(Mips::FeatureFP64Bit, "fp64"); in parseFpABIValue()
7834 setFeatureBits(Mips::FeatureFPXX, "fpxx"); in parseFpABIValue()
7835 clearFeatureBits(Mips::FeatureFP64Bit, "fp64"); in parseFpABIValue()
7857 clearModuleFeatureBits(Mips::FeatureFPXX, "fpxx"); in parseFpABIValue()
7858 clearModuleFeatureBits(Mips::FeatureFP64Bit, "fp64"); in parseFpABIValue()
7860 clearFeatureBits(Mips::FeatureFPXX, "fpxx"); in parseFpABIValue()
7861 clearFeatureBits(Mips::FeatureFP64Bit, "fp64"); in parseFpABIValue()
7866 clearModuleFeatureBits(Mips::FeatureFPXX, "fpxx"); in parseFpABIValue()
7867 setModuleFeatureBits(Mips::FeatureFP64Bit, "fp64"); in parseFpABIValue()
7869 clearFeatureBits(Mips::FeatureFPXX, "fpxx"); in parseFpABIValue()
7870 setFeatureBits(Mips::FeatureFP64Bit, "fp64"); in parseFpABIValue()