Home
last modified time | relevance | path

Searched refs:getOperand (Results 1 – 25 of 1264) sorted by relevance

12345678910>>...51

/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstComments.cpp662 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
678 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
694 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
708 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
726 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
820 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
838 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
1268 if (MI->getOperand(2).isImm() && in EmitAnyX86InstComments()
1269 MI->getOperand(3).isImm()) in EmitAnyX86InstComments()
1278 if (MI->getOperand(3).isImm() && in EmitAnyX86InstComments()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYMCCodeEmitter.cpp33 const MCOperand &MO = MI.getOperand(Idx); in getOImmOpValue()
42 const MCOperand &MO = MI.getOperand(Idx); in getImmOpValueIDLY()
53 const MCOperand &MSB = MI.getOperand(Idx); in getImmOpValueMSBSize()
80 .addOperand(MI.getOperand(0)) in expandJBTF()
105 .addOperand(MI.getOperand(0)) in expandNEG()
111 .addOperand(MI.getOperand(0)) in expandNEG()
112 .addOperand(MI.getOperand(0)) in expandNEG()
127 .addOperand(MI.getOperand(0)) in expandRSUBI()
133 .addOperand(MI.getOperand(0)) in expandRSUBI()
225 auto V = 1 << MI.getOperand(1).getImm(); in encodeInstruction()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp190 Register Reg2 = MI.getOperand(2).getReg(); in processBlock()
246 MI.getOperand(0).setReg(KilledProdReg); in processBlock()
247 MI.getOperand(1).setReg(KilledProdReg); in processBlock()
248 MI.getOperand(3).setReg(AddendSrcReg); in processBlock()
252 MI.getOperand(3).setSubReg(AddSubReg); in processBlock()
255 MI.getOperand(3).setIsKill(AddRegKill); in processBlock()
258 MI.getOperand(3).setIsUndef(AddRegUndef); in processBlock()
265 MI.getOperand(2).setReg(AddendSrcReg); in processBlock()
266 MI.getOperand(2).setSubReg(AddSubReg); in processBlock()
267 MI.getOperand(2).setIsKill(AddRegKill); in processBlock()
[all …]
H A DPPCMIPeephole.cpp183 MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm()) in getKnownLeadingZeroCount()
189 MI->getOperand(3).getImm() <= MI->getOperand(4).getImm()) in getKnownLeadingZeroCount()
483 if (!MI.getOperand(1).isImm() || MI.getOperand(1).getImm() != 0) in simplifyCode()
636 DefMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
807 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
851 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
893 SrcMI->getOperand(0).isReg() && SrcMI->getOperand(1).isReg())) in simplifyCode()
1418 if (CMPI1->getOperand(2).isReg() && CMPI2->getOperand(2).isReg()) { in eliminateRedundantCompare()
1568 BI2->getOperand(1).setReg(BI1->getOperand(1).getReg()); in eliminateRedundantCompare()
1637 MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg()); in emitRLDICWhenLoweringJumpTables()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp185 MIBHI->getOperand(4).setIsKill(); in expandArith()
210 MIBLO->getOperand(3).setIsDead(); in expandLogic()
335 MIBHI->getOperand(4).setIsKill(); in expand()
947 auto Op1 = MI.getOperand(0); in expandAtomicBinaryOp()
948 auto Op2 = MI.getOperand(1); in expandAtomicBinaryOp()
1386 MIB->getOperand(2).setIsKill(); in expand()
1503 MI0->getOperand(3).setIsDead(); in expandLSLW4Rd()
2093 ->getOperand(3) in expandLSLB7Rd()
2144 ->getOperand(4) in expandLSRB7Rd()
2195 ->getOperand(2) in expandASRB6Rd()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600ClauseMergePass.cpp128 if (LatrCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
129 RootCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
144 if (LatrCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
145 RootCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
153 if (LatrCFAlu.getOperand(Mode0Idx).getImm()) { in mergeIfPossible()
154 RootCFAlu.getOperand(Mode0Idx).setImm( in mergeIfPossible()
156 RootCFAlu.getOperand(KBank0Idx).setImm( in mergeIfPossible()
158 RootCFAlu.getOperand(KBank0LineIdx) in mergeIfPossible()
162 RootCFAlu.getOperand(Mode1Idx).setImm( in mergeIfPossible()
164 RootCFAlu.getOperand(KBank1Idx).setImm( in mergeIfPossible()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/VE/MCTargetDesc/
H A DVEInstPrinter.cpp78 if (MI->getOperand(OpNum + 2).isImm() && in printMemASXOperand()
84 if (MI->getOperand(OpNum + 1).isImm() && in printMemASXOperand()
86 MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASXOperand()
87 if (MI->getOperand(OpNum + 2).isImm() && in printMemASXOperand()
101 if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASXOperand()
122 if (MI->getOperand(OpNum + 1).isImm() && in printMemASOperandASX()
128 if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASOperandASX()
153 if (MI->getOperand(OpNum + 1).isImm() && in printMemASOperandRRM()
159 if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASOperandRRM()
184 if (MI->getOperand(OpNum + 1).isImm() && in printMemASOperandHM()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZTargetStreamer.h31 A.getNumOperands() == 5 && A.getOperand(2).getImm() == 1 && in operator()
32 B.getOperand(2).getImm() == 1 && "Unexpected EXRL target MCInst"); in operator()
35 if (A.getOperand(0).getReg() != B.getOperand(0).getReg()) in operator()
36 return A.getOperand(0).getReg() < B.getOperand(0).getReg(); in operator()
37 if (A.getOperand(1).getImm() != B.getOperand(1).getImm()) in operator()
38 return A.getOperand(1).getImm() < B.getOperand(1).getImm(); in operator()
39 if (A.getOperand(3).getReg() != B.getOperand(3).getReg()) in operator()
40 return A.getOperand(3).getReg() < B.getOperand(3).getReg(); in operator()
41 if (A.getOperand(4).getImm() != B.getOperand(4).getImm()) in operator()
42 return A.getOperand(4).getImm() < B.getOperand(4).getImm(); in operator()
H A DSystemZAsmPrinter.cpp37 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
63 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
64 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
66 .addImm(MI->getOperand(3).getImm()) in lowerRIEfLow()
67 .addImm(MI->getOperand(4).getImm()) in lowerRIEfLow()
68 .addImm(MI->getOperand(5).getImm()); in lowerRIEfLow()
117 .addReg(MI->getOperand(1).getReg()) in lowerSubvectorLoad()
118 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorLoad()
127 .addReg(MI->getOperand(1).getReg()) in lowerSubvectorStore()
128 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorStore()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVMergeBaseOffset.cpp96 !HiLUI.getOperand(1).isGlobal() || in INITIALIZE_PASS()
97 HiLUI.getOperand(1).getOffset() != 0 || in INITIALIZE_PASS()
104 !LoADDI->getOperand(2).isGlobal() || in INITIALIZE_PASS()
105 LoADDI->getOperand(2).getOffset() != 0) in INITIALIZE_PASS()
118 HiLUI.getOperand(1).setOffset(Offset); in foldOffset()
119 LoADDI.getOperand(2).setOffset(Offset); in foldOffset()
228 if (!OffsetTail.getOperand(1).isReg() || in matchShiftedOffset()
230 !OffsetTail.getOperand(2).isImm()) in matchShiftedOffset()
233 Offset = OffsetTail.getOperand(2).getImm(); in matchShiftedOffset()
346 if (UseMI.getOperand(1).isFI()) in detectAndFoldOffset()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp101 const MCOperand &Dst = MI->getOperand(0); in printInst()
102 const MCOperand &MO1 = MI->getOperand(1); in printInst()
103 const MCOperand &MO2 = MI->getOperand(2); in printInst()
104 const MCOperand &MO3 = MI->getOperand(3); in printInst()
124 const MCOperand &Dst = MI->getOperand(0); in printInst()
166 MI->getOperand(3).getImm() == -4) { in printInst()
195 MI->getOperand(4).getImm() == 4) { in printInst()
290 switch (MI->getOperand(0).getImm()) { in printInst()
997 if (MI->getOperand(OpNum).getReg()) { in printSBitModifierOperand()
1007 O << MI->getOperand(OpNum).getImm(); in printNoHashImmediate()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreISelDAGToDAG.cpp163 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
170 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
177 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
178 N->getOperand(2), N->getOperand(3) }; in Select()
184 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
185 N->getOperand(2), N->getOperand(3) }; in Select()
191 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
192 N->getOperand(2), N->getOperand(3) }; in Select()
198 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) }; in Select()
241 SDValue Chain = N->getOperand(0); in tryBRIND()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizer.cpp53 MI.getOperand(3).getMetadata()->getOperand(0)) in addConstantsToTrack()
105 while (MI.getOperand(NumOp).isReg()) { in foldConstantsIntoIntrinsics()
128 assert(MI.getOperand(2).isReg()); in insertBitcasts()
130 MIB.buildBitcast(MI.getOperand(0).getReg(), MI.getOperand(2).getReg()); in insertBitcasts()
151 if (MI->getOperand(0).isReg()) { in propagateSPIRVType()
215 Def->getOperand(0).setReg(NewReg); in insertAssignInstr()
333 MI.getOperand(0).setReg(NewReg); in processInstr()
406 assert(MI.getOperand(1).isReg()); in processSwitches()
415 assert(MI.getOperand(0).isReg() && MI.getOperand(1).isPredicate() && in processSwitches()
416 MI.getOperand(3).isReg()); in processSwitches()
[all …]
/llvm-project-15.0.7/llvm/unittests/IR/
H A DMDBuilderTest.cpp38 Metadata *Op = MD1->getOperand(0); in TEST_F()
52 EXPECT_TRUE(mdconst::hasa<ConstantInt>(R1->getOperand(0))); in TEST_F()
66 EXPECT_EQ(R0->getOperand(0), R0); in TEST_F()
67 EXPECT_EQ(R1->getOperand(0), R1); in TEST_F()
77 EXPECT_TRUE(isa<MDString>(R0->getOperand(0))); in TEST_F()
94 EXPECT_TRUE(isa<MDString>(N0->getOperand(0))); in TEST_F()
95 EXPECT_TRUE(isa<MDString>(N1->getOperand(0))); in TEST_F()
96 EXPECT_TRUE(isa<MDString>(N2->getOperand(0))); in TEST_F()
100 EXPECT_EQ(N0->getOperand(1), R); in TEST_F()
101 EXPECT_EQ(N1->getOperand(1), R); in TEST_F()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCompound.cpp211 Rt = L.getOperand(0); in getCompoundInsn()
222 Rt = L.getOperand(0); in getCompoundInsn()
223 Rs = L.getOperand(1); in getCompoundInsn()
236 Rs = L.getOperand(1); in getCompoundInsn()
237 Rt = L.getOperand(2); in getCompoundInsn()
249 Rs = L.getOperand(1); in getCompoundInsn()
250 Rt = L.getOperand(2); in getCompoundInsn()
262 Rs = L.getOperand(1); in getCompoundInsn()
263 Rt = L.getOperand(2); in getCompoundInsn()
283 Rs = L.getOperand(1); in getCompoundInsn()
[all …]
H A DHexagonMCDuplexInfo.cpp201 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
202 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
219 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
220 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
240 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
241 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
250 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
251 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
260 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
261 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DGISelKnownBits.cpp42 int64_t LogAlign = MI->getOperand(2).getImm(); in computeKnownAlignment()
46 int FrameIdx = MI->getOperand(1).getIndex(); in computeKnownAlignment()
59 return getKnownBits(MI.getOperand(0).getReg()); in getKnownBits()
329 computeKnownBitsMin(MI.getOperand(2).getReg(), MI.getOperand(3).getReg(), in computeKnownBitsImpl()
460 SrcBitWidth = MI.getOperand(2).getImm(); in computeKnownBitsImpl()
580 if (MI.getOperand(1).getReg() == R) { in computeKnownBitsImpl()
638 MachineOperand &Src = MI.getOperand(1); in computeNumSignBits()
648 Register Src = MI.getOperand(1).getReg(); in computeNumSignBits()
656 Register Src = MI.getOperand(1).getReg(); in computeNumSignBits()
680 Register Src = MI.getOperand(1).getReg(); in computeNumSignBits()
[all …]
H A DCombinerHelper.cpp811 Builder.buildCopy(MI.getOperand(0).getReg(), MI.getOperand(1).getReg()); in applySextTruncSextLoad()
1145 matchEqualDefs(MI.getOperand(2), UseMI.getOperand(2)) && in matchCombineDivRem()
1146 matchEqualDefs(MI.getOperand(1), UseMI.getOperand(1))) { in matchCombineDivRem()
1182 {MI.getOperand(1).getReg(), MI.getOperand(2).getReg()}); in applyCombineDivRem()
2480 return matchEqualDefs(MI.getOperand(2), MI.getOperand(3)) && in matchSelectSameVal()
2481 canReplaceReg(MI.getOperand(0).getReg(), MI.getOperand(2).getReg(), in matchSelectSameVal()
2486 return matchEqualDefs(MI.getOperand(1), MI.getOperand(2)) && in matchBinOpSameVal()
2487 canReplaceReg(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), in matchBinOpSameVal()
3058 MI.getOperand(1).setReg(Not->getOperand(0).getReg()); in applyXorOfAndWithSameReg()
4532 MI.getOperand(2).setReg(RHS->getOperand(2).getReg()); in matchReassocConstantInnerRHS()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp60 assert(Inst.getOperand(2).isImm()); in LowerLargeShift()
68 Inst.getOperand(2).setImm(Shift); in LowerLargeShift()
114 Inst.getOperand(0).setReg(RegOp1); in LowerCompactBranch()
115 Inst.getOperand(1).setReg(RegOp0); in LowerCompactBranch()
756 assert(MI.getOperand(OpNo).isReg()); in getMemEncoding()
772 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm4()
786 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm4Lsl1()
800 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm4Lsl2()
844 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm9()
858 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm11()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DMVETPAndVPTOptimisationsPass.cpp195 MIB.add(MI->getOperand(0)); in RevertWhileLoopSetup()
196 MIB.add(MI->getOperand(1)); in RevertWhileLoopSetup()
254 .add(WLSIt->getOperand(1)); in LowerWhileLoopStart()
472 VCTP->getOperand(0).getReg() != FirstVCTP->getOperand(0).getReg()) { in ConvertTailPredLoop()
588 MachineOperand &CondOP1 = Cond.getOperand(1), &CondOP2 = Cond.getOperand(2); in IsVPNOTEquivalent()
589 MachineOperand &PrevOP1 = Prev.getOperand(1), &PrevOP2 = Prev.getOperand(2); in IsVPNOTEquivalent()
1019 .add(MI.getOperand(0)) in ConvertVPSEL()
1020 .add(MI.getOperand(1)) in ConvertVPSEL()
1021 .add(MI.getOperand(1)) in ConvertVPSEL()
1023 .add(MI.getOperand(4)) in ConvertVPSEL()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp148 .add(MI.getOperand(0)) in expandMOVImm()
498 MI.getOperand(DOPIdx).getReg() != MI.getOperand(SrcIdx).getReg(); in expand_DestructiveOp()
507 (MI.getOperand(DOPIdx).getReg() != MI.getOperand(SrcIdx).getReg() && in expand_DestructiveOp()
508 MI.getOperand(DOPIdx).getReg() != MI.getOperand(Src2Idx).getReg()); in expand_DestructiveOp()
988 .add(MI.getOperand(1)) in expandMI()
989 .add(MI.getOperand(2)) in expandMI()
1133 .add(MI.getOperand(0)) in expandMI()
1134 .add(MI.getOperand(1)) in expandMI()
1135 .add(MI.getOperand(2)) in expandMI()
1205 .add(MI.getOperand(0)) in expandMI()
[all …]
/llvm-project-15.0.7/llvm/unittests/Analysis/
H A DAssumeBundleQueriesTest.cpp97 ASSERT_TRUE(hasTheRightValue(Assume, I->getOperand(0), in TEST()
99 ASSERT_TRUE(hasTheRightValue(Assume, I->getOperand(0), in TEST()
101 ASSERT_TRUE(hasTheRightValue(Assume, I->getOperand(0), in TEST()
121 ASSERT_TRUE(hasTheRightValue(Assume, I->getOperand(0), in TEST()
153 Assume, I->getOperand(0), in TEST()
188 I->getOperand(1)->dropDroppableUses(); in TEST()
189 I->getOperand(2)->dropDroppableUses(); in TEST()
190 I->getOperand(3)->dropDroppableUses(); in TEST()
192 Assume, I->getOperand(0), in TEST()
212 Value *Old = I->getOperand(0); in TEST()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiInstPrinter.cpp49 unsigned AluCode = MI->getOperand(3).getImm(); in usesGivenOffset()
56 unsigned AluCode = MI->getOperand(3).getImm(); in isPreIncrementForm()
61 unsigned AluCode = MI->getOperand(3).getImm(); in isPostIncrementForm()
66 if (MI->getOperand(2).getImm() < 0) in decIncOperator()
152 const MCOperand &Op = MI->getOperand(OpNo); in printOperand()
165 const MCOperand &Op = MI->getOperand(OpNo); in printMemImmOperand()
179 const MCOperand &Op = MI->getOperand(OpNo); in printHi16ImmOperand()
191 const MCOperand &Op = MI->getOperand(OpNo); in printHi16AndImmOperand()
203 const MCOperand &Op = MI->getOperand(OpNo); in printLo16AndImmOperand()
240 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemRiOperand()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp262 .add(I.getOperand(0)) in buildUnalignedStore()
343 .add(I.getOperand(0)) in select()
344 .add(I.getOperand(1)) in select()
355 .add(I.getOperand(0)) in select()
356 .add(I.getOperand(1)) in select()
362 .add(I.getOperand(0)) in select()
502 .add(I.getOperand(0)) in select()
538 .add(I.getOperand(0)) in select()
539 .add(I.getOperand(2)) in select()
540 .add(I.getOperand(1)) in select()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp2535 N0.getOperand(0) == N1.getOperand(1)) in visitADDLike()
2541 N0.getOperand(1) == N1.getOperand(0)) in visitADDLike()
2547 N0 == N1.getOperand(1).getOperand(0)) in visitADDLike()
2553 N0 == N1.getOperand(1).getOperand(1)) in visitADDLike()
2560 N0 == N1.getOperand(0).getOperand(1)) in visitADDLike()
3555 N0.getOperand(1).getOperand(0) == N1) in visitSUB()
3561 N0.getOperand(1).getOperand(1) == N1) in visitSUB()
5088 N00 = N0.getOperand(0).getOperand(0); in isSaturatingMinMax()
5089 N01 = N0.getOperand(0).getOperand(1); in isSaturatingMinMax()
15184 U->getOperand(0) == U->getOperand(1).getOperand(0) && in combineRepeatedFPDivisors()
[all …]

12345678910>>...51