|
Revision tags: llvmorg-20.1.0, llvmorg-20.1.0-rc3, llvmorg-20.1.0-rc2, llvmorg-20.1.0-rc1, llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7, llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1, llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2, llvmorg-14.0.0-rc1, llvmorg-15-init, llvmorg-13.0.1, llvmorg-13.0.1-rc3, llvmorg-13.0.1-rc2 |
|
| #
e92429d9 |
| 02-Dec-2021 |
Simon Moll <[email protected]> |
[VE][NFC] Cleanup redundant namespace wrapper
|
| #
1bd01def |
| 01-Dec-2021 |
Simon Pilgrim <[email protected]> |
[VE] Remove switch with only default case statement to fix MSVC warning. NFC.
|
|
Revision tags: llvmorg-13.0.1-rc1, llvmorg-13.0.0, llvmorg-13.0.0-rc4, llvmorg-13.0.0-rc3, llvmorg-13.0.0-rc2, llvmorg-13.0.0-rc1, llvmorg-14-init, llvmorg-12.0.1, llvmorg-12.0.1-rc4, llvmorg-12.0.1-rc3, llvmorg-12.0.1-rc2, llvmorg-12.0.1-rc1, llvmorg-12.0.0, llvmorg-12.0.0-rc5, llvmorg-12.0.0-rc4, llvmorg-12.0.0-rc3, llvmorg-12.0.0-rc2, llvmorg-11.1.0, llvmorg-11.1.0-rc3, llvmorg-12.0.0-rc1, llvmorg-13-init, llvmorg-11.1.0-rc2, llvmorg-11.1.0-rc1, llvmorg-11.0.1, llvmorg-11.0.1-rc2, llvmorg-11.0.1-rc1, llvmorg-11.0.0, llvmorg-11.0.0-rc6, llvmorg-11.0.0-rc5, llvmorg-11.0.0-rc4, llvmorg-11.0.0-rc3, llvmorg-11.0.0-rc2, llvmorg-11.0.0-rc1, llvmorg-12-init, llvmorg-10.0.1, llvmorg-10.0.1-rc4, llvmorg-10.0.1-rc3, llvmorg-10.0.1-rc2 |
|
| #
49e4faa0 |
| 10-Jun-2020 |
Kazushi (Jam) Marukawa <[email protected]> |
[VE] Support host memory access instructions in MC layer
Summary:
Add LHM/SHM instructions. Add regression tests for them of asmparser,
mccodeemitter, and disassembler. In order to add those instr
[VE] Support host memory access instructions in MC layer
Summary:
Add LHM/SHM instructions. Add regression tests for them of asmparser,
mccodeemitter, and disassembler. In order to add those instructions,
add new decode functions to disassembler, and add new print functions
to instprinter.
Differential Revision: https://reviews.llvm.org/D81535
show more ...
|
| #
b641c9f7 |
| 09-Jun-2020 |
Kazushi (Jam) Marukawa <[email protected]> |
[VE] Support rest of load/store instructions in MC layer
Summary:
Add DLD/DLDU/DLDL/PFCH/TS1AM/TS2AM/TS3AM/ATMAM/CAS instructions newly.
Add regression tests for them to asmparser, mccodeemitter, an
[VE] Support rest of load/store instructions in MC layer
Summary:
Add DLD/DLDU/DLDL/PFCH/TS1AM/TS2AM/TS3AM/ATMAM/CAS instructions newly.
Add regression tests for them to asmparser, mccodeemitter, and disassembler.
In order to add those instructions, change asmparser to support UImm0to2 and
UImm1 operands, add new decode functions to disassembler, and add new print
functions to instprinter.
Differential Revision: https://reviews.llvm.org/D81454
show more ...
|
| #
c95ba11a |
| 08-Jun-2020 |
Kazushi (Jam) Marukawa <[email protected]> |
[VE] Support control instructions in MC layer
Summary:
Add regression tests of asmparser, mccodeemitter, and disassembler for
control instructions. Add not defined LPM/SPM/LFR/SFR/SMIR/NOP/LCR/
SCR
[VE] Support control instructions in MC layer
Summary:
Add regression tests of asmparser, mccodeemitter, and disassembler for
control instructions. Add not defined LPM/SPM/LFR/SFR/SMIR/NOP/LCR/
SCR/TSCR/FIDCR control isntructions newly. Define MISC registers which
SMIR instruction reads and IC register which SIC instruction reads.
Change asmparser to support Zero, UImm3, and UImm6 operands and MISC
registers. Change instprinter to support MISC registers also.
Change to use auto to receive dyn_cast also.
Differential Revision: https://reviews.llvm.org/D81370
show more ...
|
|
Revision tags: llvmorg-10.0.1-rc1 |
|
| #
9aa67927 |
| 24-Apr-2020 |
Kazushi (Jam) Marukawa <[email protected]> |
[VE] Update floating-point arithmetic instructions
Summary:
Changing all mnemonic to match assembly instructions to simplify mnemonic
naming rules. This time update all floating-point arithmetic ins
[VE] Update floating-point arithmetic instructions
Summary:
Changing all mnemonic to match assembly instructions to simplify mnemonic
naming rules. This time update all floating-point arithmetic instructions.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D78768
show more ...
|
| #
ba4162c1 |
| 22-Apr-2020 |
Kazushi (Jam) Marukawa <[email protected]> |
[VE] Add alternative names to registers
Summary:
VE uses identical names "%s0-63" to all generic registers. Change to use
alternative name mechanism among all generic registers instead of hard-
cod
[VE] Add alternative names to registers
Summary:
VE uses identical names "%s0-63" to all generic registers. Change to use
alternative name mechanism among all generic registers instead of hard-
coding them.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D78174
show more ...
|
| #
015dee1a |
| 09-Apr-2020 |
Kazushi (Jam) Marukawa <[email protected]> |
[VE] Support (m)0 and (m)1 operands
Summary:
VE has special operands to represent 0b000...000111...111 (`(m)0`) and
0b111...111000...000 (`(m)1`) bit sequences. This patch supports those
operands n
[VE] Support (m)0 and (m)1 operands
Summary:
VE has special operands to represent 0b000...000111...111 (`(m)0`) and
0b111...111000...000 (`(m)1`) bit sequences. This patch supports those
operands not only in machine instructions but also in DAG lowering.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D77769
show more ...
|
| #
e981a46a |
| 06-Apr-2020 |
Kazushi (Jam) Marukawa <[email protected]> |
[VE] Update lea/load/store instructions
Summary:
Modify lea/load/store instructions to accept `disp(index, base)`
style addressing mode (called ASX format). Also, uniform the
number of DAG nodes to
[VE] Update lea/load/store instructions
Summary:
Modify lea/load/store instructions to accept `disp(index, base)`
style addressing mode (called ASX format). Also, uniform the
number of DAG nodes to have 3 operands for this ASX format
instructions, and update selectADDR functions to lower
appropriate MI.
Reviewers: arsenm, simoll, k-ishizaka
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D76822
show more ...
|
| #
b3cc5dce |
| 27-Mar-2020 |
Fangrui Song <[email protected]> |
[MCInstPrinter] Add parameter `Address` to MCInstPrinter::printAliasInstr. NFC
Follow-up of D72172.
|
| #
28a42dd1 |
| 25-Mar-2020 |
Kazushi (Jam) Marukawa <[email protected]> |
[VE] Change name of enum to CondCode
Summary: Change enum name for condition codes from CondCodes to CondCode.
Reviewers: arsenm, simoll, k-ishizaka
Reviewed By: arsenm
Subscribers: wdng, hiradit
[VE] Change name of enum to CondCode
Summary: Change enum name for condition codes from CondCodes to CondCode.
Reviewers: arsenm, simoll, k-ishizaka
Reviewed By: arsenm
Subscribers: wdng, hiraditya, llvm-commits
Tags: #llvm, #ve
Differential Revision: https://reviews.llvm.org/D76747
show more ...
|
|
Revision tags: llvmorg-10.0.0, llvmorg-10.0.0-rc6, llvmorg-10.0.0-rc5 |
|
| #
6bbbead7 |
| 17-Mar-2020 |
Kazushi (Jam) Marukawa <[email protected]> |
[VE] Move VEInstPrinter.cpp and VEInstPrinter.h into MCTargetDesc
Summary:
Move them into MCTargetDesc to follow other architectures (a263aa2).
Reviewed By: simoll
Differential Revision: https://r
[VE] Move VEInstPrinter.cpp and VEInstPrinter.h into MCTargetDesc
Summary:
Move them into MCTargetDesc to follow other architectures (a263aa2).
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D76270
show more ...
|