Lines Matching refs:getOperand
122 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm()
124 MI.getOperand(0).isRenamable() ? RegState::Renamable : 0; in expandMOVImm()
125 uint64_t Imm = MI.getOperand(1).getImm(); in expandMOVImm()
148 .add(MI.getOperand(0)) in expandMOVImm()
156 bool DstIsDead = MI.getOperand(0).isDead(); in expandMOVImm()
166 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm()
167 bool DstIsDead = MI.getOperand(0).isDead(); in expandMOVImm()
190 const MachineOperand &Dest = MI.getOperand(0); in expandCMP_SWAP()
191 Register StatusReg = MI.getOperand(1).getReg(); in expandCMP_SWAP()
192 bool StatusDead = MI.getOperand(1).isDead(); in expandCMP_SWAP()
195 assert(!MI.getOperand(2).isUndef() && "cannot handle undef"); in expandCMP_SWAP()
196 Register AddrReg = MI.getOperand(2).getReg(); in expandCMP_SWAP()
197 Register DesiredReg = MI.getOperand(3).getReg(); in expandCMP_SWAP()
198 Register NewReg = MI.getOperand(4).getReg(); in expandCMP_SWAP()
269 MachineOperand &DestLo = MI.getOperand(0); in expandCMP_SWAP_128()
270 MachineOperand &DestHi = MI.getOperand(1); in expandCMP_SWAP_128()
271 Register StatusReg = MI.getOperand(2).getReg(); in expandCMP_SWAP_128()
272 bool StatusDead = MI.getOperand(2).isDead(); in expandCMP_SWAP_128()
275 assert(!MI.getOperand(3).isUndef() && "cannot handle undef"); in expandCMP_SWAP_128()
276 Register AddrReg = MI.getOperand(3).getReg(); in expandCMP_SWAP_128()
277 Register DesiredLoReg = MI.getOperand(4).getReg(); in expandCMP_SWAP_128()
278 Register DesiredHiReg = MI.getOperand(5).getReg(); in expandCMP_SWAP_128()
279 Register NewLoReg = MI.getOperand(6).getReg(); in expandCMP_SWAP_128()
280 Register NewHiReg = MI.getOperand(7).getReg(); in expandCMP_SWAP_128()
447 Register DstReg = MI.getOperand(0).getReg(); in expand_DestructiveOp()
448 bool DstIsDead = MI.getOperand(0).isDead(); in expand_DestructiveOp()
451 assert(DstReg != MI.getOperand(3).getReg()); in expand_DestructiveOp()
458 if (DstReg == MI.getOperand(3).getReg()) { in expand_DestructiveOp()
474 if (DstReg == MI.getOperand(3).getReg()) { in expand_DestructiveOp()
478 } else if (DstReg == MI.getOperand(4).getReg()) { in expand_DestructiveOp()
497 DstReg != MI.getOperand(DOPIdx).getReg() || in expand_DestructiveOp()
498 MI.getOperand(DOPIdx).getReg() != MI.getOperand(SrcIdx).getReg(); in expand_DestructiveOp()
506 DstReg != MI.getOperand(DOPIdx).getReg() || in expand_DestructiveOp()
507 (MI.getOperand(DOPIdx).getReg() != MI.getOperand(SrcIdx).getReg() && in expand_DestructiveOp()
508 MI.getOperand(DOPIdx).getReg() != MI.getOperand(Src2Idx).getReg()); in expand_DestructiveOp()
563 .addReg(MI.getOperand(PredIdx).getReg()) in expand_DestructiveOp()
564 .addReg(MI.getOperand(DOPIdx).getReg()); in expand_DestructiveOp()
568 } else if (DstReg != MI.getOperand(DOPIdx).getReg()) { in expand_DestructiveOp()
574 .addReg(MI.getOperand(DOPIdx).getReg()); in expand_DestructiveOp()
586 DOP.addReg(MI.getOperand(DOPIdx).getReg(), RegState::Kill) in expand_DestructiveOp()
587 .add(MI.getOperand(PredIdx)) in expand_DestructiveOp()
588 .add(MI.getOperand(SrcIdx)); in expand_DestructiveOp()
593 DOP.add(MI.getOperand(PredIdx)) in expand_DestructiveOp()
594 .addReg(MI.getOperand(DOPIdx).getReg(), RegState::Kill) in expand_DestructiveOp()
595 .add(MI.getOperand(SrcIdx)); in expand_DestructiveOp()
598 DOP.add(MI.getOperand(PredIdx)) in expand_DestructiveOp()
599 .addReg(MI.getOperand(DOPIdx).getReg(), RegState::Kill) in expand_DestructiveOp()
600 .add(MI.getOperand(SrcIdx)) in expand_DestructiveOp()
601 .add(MI.getOperand(Src2Idx)); in expand_DestructiveOp()
620 Register SizeReg = MI.getOperand(0).getReg(); in expandSetTagLoop()
621 Register AddressReg = MI.getOperand(1).getReg(); in expandSetTagLoop()
631 unsigned Size = MI.getOperand(2).getImm(); in expandSetTagLoop()
696 int ImmOffset = MI.getOperand(2).getImm() + Offset; in expandSVESpillFill()
697 bool Kill = (Offset + 1 == N) ? MI.getOperand(1).isKill() : false; in expandSVESpillFill()
702 TRI->getSubReg(MI.getOperand(0).getReg(), AArch64::zsub0 + Offset), in expandSVESpillFill()
704 .addReg(MI.getOperand(1).getReg(), getKillRegState(Kill)) in expandSVESpillFill()
721 MachineOperand &RVTarget = MI.getOperand(0); in expandCALL_RVMARKER()
722 MachineOperand &CallTarget = MI.getOperand(1); in expandCALL_RVMARKER()
733 while (!MI.getOperand(RegMaskStartIdx).isRegMask()) { in expandCALL_RVMARKER()
734 auto MOP = MI.getOperand(RegMaskStartIdx); in expandCALL_RVMARKER()
772 MachineOperand &CallTarget = MI.getOperand(0); in expandCALL_BTI()
796 Register CtxReg = MBBI->getOperand(0).getReg(); in expandStoreSwiftAsyncContext()
797 Register BaseReg = MBBI->getOperand(1).getReg(); in expandStoreSwiftAsyncContext()
798 int Offset = MBBI->getOperand(2).getImm(); in expandStoreSwiftAsyncContext()
875 Register DstReg = MI.getOperand(0).getReg(); in expandMI()
876 if (DstReg == MI.getOperand(3).getReg()) { in expandMI()
881 .add(MI.getOperand(0)) in expandMI()
882 .add(MI.getOperand(3)) in expandMI()
883 .add(MI.getOperand(2)) in expandMI()
884 .add(MI.getOperand(1)); in expandMI()
885 } else if (DstReg == MI.getOperand(2).getReg()) { in expandMI()
890 .add(MI.getOperand(0)) in expandMI()
891 .add(MI.getOperand(2)) in expandMI()
892 .add(MI.getOperand(3)) in expandMI()
893 .add(MI.getOperand(1)); in expandMI()
896 if (DstReg == MI.getOperand(1).getReg()) { in expandMI()
900 .add(MI.getOperand(0)) in expandMI()
901 .add(MI.getOperand(1)) in expandMI()
902 .add(MI.getOperand(2)) in expandMI()
903 .add(MI.getOperand(3)); in expandMI()
910 getRenamableRegState(MI.getOperand(0).isRenamable())) in expandMI()
911 .add(MI.getOperand(1)) in expandMI()
912 .add(MI.getOperand(1)); in expandMI()
916 .add(MI.getOperand(0)) in expandMI()
919 getRenamableRegState(MI.getOperand(0).isRenamable())) in expandMI()
920 .add(MI.getOperand(2)) in expandMI()
921 .add(MI.getOperand(3)); in expandMI()
987 MIB1.addReg(MI.getOperand(0).getReg(), RegState::Define) in expandMI()
988 .add(MI.getOperand(1)) in expandMI()
989 .add(MI.getOperand(2)) in expandMI()
998 Register DstReg = MI.getOperand(0).getReg(); in expandMI()
999 const MachineOperand &MO1 = MI.getOperand(1); in expandMI()
1027 unsigned DstFlags = MI.getOperand(0).getTargetFlags(); in expandMI()
1033 Register DstReg = MI.getOperand(0).getReg(); in expandMI()
1035 .add(MI.getOperand(0)) in expandMI()
1069 const BlockAddress *BA = MI.getOperand(1).getBlockAddress(); in expandMI()
1070 assert(MI.getOperand(1).getOffset() == 0 && "unexpected offset"); in expandMI()
1075 Register DstReg = MI.getOperand(0).getReg(); in expandMI()
1096 Register DstReg = MI.getOperand(0).getReg(); in expandMI()
1100 .add(MI.getOperand(1)); in expandMI()
1102 if (MI.getOperand(1).getTargetFlags() & AArch64II::MO_TAGGED) { in expandMI()
1110 auto Tag = MI.getOperand(1); in expandMI()
1121 .add(MI.getOperand(0)) in expandMI()
1123 .add(MI.getOperand(2)) in expandMI()
1133 .add(MI.getOperand(0)) in expandMI()
1134 .add(MI.getOperand(1)) in expandMI()
1135 .add(MI.getOperand(2)) in expandMI()
1141 Register DstReg = MI.getOperand(0).getReg(); in expandMI()
1205 .add(MI.getOperand(0)) in expandMI()
1206 .add(MI.getOperand(1)); in expandMI()
1229 SrcReg = MI.getOperand(0).getReg(); in expandMI()
1234 .add(MI.getOperand(0)) in expandMI()
1236 .add(MI.getOperand(2)); in expandMI()
1241 int64_t Offset = MI.getOperand(2).getImm(); in expandMI()
1244 .add(MI.getOperand(0)) in expandMI()
1245 .add(MI.getOperand(1)) in expandMI()
1247 .add(MI.getOperand(4)); in expandMI()