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Searched refs:SrcVT (Results 1 – 25 of 45) sorted by relevance

12

/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp841 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 || in PPCEmitCmp()
842 SrcVT == MVT::i8 || SrcVT == MVT::i1) { in PPCEmitCmp()
1079 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 && in SelectIToFP()
1080 SrcVT != MVT::i32 && SrcVT != MVT::i64) in SelectIToFP()
1117 if (SrcVT == MVT::i8 || SrcVT == MVT::i16) { in SelectIToFP()
1121 SrcVT = MVT::i64; in SelectIToFP()
1189 MVT DstVT, SrcVT; in SelectFPToI() local
1207 if (SrcVT != MVT::f32 && SrcVT != MVT::f64) in SelectFPToI()
1812 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 && SrcVT != MVT::i32) in PPCEmitIntExt()
1882 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16) in SelectTrunc()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1093 MVT DstVT, SrcVT; in selectFPToInt() local
1106 if (!isTypeLegal(SrcTy, SrcVT)) in selectFPToInt()
1109 if (SrcVT != MVT::f32 && SrcVT != MVT::f64) in selectFPToInt()
1204 MVT SrcVT = ArgVT; in processCallArgs() local
1212 MVT SrcVT = ArgVT; in processCallArgs() local
1776 EVT SrcVT, DestVT; in selectTrunc() local
1780 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8) in selectTrunc()
1826 switch (SrcVT.SimpleTy) { in emitIntSExt32r1()
1844 switch (SrcVT.SimpleTy) { in emitIntSExt32r2()
1870 switch (SrcVT.SimpleTy) { in emitIntZExt()
[all …]
H A DMipsMSAInstrInfo.td3606 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3608 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3609 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
3666 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3674 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3679 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
3683 class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT,
3687 class MSABitconvertReverseBInDPat<ValueType DstVT, ValueType SrcVT,
3689 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3693 (SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27),
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp2813 if (SrcVT == MVT::f128 || SrcVT == MVT::f16) in selectFPToInt()
2854 if (SrcVT == MVT::i16 || SrcVT == MVT::i8 || SrcVT == MVT::i1) { in selectIntToFP()
3882 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 && in selectTrunc()
4027 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 || in emitLSL_ri()
4028 SrcVT == MVT::i32 || SrcVT == MVT::i64) && in emitLSL_ri()
4130 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 || in emitLSR_ri()
4131 SrcVT == MVT::i32 || SrcVT == MVT::i64) && in emitLSR_ri()
4246 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 || in emitASR_ri()
4247 SrcVT == MVT::i32 || SrcVT == MVT::i64) && in emitASR_ri()
4332 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && in emitIntExt()
[all …]
H A DAArch64ISelLowering.cpp3868 SrcVT = F32VT; in LowerVectorFP_TO_INT_SAT()
3915 if (SrcVT.isVector()) in LowerFP_TO_INT_SAT()
3927 SrcVT = MVT::f32; in LowerFP_TO_INT_SAT()
3928 } else if (SrcVT != MVT::f64 && SrcVT != MVT::f32 && SrcVT != MVT::f16) in LowerFP_TO_INT_SAT()
3933 if ((SrcVT == MVT::f64 || SrcVT == MVT::f32 || in LowerFP_TO_INT_SAT()
9456 assert((SrcVT.is64BitVector() || SrcVT.is128BitVector()) && in ReconstructShuffle()
18771 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumMaskElts); in performSelectCombine()
18946 if ((SrcVT != MVT::nxv4f32) && (SrcVT != MVT::nxv2f64)) in performScatterStoreCombine()
20016 if (VT != MVT::i16 || (SrcVT != MVT::f16 && SrcVT != MVT::bf16)) in ReplaceBITCASTResults()
21469 SrcVT, in LowerReductionToSVE()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp1002 EVT SrcVT = Src.getValueType(); in ExpandANY_EXTEND_VECTOR_INREG() local
1007 if (SrcVT.bitsLE(VT)) { in ExpandANY_EXTEND_VECTOR_INREG()
1011 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getScalarType(), in ExpandANY_EXTEND_VECTOR_INREG()
1013 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, SrcVT, DAG.getUNDEF(SrcVT), in ExpandANY_EXTEND_VECTOR_INREG()
1029 DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask)); in ExpandANY_EXTEND_VECTOR_INREG()
1036 EVT SrcVT = Src.getValueType(); in ExpandSIGN_EXTEND_VECTOR_INREG() local
1061 EVT SrcVT = Src.getValueType(); in ExpandZERO_EXTEND_VECTOR_INREG() local
1066 if (SrcVT.bitsLE(VT)) { in ExpandZERO_EXTEND_VECTOR_INREG()
1070 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getScalarType(), in ExpandZERO_EXTEND_VECTOR_INREG()
1072 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, SrcVT, DAG.getUNDEF(SrcVT), in ExpandZERO_EXTEND_VECTOR_INREG()
[all …]
H A DTargetLowering.cpp686 if (SrcVT == DstVT) in SimplifyMultipleUseDemandedBits()
721 unsigned NumSrcElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; in SimplifyMultipleUseDemandedBits()
2240 unsigned InElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; in SimplifyDemandedBits()
2277 unsigned InElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; in SimplifyDemandedBits()
2329 unsigned InElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; in SimplifyDemandedBits()
2479 SrcVT != MVT::f128) { in SimplifyDemandedBits()
2526 unsigned NumSrcElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; in SimplifyDemandedBits()
2536 if (SrcVT.isVector()) { in SimplifyDemandedBits()
2885 if (!SrcVT.isVector()) in SimplifyDemandedVectorElts()
7516 if (SrcVT.isVector() && (!isOperationLegalOrCustom(ISD::SRL, SrcVT) || in expandUINT_TO_FP()
[all …]
H A DLegalizeDAG.cpp723 EVT SrcVT = LD->getMemoryVT(); in LegalizeLoadOps() local
724 TypeSize SrcWidth = SrcVT.getSizeInBits(); in LegalizeLoadOps()
736 (SrcVT != MVT::i1 || in LegalizeLoadOps()
914 assert(!SrcVT.isVector() && in LegalizeLoadOps()
1739 EVT SrcVT = SrcOp.getValueType(); in EmitStackConvert() local
1744 if ((SrcVT.bitsGT(SlotVT) && in EmitStackConvert()
1764 if (SrcVT.bitsGT(SlotVT)) in EmitStackConvert()
2327 EVT SrcVT = Op0.getValueType(); in ExpandLegalINT_TO_FP() local
2402 if (((SrcVT == MVT::i32 || SrcVT == MVT::i64) && DestVT == MVT::f32) || in ExpandLegalINT_TO_FP()
2467 SrcVT.getSizeInBits() - 1 && in ExpandLegalINT_TO_FP()
[all …]
H A DFastISel.cpp1378 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType()); in selectCast() local
1381 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other || in selectCast()
1391 if (!TLI.isTypeLegal(SrcVT)) in selectCast()
1399 Register ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), in selectCast()
1416 MVT SrcVT = SrcEVT.getSimpleVT(); in selectBitCast() local
1423 if (SrcVT == DstVT) { in selectBitCast()
1429 Register ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0); in selectBitCast()
1783 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType()); in selectOperator() local
1785 if (DstVT.bitsGT(SrcVT)) in selectOperator()
1787 if (DstVT.bitsLT(SrcVT)) in selectOperator()
H A DLegalizeFloatTypes.cpp948 static RTLIB::Libcall findFPToIntLibcall(EVT SrcVT, EVT RetVT, EVT &Promoted, in findFPToIntLibcall() argument
957 LC = Signed ? RTLIB::getFPTOSINT(SrcVT, Promoted) in findFPToIntLibcall()
958 : RTLIB::getFPTOUINT(SrcVT, Promoted); in findFPToIntLibcall()
1670 EVT SrcVT = Src.getValueType(); in ExpandFloatRes_XINT_TO_FP() local
1683 if (SrcVT.bitsLE(MVT::i32)) { in ExpandFloatRes_XINT_TO_FP()
1695 if (SrcVT.bitsLE(MVT::i64)) { in ExpandFloatRes_XINT_TO_FP()
1699 } else if (SrcVT.bitsLE(MVT::i128)) { in ExpandFloatRes_XINT_TO_FP()
1715 if (isSigned || SrcVT.bitsLE(MVT::i32)) { in ExpandFloatRes_XINT_TO_FP()
1727 SrcVT = Src.getValueType(); in ExpandFloatRes_XINT_TO_FP()
1735 switch (SrcVT.getSimpleVT().SimpleTy) { in ExpandFloatRes_XINT_TO_FP()
[all …]
H A DLegalizeVectorTypes.cpp548 EVT SrcVT = Src.getValueType(); in ScalarizeVecRes_FP_TO_XINT_SAT() local
2182 EVT SrcVT = N->getOperand(0).getValueType(); in SplitVecRes_ExtendOp() local
2200 if (SrcVT.getVectorElementCount().isKnownEven() && in SplitVecRes_ExtendOp()
2203 EVT NewSrcVT = SrcVT.widenIntegerVectorElementType(Ctx); in SplitVecRes_ExtendOp()
2204 EVT SplitSrcVT = SrcVT.getHalfNumVectorElementsVT(Ctx); in SplitVecRes_ExtendOp()
2627 EVT SrcVT = N->getOperand(0).getValueType(); in SplitVecRes_FP_TO_XINT_SAT() local
4368 EVT SrcVT = Src.getValueType(); in WidenVecRes_FP_TO_XINT_SAT() local
4373 SrcVT = Src.getValueType(); in WidenVecRes_FP_TO_XINT_SAT()
4377 if (WidenNumElts != SrcVT.getVectorElementCount()) in WidenVecRes_FP_TO_XINT_SAT()
5693 EVT SrcVT = Src.getValueType(); in WidenVecOp_FP_TO_XINT_SAT() local
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.td310 class isFloatType<ValueType SrcVT> {
311 bit ret = !or(!eq(SrcVT.Value, f16.Value),
312 !eq(SrcVT.Value, f32.Value),
313 !eq(SrcVT.Value, f64.Value),
326 class isIntType<ValueType SrcVT> {
327 bit ret = !or(!eq(SrcVT.Value, i8.Value),
328 !eq(SrcVT.Value, i16.Value),
329 !eq(SrcVT.Value, i32.Value),
330 !eq(SrcVT.Value, i64.Value),
339 class isPackedType<ValueType SrcVT> {
[all …]
H A DAMDGPUISelLowering.cpp2441 EVT SrcVT = Src.getValueType(); in LowerUINT_TO_FP() local
2443 if (SrcVT == MVT::i16) { in LowerUINT_TO_FP()
2478 EVT SrcVT = Src.getValueType(); in LowerSINT_TO_FP() local
2480 if (SrcVT == MVT::i16) { in LowerSINT_TO_FP()
2518 EVT SrcVT = Src.getValueType(); in LowerFP_TO_INT64() local
2520 assert(SrcVT == MVT::f32 || SrcVT == MVT::f64); in LowerFP_TO_INT64()
2546 if (SrcVT == MVT::f64) { in LowerFP_TO_INT64()
2697 if (DestVT == MVT::i16 && (SrcVT == MVT::f32 || SrcVT == MVT::f64)) { in LowerFP_TO_INT()
2704 if (SrcVT == MVT::f16 || in LowerFP_TO_INT()
2714 if (DestVT == MVT::i64 && (SrcVT == MVT::f32 || SrcVT == MVT::f64)) in LowerFP_TO_INT()
[all …]
H A DSIISelLowering.h266 EVT SrcVT) const override;
325 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMFastISel.cpp1342 MVT SrcVT = SrcEVT.getSimpleVT(); in ARMEmitCmp() local
1358 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 || in ARMEmitCmp()
1359 SrcVT == MVT::i1) { in ARMEmitCmp()
1373 if (SrcVT == MVT::f32 || SrcVT == MVT::f64) in ARMEmitCmp()
1381 switch (SrcVT.SimpleTy) { in ARMEmitCmp()
1537 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIToFP() local
1538 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8) in SelectIToFP()
1545 if (SrcVT == MVT::i16 || SrcVT == MVT::i8) { in SelectIToFP()
2585 EVT SrcVT, DestVT; in SelectTrunc() local
2589 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8) in SelectTrunc()
[all …]
H A DARMISelLowering.h454 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
617 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FastISel.cpp1242 if (SrcVT != DstVT) { in X86SelectRet()
1243 if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16) in X86SelectRet()
1251 if (SrcVT == MVT::i1) { in X86SelectRet()
1256 SrcVT = MVT::i8; in X86SelectRet()
1548 if (SrcVT == MVT::i1) { in X86SelectZExt()
1551 SrcVT = MVT::i8; in X86SelectZExt()
1606 if (SrcVT == MVT::i1) { in X86SelectSExt()
1617 SrcVT = MVT::i8; in X86SelectSExt()
2406 if (SrcVT != MVT::i32 && SrcVT != MVT::i64) in X86SelectIntToFP()
2532 if (SrcVT == MVT::i8) { in X86SelectTrunc()
[all …]
H A DX86ISelLowering.cpp12296 SrcVT = MVT::getVectorVT(SrcVT, NumSrcElts); in matchShuffleAsVTRUNC()
20824 if (SrcVT != MVT::f32 && SrcVT != MVT::f64) in lowerFPToIntToFP()
21025 if (SrcVT == MVT::v2i64 || SrcVT == MVT::v4i64) in LowerSINT_TO_FP()
21031 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 && in LowerSINT_TO_FP()
22449 (SrcVT == MVT::v4f64 || SrcVT == MVT::v4f32 || SrcVT == MVT::v8f32) && in LowerFP_TO_INT()
22481 (SrcVT == MVT::v2f64 || SrcVT == MVT::v4f64 || SrcVT == MVT::v4f32) && in LowerFP_TO_INT()
22693 if (SrcVT != MVT::f32 && SrcVT != MVT::f64 && SrcVT != MVT::f80) { in LRINT_LLRINTHelper()
31256 assert((SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8 || in LowerBITCAST()
40054 if ((SrcVT == MVT::v2f64 || SrcVT == MVT::v4f32 || SrcVT == MVT::v2i64 || in combineTargetShuffle()
42751 (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) && in combineBitcast()
[all …]
H A DX86SelectionDAGInfo.cpp250 EVT SrcVT = Src.getValueType(); in emitConstantSizeRepmov() local
254 DAG.getNode(ISD::ADD, dl, SrcVT, Src, DAG.getConstant(Offset, dl, SrcVT)), in emitConstantSizeRepmov()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTypePromotion.cpp923 EVT SrcVT = TLI->getValueType(DL, I->getType()); in runOnFunction() local
924 if (SrcVT.isSimple() && TLI->isTypeLegal(SrcVT.getSimpleVT())) in runOnFunction()
927 if (TLI->getTypeAction(*Ctx, SrcVT) != in runOnFunction()
930 EVT PromotedVT = TLI->getTypeToTransformTo(*Ctx, SrcVT); in runOnFunction()
/llvm-project-15.0.7/llvm/lib/Transforms/Scalar/
H A DScalarizer.cpp744 VectorType *SrcVT = dyn_cast<VectorType>(BCI.getSrcTy()); in visitBitCastInst() local
745 if (!DstVT || !SrcVT) in visitBitCastInst()
749 unsigned SrcNumElems = cast<FixedVectorType>(SrcVT)->getNumElements(); in visitBitCastInst()
781 auto *MidTy = FixedVectorType::get(SrcVT->getElementType(), FanIn); in visitBitCastInst()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h365 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
367 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
H A DRISCVISelLowering.cpp4350 MVT SrcVT = Src.getSimpleValueType(); in lowerVectorTruncLike() local
4357 MVT ContainerVT = SrcVT; in lowerVectorTruncLike()
4363 if (SrcVT.isFixedLengthVector()) { in lowerVectorTruncLike()
4387 if (SrcVT.isFixedLengthVector()) in lowerVectorTruncLike()
4409 MVT SrcVT = Src.getSimpleValueType(); in lowerVectorFPExtendOrRoundLike() local
6334 MVT SrcVT = Src.getSimpleValueType(); in lowerVPFPIntConvOp() local
6337 SrcVT = getContainerForFixedLengthVector(SrcVT); in lowerVPFPIntConvOp()
6353 if (SrcVT.isInteger()) { in lowerVPFPIntConvOp()
6393 if (SrcVT.isInteger()) { in lowerVPFPIntConvOp()
9361 EVT SrcVT = N0.getValueType(); in PerformDAGCombine() local
[all …]
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2657 EVT SrcVT = In.getValueType(); in truncateVectorWithNARROW() local
2660 if (SrcVT == DstVT) in truncateVectorWithNARROW()
2663 unsigned SrcSizeInBits = SrcVT.getSizeInBits(); in truncateVectorWithNARROW()
2664 unsigned NumElems = SrcVT.getVectorNumElements(); in truncateVectorWithNARROW()
2671 EVT PackedSVT = EVT::getIntegerVT(Ctx, SrcVT.getScalarSizeInBits() / 2); in truncateVectorWithNARROW()
2676 if (SrcVT.getScalarSizeInBits() > 16) { in truncateVectorWithNARROW()
2689 if (SrcVT.is256BitVector() && DstVT.is128BitVector()) { in truncateVectorWithNARROW()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetLowering.h2860 virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const { in isFPExtFree() argument
2861 assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() && in isFPExtFree()
2878 EVT DestVT, EVT SrcVT) const { in isFPExtFoldable() argument
2879 assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() && in isFPExtFoldable()
2881 return isFPExtFree(DestVT, SrcVT); in isFPExtFoldable()
3002 virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument

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