Lines Matching refs:SrcVT
833 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const { in isNarrowingProfitable() argument
840 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32; in isNarrowingProfitable()
1271 EVT SrcVT = Op.getOperand(0).getValueType(); in LowerEXTRACT_SUBVECTOR() local
1274 if (((SrcVT == MVT::v4f16 && VT == MVT::v2f16) || in LowerEXTRACT_SUBVECTOR()
1275 (SrcVT == MVT::v4i16 && VT == MVT::v2i16)) && in LowerEXTRACT_SUBVECTOR()
1279 if (((SrcVT == MVT::v8f16 && VT == MVT::v4f16) || in LowerEXTRACT_SUBVECTOR()
1280 (SrcVT == MVT::v8i16 && VT == MVT::v4i16)) && in LowerEXTRACT_SUBVECTOR()
1284 if (((SrcVT == MVT::v16f16 && VT == MVT::v8f16) || in LowerEXTRACT_SUBVECTOR()
1285 (SrcVT == MVT::v16i16 && VT == MVT::v8i16)) && in LowerEXTRACT_SUBVECTOR()
2441 EVT SrcVT = Src.getValueType(); in LowerUINT_TO_FP() local
2443 if (SrcVT == MVT::i16) { in LowerUINT_TO_FP()
2453 assert(SrcVT == MVT::i64 && "operation should be legal"); in LowerUINT_TO_FP()
2478 EVT SrcVT = Src.getValueType(); in LowerSINT_TO_FP() local
2480 if (SrcVT == MVT::i16) { in LowerSINT_TO_FP()
2490 assert(SrcVT == MVT::i64 && "operation should be legal"); in LowerSINT_TO_FP()
2518 EVT SrcVT = Src.getValueType(); in LowerFP_TO_INT64() local
2520 assert(SrcVT == MVT::f32 || SrcVT == MVT::f64); in LowerFP_TO_INT64()
2531 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, SrcVT, Src); in LowerFP_TO_INT64()
2533 if (Signed && SrcVT == MVT::f32) { in LowerFP_TO_INT64()
2542 Trunc = DAG.getNode(ISD::FABS, SL, SrcVT, Trunc); in LowerFP_TO_INT64()
2546 if (SrcVT == MVT::f64) { in LowerFP_TO_INT64()
2548 SL, SrcVT); in LowerFP_TO_INT64()
2550 SL, SrcVT); in LowerFP_TO_INT64()
2553 SrcVT); in LowerFP_TO_INT64()
2555 SrcVT); in LowerFP_TO_INT64()
2558 SDValue Mul = DAG.getNode(ISD::FMUL, SL, SrcVT, Trunc, K0); in LowerFP_TO_INT64()
2560 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, SrcVT, Mul); in LowerFP_TO_INT64()
2562 SDValue Fma = DAG.getNode(ISD::FMA, SL, SrcVT, FloorMul, K1, Trunc); in LowerFP_TO_INT64()
2564 SDValue Hi = DAG.getNode((Signed && SrcVT == MVT::f64) ? ISD::FP_TO_SINT in LowerFP_TO_INT64()
2572 if (Signed && SrcVT == MVT::f32) { in LowerFP_TO_INT64()
2689 EVT SrcVT = Src.getValueType(); in LowerFP_TO_INT() local
2693 if (SrcVT == MVT::f16 && DestVT == MVT::i16) in LowerFP_TO_INT()
2697 if (DestVT == MVT::i16 && (SrcVT == MVT::f32 || SrcVT == MVT::f64)) { in LowerFP_TO_INT()
2704 if (SrcVT == MVT::f16 || in LowerFP_TO_INT()
2705 (SrcVT == MVT::f32 && Src.getOpcode() == ISD::FP16_TO_FP)) { in LowerFP_TO_INT()
2714 if (DestVT == MVT::i64 && (SrcVT == MVT::f32 || SrcVT == MVT::f64)) in LowerFP_TO_INT()
2976 EVT SrcVT = Src.getValueType(); in performAssertSZExtCombine() local
2977 if (SrcVT.bitsGE(ExtVT)) { in performAssertSZExtCombine()
2978 SDValue NewInReg = DAG.getNode(N->getOpcode(), SL, SrcVT, Src, N1); in performAssertSZExtCombine()
3237 EVT SrcVT = Src.getValueType(); in performTruncateCombine() local
3238 if (SrcVT.getScalarSizeInBits() > 32 && in performTruncateCombine()
3892 EVT SrcVT = Src.getValueType(); in performFNegCombine() local
3895 SDValue IntFNeg = DAG.getNode(ISD::XOR, SL, SrcVT, Src, in performFNegCombine()
3896 DAG.getConstant(0x8000, SL, SrcVT)); in performFNegCombine()
3917 EVT SrcVT = Src.getValueType(); in performFAbsCombine() local
3920 SDValue IntFAbs = DAG.getNode(ISD::AND, SL, SrcVT, Src, in performFAbsCombine()
3921 DAG.getConstant(0x7fff, SL, SrcVT)); in performFAbsCombine()
3960 EVT SrcVT = Src.getValueType(); in PerformDAGCombine() local
3963 if (SrcVT.getVectorNumElements() == NElts) { in PerformDAGCombine()
3968 for (unsigned I = 0, E = SrcVT.getVectorNumElements(); I != E; ++I) { in PerformDAGCombine()