197   bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
232   unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
257   unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
260   unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
263   unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
1160   MVT SrcVT = RetVT;  in emitAddSub()  local
1186     LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt);  in emitAddSub()
1275     RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt);  in emitAddSub()
2812   EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true);  in selectFPToInt()  local
2813   if (SrcVT == MVT::f128 || SrcVT == MVT::f16)  in selectFPToInt()
2817   if (SrcVT == MVT::f64) {  in selectFPToInt()
2851   EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true);  in selectIntToFP()  local
2854   if (SrcVT == MVT::i16 || SrcVT == MVT::i8 || SrcVT == MVT::i1) {  in selectIntToFP()
2856         emitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed);  in selectIntToFP()
2862   if (SrcVT == MVT::i64) {  in selectIntToFP()
3022       MVT SrcVT = ArgVT;  in processCallArgs()  local
3023       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);  in processCallArgs()
3032       MVT SrcVT = ArgVT;  in processCallArgs()  local
3033       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);  in processCallArgs()
3879   MVT SrcVT = SrcEVT.getSimpleVT();  in selectTrunc()  local
3882   if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 &&  in selectTrunc()
3883       SrcVT != MVT::i8)  in selectTrunc()
3899   if (SrcVT == MVT::i64) {  in selectTrunc()
4023 unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0,  in emitLSL_ri()  argument
4025   assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&  in emitLSL_ri()
4027   assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||  in emitLSL_ri()
4028           SrcVT == MVT::i32 || SrcVT == MVT::i64) &&  in emitLSL_ri()
4036   unsigned SrcBits = SrcVT.getSizeInBits();  in emitLSL_ri()
4042     if (RetVT == SrcVT) {  in emitLSL_ri()
4049       return emitIntExt(SrcVT, Op0, RetVT, IsZExt);  in emitLSL_ri()
4089   if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {  in emitLSL_ri()
4126 unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,  in emitLSR_ri()  argument
4128   assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&  in emitLSR_ri()
4130   assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||  in emitLSR_ri()
4131           SrcVT == MVT::i32 || SrcVT == MVT::i64) &&  in emitLSR_ri()
4139   unsigned SrcBits = SrcVT.getSizeInBits();  in emitLSR_ri()
4145     if (RetVT == SrcVT) {  in emitLSR_ri()
4152       return emitIntExt(SrcVT, Op0, RetVT, IsZExt);  in emitLSR_ri()
4190     Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt);  in emitLSR_ri()
4193     SrcVT = RetVT;  in emitLSR_ri()
4194     SrcBits = SrcVT.getSizeInBits();  in emitLSR_ri()
4205   if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {  in emitLSR_ri()
4242 unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,  in emitASR_ri()  argument
4244   assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&  in emitASR_ri()
4246   assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||  in emitASR_ri()
4247           SrcVT == MVT::i32 || SrcVT == MVT::i64) &&  in emitASR_ri()
4255   unsigned SrcBits = SrcVT.getSizeInBits();  in emitASR_ri()
4261     if (RetVT == SrcVT) {  in emitASR_ri()
4268       return emitIntExt(SrcVT, Op0, RetVT, IsZExt);  in emitASR_ri()
4310   if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {  in emitASR_ri()
4322 unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,  in emitIntExt()  argument
4332       ((SrcVT !=  MVT::i1) && (SrcVT !=  MVT::i8) &&  in emitIntExt()
4333        (SrcVT !=  MVT::i16) && (SrcVT !=  MVT::i32)))  in emitIntExt()
4339   switch (SrcVT.SimpleTy) {  in emitIntExt()
4432                                          MVT SrcVT) {  in optimizeIntExtLoad()  argument
4460   if (RetVT != MVT::i64 || SrcVT > MVT::i32) {  in optimizeIntExtLoad()
4489   MVT SrcVT;  in selectIntExt()  local
4493   if (!isTypeSupported(I->getOperand(0)->getType(), SrcVT))  in selectIntExt()
4497   if (optimizeIntExtLoad(I, RetVT, SrcVT))  in selectIntExt()
4508       if (RetVT == MVT::i64 && SrcVT != MVT::i64) {  in selectIntExt()
4523   unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt);  in selectIntExt()
4590       MVT SrcVT = VT;  in selectMul()  local
4596             SrcVT = VT;  in selectMul()
4605             SrcVT = VT;  in selectMul()
4617           emitLSL_ri(VT, SrcVT, Src0Reg, ShiftVal, IsZExt);  in selectMul()
4653     MVT SrcVT = RetVT;  in selectShift()  local
4660           SrcVT = TmpVT;  in selectShift()
4669           SrcVT = TmpVT;  in selectShift()
4683       ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);  in selectShift()
4686       ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);  in selectShift()
4689       ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);  in selectShift()
4729   MVT RetVT, SrcVT;  in selectBitCast()  local
4731   if (!isTypeLegal(I->getOperand(0)->getType(), SrcVT))  in selectBitCast()
4737   if (RetVT == MVT::f32 && SrcVT == MVT::i32)  in selectBitCast()
4739   else if (RetVT == MVT::f64 && SrcVT == MVT::i64)  in selectBitCast()
4741   else if (RetVT == MVT::i32 && SrcVT == MVT::f32)  in selectBitCast()
4743   else if (RetVT == MVT::i64 && SrcVT == MVT::f64)  in selectBitCast()