Lines Matching refs:SrcVT

183   unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
184 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
187 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
189 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
190 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
192 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
991 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); in selectFPExt() local
994 if (SrcVT != MVT::f32 || DestVT != MVT::f64) in selectFPExt()
1070 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); in selectFPTrunc() local
1073 if (SrcVT != MVT::f64 || DestVT != MVT::f32) in selectFPTrunc()
1093 MVT DstVT, SrcVT; in selectFPToInt() local
1106 if (!isTypeLegal(SrcTy, SrcVT)) in selectFPToInt()
1109 if (SrcVT != MVT::f32 && SrcVT != MVT::f64) in selectFPToInt()
1120 unsigned Opc = (SrcVT == MVT::f32) ? Mips::TRUNC_W_S : Mips::TRUNC_W_D32; in selectFPToInt()
1204 MVT SrcVT = ArgVT; in processCallArgs() local
1205 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false); in processCallArgs()
1212 MVT SrcVT = ArgVT; in processCallArgs() local
1213 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true); in processCallArgs()
1776 EVT SrcVT, DestVT; in selectTrunc() local
1777 SrcVT = TLI.getValueType(DL, Op->getType(), true); in selectTrunc()
1780 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8) in selectTrunc()
1813 MVT SrcVT = SrcEVT.getSimpleVT(); in selectIntExt() local
1817 if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt)) in selectIntExt()
1823 bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntSExt32r1() argument
1826 switch (SrcVT.SimpleTy) { in emitIntSExt32r1()
1842 bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntSExt32r2() argument
1844 switch (SrcVT.SimpleTy) { in emitIntSExt32r2()
1857 bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntSExt() argument
1862 return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg); in emitIntSExt()
1863 return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg); in emitIntSExt()
1866 bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntZExt() argument
1870 switch (SrcVT.SimpleTy) { in emitIntZExt()
1888 bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntExt() argument
1895 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && (SrcVT != MVT::i16))) in emitIntExt()
1898 return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg); in emitIntExt()
1899 return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg); in emitIntExt()
1902 unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntExt() argument
1905 bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt); in emitIntExt()