| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 1676 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, in getCastInstrCost()
1677 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, in getCastInstrCost()
1680 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, in getCastInstrCost()
1681 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v2i1, 1 }, in getCastInstrCost()
1682 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, in getCastInstrCost()
1789 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, in getCastInstrCost()
1790 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, in getCastInstrCost()
1791 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, in getCastInstrCost()
1829 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8 }, in getCastInstrCost()
1830 { ISD::TRUNCATE, MVT::v64i8, MVT::v32i16, 8 }, in getCastInstrCost()
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| H A D | X86ISelLowering.cpp | 299 for (MVT VT : { MVT::i8, MVT::i16, MVT::i32 }) { in X86TargetLowering()
335 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) { in X86TargetLowering()
346 for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128, in X86TargetLowering()
347 MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) { in X86TargetLowering()
393 for (auto VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) { in X86TargetLowering()
415 for (MVT VT : {MVT::f32, MVT::f64, MVT::f80, MVT::f128}) { in X86TargetLowering()
457 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) { in X86TargetLowering()
1227 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) { in X86TargetLowering()
1529 for (MVT VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64, in X86TargetLowering()
1562 for (MVT VT : { MVT::f16, MVT::v2f16, MVT::v4f16, MVT::v8f16 }) { in X86TargetLowering()
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| /llvm-project-15.0.7/llvm/include/llvm/Support/ |
| H A D | MachineValueType.h | 31 class MVT {
393 return (SimpleTy == MVT::v2i8 || SimpleTy == MVT::v1i16 || in is16BitVector()
394 SimpleTy == MVT::v16i1 || SimpleTy == MVT::v1f16); in is16BitVector()
420 SimpleTy == MVT::v4f32 || SimpleTy == MVT::v2f64); in is128BitVector()
426 SimpleTy == MVT::v8f32 || SimpleTy == MVT::v4f64 || in is256BitVector()
461 return (SimpleTy == MVT::Any || SimpleTy == MVT::iAny || in isOverloaded()
462 SimpleTy == MVT::fAny || SimpleTy == MVT::vAny || in isOverloaded()
471 MVT IntTy = MVT::getIntegerVT(EltTy.getSizeInBits()); in changeVectorElementTypeToInteger()
480 MVT changeVectorElementType(MVT EltVT) const { in changeVectorElementType()
1216 static MVT getVectorVT(MVT VT, unsigned NumElements) { in getVectorVT()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | ValueTypes.cpp | 541 MVT MVT::getVT(Type *Ty, bool HandleUnknown){ in getVT()
544 if (HandleUnknown) return MVT(MVT::Other); in getVT()
550 case Type::HalfTyID: return MVT(MVT::f16); in getVT()
551 case Type::BFloatTyID: return MVT(MVT::bf16); in getVT()
552 case Type::FloatTyID: return MVT(MVT::f32); in getVT()
553 case Type::DoubleTyID: return MVT(MVT::f64); in getVT()
554 case Type::X86_FP80TyID: return MVT(MVT::f80); in getVT()
555 case Type::X86_MMXTyID: return MVT(MVT::x86mmx); in getVT()
556 case Type::X86_AMXTyID: return MVT(MVT::x86amx); in getVT()
557 case Type::FP128TyID: return MVT(MVT::f128); in getVT()
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| H A D | TargetLoweringBase.cpp | 751 for (MVT VT : {MVT::i2, MVT::i4}) in initActions()
754 for (MVT AVT : MVT::all_valuetypes()) { in initActions()
755 for (MVT VT : {MVT::i2, MVT::i4, MVT::v128i2, MVT::v64i4}) { in initActions()
763 for (MVT VT : {MVT::i2, MVT::i4}) { in initActions()
771 for (MVT VT : MVT::fp_valuetypes()) { in initActions()
780 for (MVT VT : MVT::all_valuetypes()) { in initActions()
883 {MVT::f16, MVT::f32, MVT::f64, MVT::f80, MVT::f128}, in initActions()
891 {MVT::f32, MVT::f64, MVT::f128}, Expand); in initActions()
1350 TransformToType[MVT::f64] = MVT::i64; in computeRegisterProperties()
1359 TransformToType[MVT::f32] = MVT::i32; in computeRegisterProperties()
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| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | CodeGenTarget.cpp | 48 case MVT::Other: return "UNKNOWN"; in getName()
59 case MVT::i1: return "MVT::i1"; in getEnumName()
60 case MVT::i2: return "MVT::i2"; in getEnumName()
61 case MVT::i4: return "MVT::i4"; in getEnumName()
748 MVT::SimpleValueType VT; in CodeGenIntrinsic()
759 VT == MVT::iAny || VT == MVT::vAny) && in CodeGenIntrinsic()
766 if (VT == MVT::isVoid) in CodeGenIntrinsic()
779 MVT::SimpleValueType VT; in CodeGenIntrinsic()
795 VT == MVT::iAny || VT == MVT::vAny) && in CodeGenIntrinsic()
922 MVT ParamType = MVT(IS.ParamVTs[ParamIdx]); in isParamAPointer()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMTargetTransformInfo.cpp | 603 { ISD::ADD, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
604 { ISD::ADD, MVT::v8i16, MVT::v8i8, 0 }, in getCastInstrCost()
606 { ISD::SUB, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
607 { ISD::SUB, MVT::v8i16, MVT::v8i8, 0 }, in getCastInstrCost()
609 { ISD::MUL, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
610 { ISD::MUL, MVT::v8i16, MVT::v8i8, 0 }, in getCastInstrCost()
612 { ISD::SHL, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
613 { ISD::SHL, MVT::v8i16, MVT::v8i8, 0 }, in getCastInstrCost()
737 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 }, in getCastInstrCost()
738 { ISD::FP_TO_UINT, MVT::i1, MVT::f32, 2 }, in getCastInstrCost()
[all …]
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| H A D | ARMCallingConv.h | 20 bool CC_ARM_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
23 bool CC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT, MVT LocVT,
26 bool CC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT,
29 bool CC_ARM_APCS_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
32 bool FastCC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT,
35 bool CC_ARM_Win32_CFGuard_Check(unsigned ValNo, MVT ValVT, MVT LocVT,
38 bool RetCC_ARM_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
41 bool RetCC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT, MVT LocVT,
44 bool RetCC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT,
47 bool RetFastCC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT,
|
| H A D | ARMCallingConv.cpp | 21 static bool f64AssignAPCS(unsigned ValNo, MVT ValVT, MVT LocVT, in f64AssignAPCS()
62 static bool f64AssignAAPCS(unsigned ValNo, MVT ValVT, MVT LocVT, in f64AssignAAPCS()
114 static bool f64RetAssign(unsigned ValNo, MVT ValVT, MVT LocVT, in f64RetAssign()
199 case MVT::i32: { in CC_ARM_AAPCS_Custom_Aggregate()
211 case MVT::f16: in CC_ARM_AAPCS_Custom_Aggregate()
212 case MVT::bf16: in CC_ARM_AAPCS_Custom_Aggregate()
213 case MVT::f32: in CC_ARM_AAPCS_Custom_Aggregate()
216 case MVT::v4f16: in CC_ARM_AAPCS_Custom_Aggregate()
218 case MVT::f64: in CC_ARM_AAPCS_Custom_Aggregate()
221 case MVT::v8f16: in CC_ARM_AAPCS_Custom_Aggregate()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetTransformInfo.cpp | 310 static const auto ValidMinMaxTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16, in getIntrinsicInstrCost()
311 MVT::v8i16, MVT::v2i32, MVT::v4i32}; in getIntrinsicInstrCost()
324 static const auto ValidSatTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16, in getIntrinsicInstrCost()
325 MVT::v8i16, MVT::v2i32, MVT::v4i32, in getIntrinsicInstrCost()
337 static const auto ValidAbsTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16, in getIntrinsicInstrCost()
338 MVT::v8i16, MVT::v2i32, MVT::v4i32, in getIntrinsicInstrCost()
1605 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, in getCastInstrCost()
1606 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, in getCastInstrCost()
2146 MVT::v8i8, MVT::v16i8, MVT::v4i16, MVT::v8i16, MVT::v2i32, in getCmpSelInstrCost()
2147 MVT::v4i32, MVT::v2i64, MVT::v2f32, MVT::v4f32, MVT::v2f64}; in getCmpSelInstrCost()
[all …]
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| H A D | AArch64ISelDAGToDAG.cpp | 2568 if (VT != MVT::i32 && VT != MVT::i64) in tryBitfieldInsertOpFromOrAndImm()
2657 if (VT != MVT::i32 && VT != MVT::i64) in tryBitfieldInsertOpFromOr()
2847 if (VT != MVT::i32 && VT != MVT::i64) in tryBitfieldInsertInZeroOp()
3201 MVT RegTy = MemTy == MVT::i64 ? MVT::i64 : MVT::i32; in SelectCMP_SWAP()
4725 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 || in Select()
4729 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 || in Select()
4733 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 || in Select()
4744 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 || in Select()
4748 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 || in Select()
4752 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 || in Select()
[all …]
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| H A D | AArch64CallingConvention.h | 19 bool CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
22 bool CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
25 bool CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
28 bool CC_AArch64_DarwinPCS_ILP32_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
31 bool CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
34 bool CC_AArch64_Win64_CFGuard_Check(unsigned ValNo, MVT ValVT, MVT LocVT,
37 bool CC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT, MVT LocVT,
40 bool CC_AArch64_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
43 bool RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
46 bool RetCC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT, MVT LocVT,
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| H A D | AArch64FastISel.cpp | 393 if (VT != MVT::f32 && VT != MVT::f64) in materializeFP()
541 if (VT != MVT::f32 && VT != MVT::f64) in fastMaterializeFloatZero()
991 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16) in isTypeSupported()
2854 if (SrcVT == MVT::i16 || SrcVT == MVT::i8 || SrcVT == MVT::i1) { in selectIntToFP()
3178 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)) in fastLowerCall()
3835 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16) in selectRet()
3882 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 && in selectTrunc()
3885 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8 && in selectTrunc()
4027 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 || in emitLSL_ri()
4130 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 || in emitLSR_ri()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 22 static const MVT LegalV64[] = { MVT::v64i8, MVT::v32i16, MVT::v16i32 };
23 static const MVT LegalW64[] = { MVT::v128i8, MVT::v64i16, MVT::v32i32 };
24 static const MVT LegalV128[] = { MVT::v128i8, MVT::v64i16, MVT::v32i32 };
25 static const MVT LegalW128[] = { MVT::v256i8, MVT::v128i16, MVT::v64i32 };
70 MVT ByteV = Use64b ? MVT::v64i8 : MVT::v128i8; in initializeHVXLowering()
71 MVT ByteW = Use64b ? MVT::v128i8 : MVT::v256i8; in initializeHVXLowering()
356 for (MVT T: {MVT::v32i8, MVT::v32i16, MVT::v16i8, MVT::v16i16, MVT::v16i32}) in initializeHVXLowering()
359 for (MVT T: {MVT::v64i8, MVT::v64i16, MVT::v32i8, MVT::v32i16, MVT::v32i32}) in initializeHVXLowering()
382 MVT BoolTy = MVT::getVectorVT(MVT::i1, N); in initializeHVXLowering()
825 MVT ByteTy = MVT::getVectorVT(MVT::i8, HwLen); in createHvxPrefixPred()
[all …]
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| H A D | HexagonISelLowering.cpp | 637 bool IsLegalType = VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 || in getPostIndexedAddressParts()
1666 MVT VT32 = MVT::getVectorVT(MVT::i32, VT.getSizeInBits()/32); in HexagonTargetLowering()
1689 for (MVT NativeVT : {MVT::v8i1, MVT::v4i1, MVT::v2i1, MVT::v4i8, in HexagonTargetLowering()
1690 MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v2i32}) { in HexagonTargetLowering()
1709 for (MVT VT : {MVT::v8i8, MVT::v4i16, MVT::v2i32}) { in HexagonTargetLowering()
1720 for (MVT VT : {MVT::i16, MVT::i32, MVT::v4i8, MVT::i64, MVT::v8i8, in HexagonTargetLowering()
1721 MVT::v2i16, MVT::v4i16, MVT::v2i32}) { in HexagonTargetLowering()
1727 for (MVT VT : {MVT::v2i1, MVT::v4i1, MVT::v8i1}) { in HexagonTargetLowering()
1732 for (MVT VT : {MVT::v2i16, MVT::v4i8, MVT::v8i8, MVT::v2i32, MVT::v4i16, in HexagonTargetLowering()
1788 for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64, MVT::f32, MVT::f64, in HexagonTargetLowering()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 149 {MVT::v2i8, MVT::v4i8, MVT::v2i16, MVT::v3i16, MVT::v4i16}) in AMDGPUTargetLowering()
313 {MVT::v3i32, MVT::v3f32, MVT::v4i32, MVT::v4f32, in AMDGPUTargetLowering()
319 {MVT::v2f16, MVT::v2i16, MVT::v4f16, MVT::v4i16, MVT::v2f32, in AMDGPUTargetLowering()
320 MVT::v2i32, MVT::v3f32, MVT::v3i32, MVT::v4f32, MVT::v4i32, in AMDGPUTargetLowering()
321 MVT::v5f32, MVT::v5i32, MVT::v6f32, MVT::v6i32, MVT::v7f32, in AMDGPUTargetLowering()
322 MVT::v7i32, MVT::v8f32, MVT::v8i32, MVT::v16f16, MVT::v16i16, in AMDGPUTargetLowering()
323 MVT::v16f32, MVT::v16i32, MVT::v32f32, MVT::v32i32, MVT::v2f64, in AMDGPUTargetLowering()
324 MVT::v2i64, MVT::v3f64, MVT::v3i64, MVT::v4f64, MVT::v4i64, in AMDGPUTargetLowering()
325 MVT::v8f64, MVT::v8i64, MVT::v16f64, MVT::v16i64}, in AMDGPUTargetLowering()
372 MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32, MVT::v6i32, MVT::v7i32}; in AMDGPUTargetLowering()
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| H A D | R600ISelLowering.cpp | 45 setOperationAction(ISD::LOAD, {MVT::i32, MVT::v2i32, MVT::v4i32}, Custom); in R600TargetLowering()
50 for (MVT VT : MVT::integer_valuetypes()) { in R600TargetLowering()
63 setOperationAction(ISD::STORE, {MVT::i8, MVT::i32, MVT::v2i32, MVT::v4i32}, in R600TargetLowering()
66 setTruncStoreAction(MVT::i32, MVT::i8, Custom); in R600TargetLowering()
67 setTruncStoreAction(MVT::i32, MVT::i16, Custom); in R600TargetLowering()
75 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom); in R600TargetLowering()
76 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom); in R600TargetLowering()
112 setOperationAction(ISD::SELECT, {MVT::i32, MVT::f32, MVT::v2i32, MVT::v4i32}, in R600TargetLowering()
145 {MVT::v2i32, MVT::v2f32, MVT::v4i32, MVT::v4f32}, Custom); in R600TargetLowering()
148 {MVT::v2i32, MVT::v2f32, MVT::v4i32, MVT::v4f32}, Custom); in R600TargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kExpandPseudo.cpp | 85 return TII->ExpandMOVX_RR(MIB, MVT::i16, MVT::i8); in ExpandMI()
87 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i8); in ExpandMI()
89 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i16); in ExpandMI()
92 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i16, MVT::i8); in ExpandMI()
94 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i8); in ExpandMI()
96 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i16); in ExpandMI()
99 return TII->ExpandMOVSZX_RR(MIB, false, MVT::i16, MVT::i8); in ExpandMI()
101 return TII->ExpandMOVSZX_RR(MIB, false, MVT::i32, MVT::i8); in ExpandMI()
103 return TII->ExpandMOVSZX_RR(MIB, false, MVT::i32, MVT::i16); in ExpandMI()
107 MVT::i8); in ExpandMI()
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| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 107 assert((LocVT == MVT::f32 || LocVT == MVT::f128 in Analyze_CC_Sparc64_Full()
1564 for (MVT VT : MVT::fp_valuetypes()) { in SparcTargetLowering()
1571 for (MVT VT : MVT::integer_valuetypes()) in SparcTargetLowering()
2446 assert(VT == MVT::i32 || VT == MVT::i64); in LowerFP_TO_SINT()
2475 assert(OpVT == MVT::i32 || (OpVT == MVT::i64)); in LowerSINT_TO_FP()
2477 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64; in LowerSINT_TO_FP()
2510 assert(VT == MVT::i32 || VT == MVT::i64); in LowerFP_TO_UINT()
2524 assert(OpVT == MVT::i32 || OpVT == MVT::i64); in LowerUINT_TO_FP()
3396 if (VT == MVT::f32 || VT == MVT::i32) in getRegForInlineAsmConstraint()
3398 else if (VT == MVT::f64 || VT == MVT::i64) in getRegForInlineAsmConstraint()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFastISel.cpp | 124 MVT::SimpleValueType getLegalType(MVT::SimpleValueType VT) { in getLegalType()
126 case MVT::i1: in getLegalType()
127 case MVT::i8: in getLegalType()
128 case MVT::i16: in getLegalType()
130 case MVT::i32: in getLegalType()
446 case MVT::i1: in zeroExtendToI32()
453 case MVT::i8: in zeroExtendToI32()
482 case MVT::i1: in signExtendToI32()
483 case MVT::i8: in signExtendToI32()
932 case MVT::i1: in selectSelect()
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| H A D | WebAssemblyISelLowering.cpp | 81 for (auto T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64}) { in WebAssemblyTargetLowering()
86 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, in WebAssemblyTargetLowering()
115 for (auto T : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) { in WebAssemblyTargetLowering()
149 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) in WebAssemblyTargetLowering()
184 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) in WebAssemblyTargetLowering()
188 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, in WebAssemblyTargetLowering()
193 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, in WebAssemblyTargetLowering()
204 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, in WebAssemblyTargetLowering()
212 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, in WebAssemblyTargetLowering()
280 for (auto T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64}) in WebAssemblyTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/Utils/ |
| H A D | WebAssemblyTypeUtilities.cpp | 127 case MVT::i32: in toValType()
129 case MVT::i64: in toValType()
131 case MVT::f32: in toValType()
133 case MVT::f64: in toValType()
135 case MVT::v16i8: in toValType()
136 case MVT::v8i16: in toValType()
137 case MVT::v4i32: in toValType()
138 case MVT::v2i64: in toValType()
139 case MVT::v4f32: in toValType()
140 case MVT::v2f64: in toValType()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 289 if (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) { in isLoadTypeLegal()
841 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 || in PPCEmitCmp()
1514 if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) in finishCall()
1585 if (RetVT != MVT::isVoid && RetVT != MVT::i8 && RetVT != MVT::i16 && in fastLowerCall()
1586 RetVT != MVT::i32 && RetVT != MVT::i64 && RetVT != MVT::f32 && in fastLowerCall()
1812 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 && SrcVT != MVT::i32) in PPCEmitIntExt()
1882 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16) in SelectTrunc()
1885 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8) in SelectTrunc()
2218 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && in PPCMaterializeInt()
2352 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8) in tryToFoldLoadIntoMI()
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| H A D | PPCISelLowering.cpp | 234 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 }; in PPCTargetLowering()
754 for (MVT VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) { in PPCTargetLowering()
914 for (auto VT : {MVT::v4i32, MVT::v8i16, MVT::v16i8}) in PPCTargetLowering()
1260 for (MVT VT : {MVT::f32, MVT::f64}) { in PPCTargetLowering()
5437 const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in prepareDescriptorIndirectCall()
5489 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32; in buildCallOperands()
6590 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32; in CC_AIX()
7509 const MVT PtrVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in LowerCall_AIX()
8453 MVT IntermediateVT = FourEltRes ? MVT::v4i32 : MVT::v2i64; in LowerINT_TO_FPVector()
8943 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 in getCanonicalConstSplat()
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| H A D | PPCCallingConv.h | 22 bool RetCC_PPC(unsigned ValNo, MVT ValVT, MVT LocVT,
25 bool RetCC_PPC64_ELF_FIS(unsigned ValNo, MVT ValVT, MVT LocVT,
28 bool RetCC_PPC_Cold(unsigned ValNo, MVT ValVT, MVT LocVT,
31 bool CC_PPC32_SVR4(unsigned ValNo, MVT ValVT, MVT LocVT,
34 bool CC_PPC64_ELF_FIS(unsigned ValNo, MVT ValVT, MVT LocVT,
37 bool CC_PPC32_SVR4_ByVal(unsigned ValNo, MVT ValVT, MVT LocVT,
40 bool CC_PPC32_SVR4_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
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