Lines Matching refs:MVT
32 addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass); in R600TargetLowering()
33 addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass); in R600TargetLowering()
34 addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass); in R600TargetLowering()
35 addRegisterClass(MVT::v2i32, &R600::R600_Reg64RegClass); in R600TargetLowering()
36 addRegisterClass(MVT::v4f32, &R600::R600_Reg128RegClass); in R600TargetLowering()
37 addRegisterClass(MVT::v4i32, &R600::R600_Reg128RegClass); in R600TargetLowering()
45 setOperationAction(ISD::LOAD, {MVT::i32, MVT::v2i32, MVT::v4i32}, Custom); in R600TargetLowering()
50 for (MVT VT : MVT::integer_valuetypes()) { in R600TargetLowering()
51 setLoadExtAction(Op, VT, MVT::i1, Promote); in R600TargetLowering()
52 setLoadExtAction(Op, VT, MVT::i8, Custom); in R600TargetLowering()
53 setLoadExtAction(Op, VT, MVT::i16, Custom); in R600TargetLowering()
57 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::v2i32, in R600TargetLowering()
58 MVT::v2i1, Expand); in R600TargetLowering()
60 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::v4i32, in R600TargetLowering()
61 MVT::v4i1, Expand); in R600TargetLowering()
63 setOperationAction(ISD::STORE, {MVT::i8, MVT::i32, MVT::v2i32, MVT::v4i32}, in R600TargetLowering()
66 setTruncStoreAction(MVT::i32, MVT::i8, Custom); in R600TargetLowering()
67 setTruncStoreAction(MVT::i32, MVT::i16, Custom); in R600TargetLowering()
70 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom); in R600TargetLowering()
71 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Custom); in R600TargetLowering()
72 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Custom); in R600TargetLowering()
73 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Custom); in R600TargetLowering()
74 setTruncStoreAction(MVT::v32i32, MVT::v32i16, Custom); in R600TargetLowering()
75 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom); in R600TargetLowering()
76 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom); in R600TargetLowering()
77 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Custom); in R600TargetLowering()
78 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Custom); in R600TargetLowering()
79 setTruncStoreAction(MVT::v32i32, MVT::v32i8, Custom); in R600TargetLowering()
82 setTruncStoreAction(MVT::v2i32, MVT::v2i1, Expand); in R600TargetLowering()
83 setTruncStoreAction(MVT::v4i32, MVT::v4i1, Expand); in R600TargetLowering()
89 MVT::f32, Expand); in R600TargetLowering()
92 MVT::i32, Expand); in R600TargetLowering()
94 setOperationAction({ISD::FCOS, ISD::FSIN}, MVT::f32, Custom); in R600TargetLowering()
96 setOperationAction(ISD::SETCC, {MVT::v4i32, MVT::v2i32}, Expand); in R600TargetLowering()
98 setOperationAction(ISD::BR_CC, {MVT::i32, MVT::f32}, Expand); in R600TargetLowering()
99 setOperationAction(ISD::BRCOND, MVT::Other, Custom); in R600TargetLowering()
101 setOperationAction(ISD::FSUB, MVT::f32, Expand); in R600TargetLowering()
104 MVT::f64, Custom); in R600TargetLowering()
106 setOperationAction(ISD::SELECT_CC, {MVT::f32, MVT::i32}, Custom); in R600TargetLowering()
108 setOperationAction(ISD::SETCC, {MVT::i32, MVT::f32}, Expand); in R600TargetLowering()
109 setOperationAction({ISD::FP_TO_UINT, ISD::FP_TO_SINT}, {MVT::i1, MVT::i64}, in R600TargetLowering()
112 setOperationAction(ISD::SELECT, {MVT::i32, MVT::f32, MVT::v2i32, MVT::v4i32}, in R600TargetLowering()
118 setOperationAction(ISD::UADDO, MVT::i32, Custom); in R600TargetLowering()
121 setOperationAction(ISD::USUBO, MVT::i32, Custom); in R600TargetLowering()
125 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in R600TargetLowering()
127 setOperationAction(ISD::SIGN_EXTEND_INREG, {MVT::v2i1, MVT::v4i1}, Expand); in R600TargetLowering()
130 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in R600TargetLowering()
131 setOperationAction(ISD::SIGN_EXTEND_INREG, {MVT::v2i8, MVT::v4i8}, Expand); in R600TargetLowering()
134 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in R600TargetLowering()
135 setOperationAction(ISD::SIGN_EXTEND_INREG, {MVT::v2i16, MVT::v4i16}, Expand); in R600TargetLowering()
137 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); in R600TargetLowering()
138 setOperationAction(ISD::SIGN_EXTEND_INREG, {MVT::v2i32, MVT::v4i32}, Expand); in R600TargetLowering()
140 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand); in R600TargetLowering()
142 setOperationAction(ISD::FrameIndex, MVT::i32, Custom); in R600TargetLowering()
145 {MVT::v2i32, MVT::v2f32, MVT::v4i32, MVT::v4f32}, Custom); in R600TargetLowering()
148 {MVT::v2i32, MVT::v2f32, MVT::v4i32, MVT::v4f32}, Custom); in R600TargetLowering()
152 setOperationAction({ISD::SHL_PARTS, ISD::SRL_PARTS, ISD::SRA_PARTS}, MVT::i32, in R600TargetLowering()
156 setOperationAction(ISD::FMA, {MVT::f32, MVT::f64}, Expand); in R600TargetLowering()
159 setOperationAction(ISD::FMAD, MVT::f32, Legal); in R600TargetLowering()
163 setOperationAction(ISD::FCOPYSIGN, {MVT::f32, MVT::f64}, Expand); in R600TargetLowering()
166 setOperationAction(ISD::CTPOP, MVT::i32, Expand); in R600TargetLowering()
169 setOperationAction(ISD::CTPOP, MVT::i64, Expand); in R600TargetLowering()
172 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Custom); in R600TargetLowering()
175 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Custom); in R600TargetLowering()
182 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); in R600TargetLowering()
184 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 }; in R600TargetLowering()
185 for (MVT VT : ScalarIntVTs) in R600TargetLowering()
191 setOperationAction({ISD::ATOMIC_LOAD, ISD::ATOMIC_STORE}, MVT::i32, Expand); in R600TargetLowering()
194 setOperationAction({ISD::INTRINSIC_VOID, ISD::INTRINSIC_WO_CHAIN}, MVT::Other, in R600TargetLowering()
433 DAG.getConstant(0, DL, MVT::i32), // SWZ_X in LowerOperation()
434 DAG.getConstant(1, DL, MVT::i32), // SWZ_Y in LowerOperation()
435 DAG.getConstant(2, DL, MVT::i32), // SWZ_Z in LowerOperation()
436 DAG.getConstant(3, DL, MVT::i32) // SWZ_W in LowerOperation()
468 DAG.getConstant(TextureOp, DL, MVT::i32), in LowerOperation()
470 DAG.getConstant(0, DL, MVT::i32), in LowerOperation()
471 DAG.getConstant(1, DL, MVT::i32), in LowerOperation()
472 DAG.getConstant(2, DL, MVT::i32), in LowerOperation()
473 DAG.getConstant(3, DL, MVT::i32), in LowerOperation()
477 DAG.getConstant(0, DL, MVT::i32), in LowerOperation()
478 DAG.getConstant(1, DL, MVT::i32), in LowerOperation()
479 DAG.getConstant(2, DL, MVT::i32), in LowerOperation()
480 DAG.getConstant(3, DL, MVT::i32), in LowerOperation()
488 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs); in LowerOperation()
492 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
493 DAG.getConstant(0, DL, MVT::i32)), in LowerOperation()
494 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
495 DAG.getConstant(0, DL, MVT::i32)), in LowerOperation()
496 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
497 DAG.getConstant(1, DL, MVT::i32)), in LowerOperation()
498 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
499 DAG.getConstant(1, DL, MVT::i32)), in LowerOperation()
500 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
501 DAG.getConstant(2, DL, MVT::i32)), in LowerOperation()
502 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
503 DAG.getConstant(2, DL, MVT::i32)), in LowerOperation()
504 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
505 DAG.getConstant(3, DL, MVT::i32)), in LowerOperation()
506 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
507 DAG.getConstant(3, DL, MVT::i32)) in LowerOperation()
509 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args); in LowerOperation()
513 MVT PtrVT = getPointerTy(DAG.getDataLayout(), AMDGPUAS::PARAM_I_ADDRESS); in LowerOperation()
585 if (N->getValueType(0) == MVT::i1) { in ReplaceNodeResults()
594 if (N->getValueType(0) == MVT::i1) { in ReplaceNodeResults()
675 MVT ConstPtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS); in LowerGlobalAddress()
692 DAG.getConstantFP(0.15915494309, DL, MVT::f32)), in LowerTrig()
693 DAG.getConstantFP(0.5, DL, MVT::f32))); in LowerTrig()
707 DAG.getConstantFP(-0.5, DL, MVT::f32))); in LowerTrig()
712 DAG.getConstantFP(numbers::pif, DL, MVT::f32)); in LowerTrig()
733 DAG.getValueType(MVT::i1)); in LowerUADDSUBO()
745 MVT::i1, in lowerFP_TO_UINT()
746 Op, DAG.getConstantFP(1.0f, DL, MVT::f32), in lowerFP_TO_UINT()
755 MVT::i1, in lowerFP_TO_SINT()
756 Op, DAG.getConstantFP(-1.0f, DL, MVT::f32), in lowerFP_TO_SINT()
771 DAG.getConstant(ByteOffset, DL, MVT::i32), // PTR in LowerImplicitParameter()
810 if (VT == MVT::f32) { in LowerSELECT_CC()
849 (CompareVT == VT || VT == MVT::i32)) { in LowerSELECT_CC()
919 if (CompareVT == MVT::f32) { in LowerSELECT_CC()
922 } else if (CompareVT == MVT::i32) { in LowerSELECT_CC()
964 DAG.getConstant(SRLPad, DL, MVT::i32)); in stackPtrToRegIndex()
1001 || Store->getValue().getValueType() == MVT::i8); in lowerPrivateTruncStore()
1005 if (Store->getMemoryVT() == MVT::i8) { in lowerPrivateTruncStore()
1007 Mask = DAG.getConstant(0xff, DL, MVT::i32); in lowerPrivateTruncStore()
1008 } else if (Store->getMemoryVT() == MVT::i16) { in lowerPrivateTruncStore()
1010 Mask = DAG.getConstant(0xffff, DL, MVT::i32); in lowerPrivateTruncStore()
1025 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset); in lowerPrivateTruncStore()
1030 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateTruncStore()
1031 DAG.getConstant(0xfffffffc, DL, MVT::i32)); in lowerPrivateTruncStore()
1036 SDValue Dst = DAG.getLoad(MVT::i32, DL, Chain, Ptr, PtrInfo); in lowerPrivateTruncStore()
1041 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateTruncStore()
1042 DAG.getConstant(0x3, DL, MVT::i32)); in lowerPrivateTruncStore()
1045 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in lowerPrivateTruncStore()
1046 DAG.getConstant(3, DL, MVT::i32)); in lowerPrivateTruncStore()
1050 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32, in lowerPrivateTruncStore()
1057 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32, in lowerPrivateTruncStore()
1061 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, Mask, ShiftAmt); in lowerPrivateTruncStore()
1065 DstMask = DAG.getNOT(DL, DstMask, MVT::i32); in lowerPrivateTruncStore()
1068 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask); in lowerPrivateTruncStore()
1071 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue); in lowerPrivateTruncStore()
1080 Chain = DAG.getNode(AMDGPUISD::DUMMY_CHAIN, DL, MVT::Other, NewStore); in lowerPrivateTruncStore()
1108 SDValue NewChain = DAG.getNode(AMDGPUISD::DUMMY_CHAIN, DL, MVT::Other, Chain); in LowerSTORE()
1135 assert(VT.bitsLE(MVT::i32)); in LowerSTORE()
1137 if (MemVT == MVT::i8) { in LowerSTORE()
1138 MaskConstant = DAG.getConstant(0xFF, DL, MVT::i32); in LowerSTORE()
1140 assert(MemVT == MVT::i16); in LowerSTORE()
1142 MaskConstant = DAG.getConstant(0xFFFF, DL, MVT::i32); in LowerSTORE()
1161 DAG.getConstant(0, DL, MVT::i32), in LowerSTORE()
1162 DAG.getConstant(0, DL, MVT::i32), in LowerSTORE()
1165 SDValue Input = DAG.getBuildVector(MVT::v4i32, DL, Src); in LowerSTORE()
1170 } else if (Ptr->getOpcode() != AMDGPUISD::DWORDADDR && VT.bitsGE(MVT::i32)) { in LowerSTORE()
1187 if (MemVT.bitsLT(MVT::i32)) in LowerSTORE()
1256 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset); in lowerPrivateExtLoad()
1261 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateExtLoad()
1262 DAG.getConstant(0xfffffffc, DL, MVT::i32)); in lowerPrivateExtLoad()
1267 SDValue Read = DAG.getLoad(MVT::i32, DL, Chain, Ptr, PtrInfo); in lowerPrivateExtLoad()
1270 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, in lowerPrivateExtLoad()
1271 LoadPtr, DAG.getConstant(0x3, DL, MVT::i32)); in lowerPrivateExtLoad()
1274 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in lowerPrivateExtLoad()
1275 DAG.getConstant(3, DL, MVT::i32)); in lowerPrivateExtLoad()
1278 SDValue Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Read, ShiftAmt); in lowerPrivateExtLoad()
1285 Ret = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode); in lowerPrivateExtLoad()
1305 ExtType != ISD::NON_EXTLOAD && MemVT.bitsLT(MVT::i32)) { in LowerLOAD()
1334 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32, in LowerLOAD()
1335 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, in LowerLOAD()
1336 DAG.getConstant(4, DL, MVT::i32)), in LowerLOAD()
1338 AMDGPUAS::CONSTANT_BUFFER_0, DL, MVT::i32) in LowerLOAD()
1343 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in LowerLOAD()
1344 DAG.getConstant(0, DL, MVT::i32)); in LowerLOAD()
1362 assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8)); in LowerLOAD()
1379 assert(VT == MVT::i32); in LowerLOAD()
1380 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(2, DL, MVT::i32)); in LowerLOAD()
1381 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, MVT::i32, Ptr); in LowerLOAD()
1382 return DAG.getLoad(MVT::i32, DL, Chain, Ptr, LoadNode->getMemOperand()); in LowerLOAD()
1495 DAG.getConstant(PartOffset, DL, MVT::i32), DAG.getUNDEF(MVT::i32), in LowerFormalArguments()
1509 return MVT::i32; in getSetCCResultType()
1528 if (!VT.isSimple() || VT == MVT::Other) in allowsMisalignedMemoryAccesses()
1531 if (VT.bitsLT(MVT::i32)) in allowsMisalignedMemoryAccesses()
1538 return VT.bitsGT(MVT::i32) && Alignment >= Align(4); in allowsMisalignedMemoryAccesses()
1563 NewBldVec[i] = DAG.getUNDEF(MVT::f32); in CompactSwizzlableVector()
1566 NewBldVec[i] = DAG.getUNDEF(MVT::f32); in CompactSwizzlableVector()
1636 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32); in OptimizeSwizzle()
1644 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32); in OptimizeSwizzle()
1659 if (LoadNode->getMemoryVT().getScalarType() != MVT::i32 || !ISD::isNON_EXTLoad(LoadNode)) in constBufferLoad()
1675 DAG.getConstant(4 * i + ConstantBlock * 16, DL, MVT::i32)); in constBufferLoad()
1676 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr); in constBufferLoad()
1678 EVT NewVT = MVT::v4i32; in constBufferLoad()
1686 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in constBufferLoad()
1687 DAG.getConstant(0, DL, MVT::i32)); in constBufferLoad()
1709 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) { in PerformDAGCombine()
1728 SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS in PerformDAGCombine()
1729 SelectCC.getOperand(2).getValueType() != MVT::f32 || // True in PerformDAGCombine()
1738 DAG.getConstant(-1, DL, MVT::i32), // True in PerformDAGCombine()
1739 DAG.getConstant(0, DL, MVT::i32), // False in PerformDAGCombine()
1940 Neg = DAG.getTargetConstant(1, SDLoc(ParentNode), MVT::i32); in FoldOperand()
1946 Abs = DAG.getTargetConstant(1, SDLoc(ParentNode), MVT::i32); in FoldOperand()
1999 Src = DAG.getRegister(R600::ALU_CONST, MVT::f32); in FoldOperand()
2007 Src = DAG.getRegister(R600::ALU_LITERAL_X, MVT::i32); in FoldOperand()
2047 Imm = DAG.getTargetConstant(ImmValue, SDLoc(ParentNode), MVT::i32); in FoldOperand()
2049 Src = DAG.getRegister(ImmReg, MVT::i32); in FoldOperand()