Lines Matching refs:MVT
166 addRegisterClass(MVT::i32, &PPC::GPRCRegClass); in PPCTargetLowering()
169 addRegisterClass(MVT::f32, &PPC::GPRCRegClass); in PPCTargetLowering()
172 addRegisterClass(MVT::f64, &PPC::SPERCRegClass); in PPCTargetLowering()
174 addRegisterClass(MVT::f32, &PPC::F4RCRegClass); in PPCTargetLowering()
175 addRegisterClass(MVT::f64, &PPC::F8RCRegClass); in PPCTargetLowering()
180 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); in PPCTargetLowering()
181 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal); in PPCTargetLowering()
184 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom); in PPCTargetLowering()
187 setOperationAction(ISD::INLINEASM, MVT::Other, Custom); in PPCTargetLowering()
188 setOperationAction(ISD::INLINEASM_BR, MVT::Other, Custom); in PPCTargetLowering()
191 for (MVT VT : MVT::integer_valuetypes()) { in PPCTargetLowering()
192 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in PPCTargetLowering()
193 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); in PPCTargetLowering()
197 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Legal); in PPCTargetLowering()
198 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Legal); in PPCTargetLowering()
199 setTruncStoreAction(MVT::f64, MVT::f16, Legal); in PPCTargetLowering()
200 setTruncStoreAction(MVT::f32, MVT::f16, Legal); in PPCTargetLowering()
203 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand); in PPCTargetLowering()
204 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); in PPCTargetLowering()
205 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); in PPCTargetLowering()
206 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand); in PPCTargetLowering()
207 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); in PPCTargetLowering()
208 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); in PPCTargetLowering()
209 setTruncStoreAction(MVT::f64, MVT::f16, Expand); in PPCTargetLowering()
210 setTruncStoreAction(MVT::f32, MVT::f16, Expand); in PPCTargetLowering()
213 setTruncStoreAction(MVT::f64, MVT::f32, Expand); in PPCTargetLowering()
216 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
217 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
218 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
219 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); in PPCTargetLowering()
220 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); in PPCTargetLowering()
221 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
222 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
223 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
224 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); in PPCTargetLowering()
225 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); in PPCTargetLowering()
227 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal); in PPCTargetLowering()
228 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal); in PPCTargetLowering()
229 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal); in PPCTargetLowering()
230 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal); in PPCTargetLowering()
234 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 }; in PPCTargetLowering()
235 for (MVT VT : ScalarIntVTs) { in PPCTargetLowering()
243 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in PPCTargetLowering()
246 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i1, Promote); in PPCTargetLowering()
247 AddPromotedToType(ISD::STRICT_SINT_TO_FP, MVT::i1, in PPCTargetLowering()
248 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
249 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i1, Promote); in PPCTargetLowering()
250 AddPromotedToType(ISD::STRICT_UINT_TO_FP, MVT::i1, in PPCTargetLowering()
251 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
253 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); in PPCTargetLowering()
254 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1, in PPCTargetLowering()
255 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
256 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote); in PPCTargetLowering()
257 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1, in PPCTargetLowering()
258 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
260 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i1, Promote); in PPCTargetLowering()
261 AddPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::i1, in PPCTargetLowering()
262 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
263 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i1, Promote); in PPCTargetLowering()
264 AddPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::i1, in PPCTargetLowering()
265 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
267 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote); in PPCTargetLowering()
268 AddPromotedToType(ISD::FP_TO_SINT, MVT::i1, in PPCTargetLowering()
269 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
270 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote); in PPCTargetLowering()
271 AddPromotedToType(ISD::FP_TO_UINT, MVT::i1, in PPCTargetLowering()
272 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
274 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i1, Custom); in PPCTargetLowering()
275 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i1, Custom); in PPCTargetLowering()
276 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom); in PPCTargetLowering()
277 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom); in PPCTargetLowering()
281 setOperationAction(ISD::LOAD, MVT::i1, Custom); in PPCTargetLowering()
282 setOperationAction(ISD::STORE, MVT::i1, Custom); in PPCTargetLowering()
286 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom); in PPCTargetLowering()
288 for (MVT VT : MVT::integer_valuetypes()) { in PPCTargetLowering()
289 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in PPCTargetLowering()
290 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in PPCTargetLowering()
291 setTruncStoreAction(VT, MVT::i1, Expand); in PPCTargetLowering()
294 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass); in PPCTargetLowering()
299 setOperationAction(ISD::FP_TO_SINT, MVT::ppcf128, Custom); in PPCTargetLowering()
300 setOperationAction(ISD::FP_TO_UINT, MVT::ppcf128, Custom); in PPCTargetLowering()
301 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::ppcf128, Custom); in PPCTargetLowering()
302 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::ppcf128, Custom); in PPCTargetLowering()
305 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand); in PPCTargetLowering()
306 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand); in PPCTargetLowering()
307 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand); in PPCTargetLowering()
308 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand); in PPCTargetLowering()
309 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand); in PPCTargetLowering()
310 setOperationAction(ISD::FREM, MVT::ppcf128, Expand); in PPCTargetLowering()
320 setOperationAction(ISD::SREM, MVT::i32, Legal); in PPCTargetLowering()
321 setOperationAction(ISD::UREM, MVT::i32, Legal); in PPCTargetLowering()
322 setOperationAction(ISD::SREM, MVT::i64, Legal); in PPCTargetLowering()
323 setOperationAction(ISD::UREM, MVT::i64, Legal); in PPCTargetLowering()
325 setOperationAction(ISD::SREM, MVT::i32, Expand); in PPCTargetLowering()
326 setOperationAction(ISD::UREM, MVT::i32, Expand); in PPCTargetLowering()
327 setOperationAction(ISD::SREM, MVT::i64, Expand); in PPCTargetLowering()
328 setOperationAction(ISD::UREM, MVT::i64, Expand); in PPCTargetLowering()
332 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); in PPCTargetLowering()
333 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); in PPCTargetLowering()
334 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); in PPCTargetLowering()
335 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); in PPCTargetLowering()
336 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in PPCTargetLowering()
337 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in PPCTargetLowering()
338 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in PPCTargetLowering()
339 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in PPCTargetLowering()
343 setOperationAction(ISD::STRICT_FADD, MVT::f32, Legal); in PPCTargetLowering()
344 setOperationAction(ISD::STRICT_FSUB, MVT::f32, Legal); in PPCTargetLowering()
345 setOperationAction(ISD::STRICT_FMUL, MVT::f32, Legal); in PPCTargetLowering()
346 setOperationAction(ISD::STRICT_FDIV, MVT::f32, Legal); in PPCTargetLowering()
347 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal); in PPCTargetLowering()
349 setOperationAction(ISD::STRICT_FADD, MVT::f64, Legal); in PPCTargetLowering()
350 setOperationAction(ISD::STRICT_FSUB, MVT::f64, Legal); in PPCTargetLowering()
351 setOperationAction(ISD::STRICT_FMUL, MVT::f64, Legal); in PPCTargetLowering()
352 setOperationAction(ISD::STRICT_FDIV, MVT::f64, Legal); in PPCTargetLowering()
355 setOperationAction(ISD::STRICT_FMA, MVT::f32, Legal); in PPCTargetLowering()
356 setOperationAction(ISD::STRICT_FMA, MVT::f64, Legal); in PPCTargetLowering()
360 setOperationAction(ISD::STRICT_FRINT, MVT::f32, Legal); in PPCTargetLowering()
361 setOperationAction(ISD::STRICT_FRINT, MVT::f64, Legal); in PPCTargetLowering()
365 setOperationAction(ISD::STRICT_FSQRT, MVT::f32, Legal); in PPCTargetLowering()
366 setOperationAction(ISD::STRICT_FSQRT, MVT::f64, Legal); in PPCTargetLowering()
370 setOperationAction(ISD::STRICT_FFLOOR, MVT::f32, Legal); in PPCTargetLowering()
371 setOperationAction(ISD::STRICT_FCEIL, MVT::f32, Legal); in PPCTargetLowering()
372 setOperationAction(ISD::STRICT_FTRUNC, MVT::f32, Legal); in PPCTargetLowering()
373 setOperationAction(ISD::STRICT_FROUND, MVT::f32, Legal); in PPCTargetLowering()
375 setOperationAction(ISD::STRICT_FFLOOR, MVT::f64, Legal); in PPCTargetLowering()
376 setOperationAction(ISD::STRICT_FCEIL, MVT::f64, Legal); in PPCTargetLowering()
377 setOperationAction(ISD::STRICT_FTRUNC, MVT::f64, Legal); in PPCTargetLowering()
378 setOperationAction(ISD::STRICT_FROUND, MVT::f64, Legal); in PPCTargetLowering()
382 setOperationAction(ISD::FSIN , MVT::f64, Expand); in PPCTargetLowering()
383 setOperationAction(ISD::FCOS , MVT::f64, Expand); in PPCTargetLowering()
384 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in PPCTargetLowering()
385 setOperationAction(ISD::FREM , MVT::f64, Expand); in PPCTargetLowering()
386 setOperationAction(ISD::FPOW , MVT::f64, Expand); in PPCTargetLowering()
387 setOperationAction(ISD::FSIN , MVT::f32, Expand); in PPCTargetLowering()
388 setOperationAction(ISD::FCOS , MVT::f32, Expand); in PPCTargetLowering()
389 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in PPCTargetLowering()
390 setOperationAction(ISD::FREM , MVT::f32, Expand); in PPCTargetLowering()
391 setOperationAction(ISD::FPOW , MVT::f32, Expand); in PPCTargetLowering()
396 setOperationAction(ISD::FSIN , MVT::f64, Custom); in PPCTargetLowering()
397 setOperationAction(ISD::FCOS , MVT::f64, Custom); in PPCTargetLowering()
398 setOperationAction(ISD::FPOW , MVT::f64, Custom); in PPCTargetLowering()
399 setOperationAction(ISD::FLOG, MVT::f64, Custom); in PPCTargetLowering()
400 setOperationAction(ISD::FLOG10, MVT::f64, Custom); in PPCTargetLowering()
401 setOperationAction(ISD::FEXP, MVT::f64, Custom); in PPCTargetLowering()
402 setOperationAction(ISD::FSIN , MVT::f32, Custom); in PPCTargetLowering()
403 setOperationAction(ISD::FCOS , MVT::f32, Custom); in PPCTargetLowering()
404 setOperationAction(ISD::FPOW , MVT::f32, Custom); in PPCTargetLowering()
405 setOperationAction(ISD::FLOG, MVT::f32, Custom); in PPCTargetLowering()
406 setOperationAction(ISD::FLOG10, MVT::f32, Custom); in PPCTargetLowering()
407 setOperationAction(ISD::FEXP, MVT::f32, Custom); in PPCTargetLowering()
411 setOperationAction(ISD::FMA , MVT::f64, Expand); in PPCTargetLowering()
412 setOperationAction(ISD::FMA , MVT::f32, Expand); in PPCTargetLowering()
414 setOperationAction(ISD::FMA , MVT::f64, Legal); in PPCTargetLowering()
415 setOperationAction(ISD::FMA , MVT::f32, Legal); in PPCTargetLowering()
419 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand); in PPCTargetLowering()
421 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); in PPCTargetLowering()
427 setOperationAction(ISD::FSQRT, MVT::f64, Expand); in PPCTargetLowering()
432 setOperationAction(ISD::FSQRT, MVT::f32, Expand); in PPCTargetLowering()
435 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal); in PPCTargetLowering()
436 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal); in PPCTargetLowering()
438 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in PPCTargetLowering()
439 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); in PPCTargetLowering()
443 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); in PPCTargetLowering()
444 setOperationAction(ISD::FCEIL, MVT::f64, Legal); in PPCTargetLowering()
445 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); in PPCTargetLowering()
446 setOperationAction(ISD::FROUND, MVT::f64, Legal); in PPCTargetLowering()
448 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); in PPCTargetLowering()
449 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in PPCTargetLowering()
450 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); in PPCTargetLowering()
451 setOperationAction(ISD::FROUND, MVT::f32, Legal); in PPCTargetLowering()
457 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); in PPCTargetLowering()
459 setOperationAction(ISD::BSWAP, MVT::i64 , Custom); in PPCTargetLowering()
461 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); in PPCTargetLowering()
463 setOperationAction(ISD::CTTZ , MVT::i32 , Legal); in PPCTargetLowering()
464 setOperationAction(ISD::CTTZ , MVT::i64 , Legal); in PPCTargetLowering()
466 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); in PPCTargetLowering()
467 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); in PPCTargetLowering()
471 setOperationAction(ISD::CTPOP, MVT::i32 , Legal); in PPCTargetLowering()
472 setOperationAction(ISD::CTPOP, MVT::i64 , Legal); in PPCTargetLowering()
474 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); in PPCTargetLowering()
475 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); in PPCTargetLowering()
479 setOperationAction(ISD::ROTR, MVT::i32 , Expand); in PPCTargetLowering()
480 setOperationAction(ISD::ROTR, MVT::i64 , Expand); in PPCTargetLowering()
484 setOperationAction(ISD::SELECT, MVT::i32, Expand); in PPCTargetLowering()
485 setOperationAction(ISD::SELECT, MVT::i64, Expand); in PPCTargetLowering()
486 setOperationAction(ISD::SELECT, MVT::f32, Expand); in PPCTargetLowering()
487 setOperationAction(ISD::SELECT, MVT::f64, Expand); in PPCTargetLowering()
491 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in PPCTargetLowering()
492 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in PPCTargetLowering()
496 setOperationAction(ISD::SETCC, MVT::i32, Custom); in PPCTargetLowering()
499 setOperationAction(ISD::STRICT_FSETCC, MVT::f32, Legal); in PPCTargetLowering()
500 setOperationAction(ISD::STRICT_FSETCC, MVT::f64, Legal); in PPCTargetLowering()
501 setOperationAction(ISD::STRICT_FSETCC, MVT::f128, Legal); in PPCTargetLowering()
503 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Legal); in PPCTargetLowering()
504 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Legal); in PPCTargetLowering()
505 setOperationAction(ISD::STRICT_FSETCCS, MVT::f128, Legal); in PPCTargetLowering()
510 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in PPCTargetLowering()
512 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in PPCTargetLowering()
516 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Legal); in PPCTargetLowering()
517 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Legal); in PPCTargetLowering()
518 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Legal); in PPCTargetLowering()
519 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal); in PPCTargetLowering()
520 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal); in PPCTargetLowering()
521 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal); in PPCTargetLowering()
524 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Legal); in PPCTargetLowering()
525 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Legal); in PPCTargetLowering()
528 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
529 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
532 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Expand); in PPCTargetLowering()
533 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Expand); in PPCTargetLowering()
534 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); in PPCTargetLowering()
535 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); in PPCTargetLowering()
539 setOperationAction(ISD::BITCAST, MVT::f32, Legal); in PPCTargetLowering()
540 setOperationAction(ISD::BITCAST, MVT::i32, Legal); in PPCTargetLowering()
541 setOperationAction(ISD::BITCAST, MVT::i64, Legal); in PPCTargetLowering()
542 setOperationAction(ISD::BITCAST, MVT::f64, Legal); in PPCTargetLowering()
544 setOperationAction(ISD::LRINT, MVT::f64, Legal); in PPCTargetLowering()
545 setOperationAction(ISD::LRINT, MVT::f32, Legal); in PPCTargetLowering()
546 setOperationAction(ISD::LLRINT, MVT::f64, Legal); in PPCTargetLowering()
547 setOperationAction(ISD::LLRINT, MVT::f32, Legal); in PPCTargetLowering()
548 setOperationAction(ISD::LROUND, MVT::f64, Legal); in PPCTargetLowering()
549 setOperationAction(ISD::LROUND, MVT::f32, Legal); in PPCTargetLowering()
550 setOperationAction(ISD::LLROUND, MVT::f64, Legal); in PPCTargetLowering()
551 setOperationAction(ISD::LLROUND, MVT::f32, Legal); in PPCTargetLowering()
554 setOperationAction(ISD::BITCAST, MVT::f32, Expand); in PPCTargetLowering()
555 setOperationAction(ISD::BITCAST, MVT::i32, Expand); in PPCTargetLowering()
556 setOperationAction(ISD::BITCAST, MVT::i64, Expand); in PPCTargetLowering()
557 setOperationAction(ISD::BITCAST, MVT::f64, Expand); in PPCTargetLowering()
561 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in PPCTargetLowering()
569 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom); in PPCTargetLowering()
570 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom); in PPCTargetLowering()
574 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); in PPCTargetLowering()
575 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); in PPCTargetLowering()
576 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); in PPCTargetLowering()
577 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); in PPCTargetLowering()
578 setOperationAction(ISD::JumpTable, MVT::i32, Custom); in PPCTargetLowering()
579 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); in PPCTargetLowering()
580 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); in PPCTargetLowering()
581 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); in PPCTargetLowering()
582 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); in PPCTargetLowering()
583 setOperationAction(ISD::JumpTable, MVT::i64, Custom); in PPCTargetLowering()
586 setOperationAction(ISD::TRAP, MVT::Other, Legal); in PPCTargetLowering()
589 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); in PPCTargetLowering()
590 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); in PPCTargetLowering()
593 setOperationAction(ISD::VASTART , MVT::Other, Custom); in PPCTargetLowering()
597 setOperationAction(ISD::VAARG, MVT::i1, Promote); in PPCTargetLowering()
598 AddPromotedToType(ISD::VAARG, MVT::i1, MVT::i64); in PPCTargetLowering()
599 setOperationAction(ISD::VAARG, MVT::i8, Promote); in PPCTargetLowering()
600 AddPromotedToType(ISD::VAARG, MVT::i8, MVT::i64); in PPCTargetLowering()
601 setOperationAction(ISD::VAARG, MVT::i16, Promote); in PPCTargetLowering()
602 AddPromotedToType(ISD::VAARG, MVT::i16, MVT::i64); in PPCTargetLowering()
603 setOperationAction(ISD::VAARG, MVT::i32, Promote); in PPCTargetLowering()
604 AddPromotedToType(ISD::VAARG, MVT::i32, MVT::i64); in PPCTargetLowering()
605 setOperationAction(ISD::VAARG, MVT::Other, Expand); in PPCTargetLowering()
608 setOperationAction(ISD::VAARG, MVT::Other, Custom); in PPCTargetLowering()
609 setOperationAction(ISD::VAARG, MVT::i64, Custom); in PPCTargetLowering()
611 setOperationAction(ISD::VAARG, MVT::Other, Expand); in PPCTargetLowering()
615 setOperationAction(ISD::VACOPY , MVT::Other, Custom); in PPCTargetLowering()
617 setOperationAction(ISD::VACOPY , MVT::Other, Expand); in PPCTargetLowering()
620 setOperationAction(ISD::VAEND , MVT::Other, Expand); in PPCTargetLowering()
621 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); in PPCTargetLowering()
622 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); in PPCTargetLowering()
623 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); in PPCTargetLowering()
624 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); in PPCTargetLowering()
625 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i32, Custom); in PPCTargetLowering()
626 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i64, Custom); in PPCTargetLowering()
627 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom); in PPCTargetLowering()
628 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom); in PPCTargetLowering()
631 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in PPCTargetLowering()
632 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f64, Custom); in PPCTargetLowering()
633 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::ppcf128, Custom); in PPCTargetLowering()
634 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom); in PPCTargetLowering()
635 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v2f64, Custom); in PPCTargetLowering()
638 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom); in PPCTargetLowering()
640 setOperationAction(ISD::INTRINSIC_VOID, MVT::i8, Custom); in PPCTargetLowering()
641 setOperationAction(ISD::INTRINSIC_VOID, MVT::i16, Custom); in PPCTargetLowering()
642 setOperationAction(ISD::INTRINSIC_VOID, MVT::i32, Custom); in PPCTargetLowering()
643 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); in PPCTargetLowering()
647 setCondCodeAction(ISD::SETO, MVT::f32, Expand); in PPCTargetLowering()
648 setCondCodeAction(ISD::SETO, MVT::f64, Expand); in PPCTargetLowering()
649 setCondCodeAction(ISD::SETUO, MVT::f32, Expand); in PPCTargetLowering()
650 setCondCodeAction(ISD::SETUO, MVT::f64, Expand); in PPCTargetLowering()
652 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); in PPCTargetLowering()
653 setCondCodeAction(ISD::SETULT, MVT::f64, Expand); in PPCTargetLowering()
654 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); in PPCTargetLowering()
655 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); in PPCTargetLowering()
656 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); in PPCTargetLowering()
657 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand); in PPCTargetLowering()
658 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); in PPCTargetLowering()
659 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); in PPCTargetLowering()
660 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); in PPCTargetLowering()
661 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); in PPCTargetLowering()
662 setCondCodeAction(ISD::SETONE, MVT::f32, Expand); in PPCTargetLowering()
663 setCondCodeAction(ISD::SETONE, MVT::f64, Expand); in PPCTargetLowering()
665 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f32, Legal); in PPCTargetLowering()
666 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f64, Legal); in PPCTargetLowering()
670 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
671 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i64, Expand); in PPCTargetLowering()
672 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
673 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i64, Expand); in PPCTargetLowering()
674 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
675 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); in PPCTargetLowering()
676 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
677 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); in PPCTargetLowering()
680 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom); in PPCTargetLowering()
681 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in PPCTargetLowering()
684 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
685 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
690 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Legal); in PPCTargetLowering()
691 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal); in PPCTargetLowering()
693 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Expand); in PPCTargetLowering()
694 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); in PPCTargetLowering()
701 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
702 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i64, Custom); in PPCTargetLowering()
703 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
704 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
705 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
706 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); in PPCTargetLowering()
707 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
708 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
711 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
712 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom); in PPCTargetLowering()
713 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
714 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
715 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
716 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in PPCTargetLowering()
717 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
718 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
723 addRegisterClass(MVT::i64, &PPC::G8RCRegClass); in PPCTargetLowering()
725 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); in PPCTargetLowering()
727 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); in PPCTargetLowering()
728 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); in PPCTargetLowering()
729 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); in PPCTargetLowering()
732 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); in PPCTargetLowering()
733 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); in PPCTargetLowering()
734 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); in PPCTargetLowering()
740 setOperationAction(ISD::FSHL, MVT::i64, Custom); in PPCTargetLowering()
741 setOperationAction(ISD::FSHR, MVT::i64, Custom); in PPCTargetLowering()
743 setOperationAction(ISD::FSHL, MVT::i32, Custom); in PPCTargetLowering()
744 setOperationAction(ISD::FSHR, MVT::i32, Custom); in PPCTargetLowering()
747 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f64, Legal); in PPCTargetLowering()
748 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f32, Legal); in PPCTargetLowering()
749 setOperationAction(ISD::FMINNUM_IEEE, MVT::f64, Legal); in PPCTargetLowering()
750 setOperationAction(ISD::FMINNUM_IEEE, MVT::f32, Legal); in PPCTargetLowering()
754 for (MVT VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) { in PPCTargetLowering()
762 for (MVT VT : MVT::fixedlen_vector_valuetypes()) { in PPCTargetLowering()
788 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) { in PPCTargetLowering()
798 if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128)) in PPCTargetLowering()
805 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); in PPCTargetLowering()
809 AddPromotedToType (ISD::AND , VT, MVT::v4i32); in PPCTargetLowering()
811 AddPromotedToType (ISD::OR , VT, MVT::v4i32); in PPCTargetLowering()
813 AddPromotedToType (ISD::XOR , VT, MVT::v4i32); in PPCTargetLowering()
815 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32); in PPCTargetLowering()
817 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32); in PPCTargetLowering()
820 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32); in PPCTargetLowering()
822 AddPromotedToType (ISD::STORE, VT, MVT::v4i32); in PPCTargetLowering()
863 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) { in PPCTargetLowering()
870 setOperationAction(ISD::SELECT_CC, MVT::v4i32, Expand); in PPCTargetLowering()
872 setOperationAction(ISD::SMAX, MVT::v2i64, Expand); in PPCTargetLowering()
873 setOperationAction(ISD::SMIN, MVT::v2i64, Expand); in PPCTargetLowering()
874 setOperationAction(ISD::UMAX, MVT::v2i64, Expand); in PPCTargetLowering()
875 setOperationAction(ISD::UMIN, MVT::v2i64, Expand); in PPCTargetLowering()
880 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); in PPCTargetLowering()
884 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Custom); in PPCTargetLowering()
885 setOperationAction(ISD::TRUNCATE, MVT::v4i8, Custom); in PPCTargetLowering()
886 setOperationAction(ISD::TRUNCATE, MVT::v2i8, Custom); in PPCTargetLowering()
887 setOperationAction(ISD::TRUNCATE, MVT::v4i16, Custom); in PPCTargetLowering()
888 setOperationAction(ISD::TRUNCATE, MVT::v2i16, Custom); in PPCTargetLowering()
890 setOperationAction(ISD::AND , MVT::v4i32, Legal); in PPCTargetLowering()
891 setOperationAction(ISD::OR , MVT::v4i32, Legal); in PPCTargetLowering()
892 setOperationAction(ISD::XOR , MVT::v4i32, Legal); in PPCTargetLowering()
893 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); in PPCTargetLowering()
894 setOperationAction(ISD::SELECT, MVT::v4i32, in PPCTargetLowering()
896 setOperationAction(ISD::STORE , MVT::v4i32, Legal); in PPCTargetLowering()
897 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v4i32, Legal); in PPCTargetLowering()
898 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v4i32, Legal); in PPCTargetLowering()
899 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i32, Legal); in PPCTargetLowering()
900 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i32, Legal); in PPCTargetLowering()
901 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); in PPCTargetLowering()
902 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal); in PPCTargetLowering()
903 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); in PPCTargetLowering()
904 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal); in PPCTargetLowering()
905 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal); in PPCTargetLowering()
906 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); in PPCTargetLowering()
907 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal); in PPCTargetLowering()
908 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); in PPCTargetLowering()
911 setOperationAction(ISD::ROTL, MVT::v1i128, Custom); in PPCTargetLowering()
914 for (auto VT : {MVT::v4i32, MVT::v8i16, MVT::v16i8}) in PPCTargetLowering()
918 setOperationAction(ISD::ROTL, MVT::v2i64, Legal); in PPCTargetLowering()
920 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass); in PPCTargetLowering()
921 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass); in PPCTargetLowering()
922 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass); in PPCTargetLowering()
923 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass); in PPCTargetLowering()
925 setOperationAction(ISD::MUL, MVT::v4f32, Legal); in PPCTargetLowering()
926 setOperationAction(ISD::FMA, MVT::v4f32, Legal); in PPCTargetLowering()
929 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); in PPCTargetLowering()
930 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); in PPCTargetLowering()
931 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); in PPCTargetLowering()
935 setOperationAction(ISD::MUL, MVT::v4i32, Legal); in PPCTargetLowering()
937 setOperationAction(ISD::MUL, MVT::v4i32, Custom); in PPCTargetLowering()
940 setOperationAction(ISD::MUL, MVT::v2i64, Legal); in PPCTargetLowering()
941 setOperationAction(ISD::MULHS, MVT::v2i64, Legal); in PPCTargetLowering()
942 setOperationAction(ISD::MULHU, MVT::v2i64, Legal); in PPCTargetLowering()
943 setOperationAction(ISD::MULHS, MVT::v4i32, Legal); in PPCTargetLowering()
944 setOperationAction(ISD::MULHU, MVT::v4i32, Legal); in PPCTargetLowering()
945 setOperationAction(ISD::UDIV, MVT::v2i64, Legal); in PPCTargetLowering()
946 setOperationAction(ISD::SDIV, MVT::v2i64, Legal); in PPCTargetLowering()
947 setOperationAction(ISD::UDIV, MVT::v4i32, Legal); in PPCTargetLowering()
948 setOperationAction(ISD::SDIV, MVT::v4i32, Legal); in PPCTargetLowering()
949 setOperationAction(ISD::UREM, MVT::v2i64, Legal); in PPCTargetLowering()
950 setOperationAction(ISD::SREM, MVT::v2i64, Legal); in PPCTargetLowering()
951 setOperationAction(ISD::UREM, MVT::v4i32, Legal); in PPCTargetLowering()
952 setOperationAction(ISD::SREM, MVT::v4i32, Legal); in PPCTargetLowering()
953 setOperationAction(ISD::UREM, MVT::v1i128, Legal); in PPCTargetLowering()
954 setOperationAction(ISD::SREM, MVT::v1i128, Legal); in PPCTargetLowering()
955 setOperationAction(ISD::UDIV, MVT::v1i128, Legal); in PPCTargetLowering()
956 setOperationAction(ISD::SDIV, MVT::v1i128, Legal); in PPCTargetLowering()
957 setOperationAction(ISD::ROTL, MVT::v1i128, Legal); in PPCTargetLowering()
960 setOperationAction(ISD::MUL, MVT::v8i16, Legal); in PPCTargetLowering()
961 setOperationAction(ISD::MUL, MVT::v16i8, Custom); in PPCTargetLowering()
963 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); in PPCTargetLowering()
964 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); in PPCTargetLowering()
966 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); in PPCTargetLowering()
967 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); in PPCTargetLowering()
968 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); in PPCTargetLowering()
969 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); in PPCTargetLowering()
972 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand); in PPCTargetLowering()
973 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand); in PPCTargetLowering()
974 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand); in PPCTargetLowering()
975 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand); in PPCTargetLowering()
978 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal); in PPCTargetLowering()
979 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal); in PPCTargetLowering()
981 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal); in PPCTargetLowering()
982 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal); in PPCTargetLowering()
985 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal); in PPCTargetLowering()
986 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal); in PPCTargetLowering()
987 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal); in PPCTargetLowering()
988 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal); in PPCTargetLowering()
989 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Legal); in PPCTargetLowering()
990 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Legal); in PPCTargetLowering()
991 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal); in PPCTargetLowering()
992 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); in PPCTargetLowering()
994 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal); in PPCTargetLowering()
999 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); in PPCTargetLowering()
1000 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); in PPCTargetLowering()
1003 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal); in PPCTargetLowering()
1004 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal); in PPCTargetLowering()
1005 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal); in PPCTargetLowering()
1006 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal); in PPCTargetLowering()
1007 setOperationAction(ISD::FRINT, MVT::v2f64, Legal); in PPCTargetLowering()
1008 setOperationAction(ISD::FROUND, MVT::v2f64, Legal); in PPCTargetLowering()
1009 setOperationAction(ISD::FROUND, MVT::f64, Legal); in PPCTargetLowering()
1010 setOperationAction(ISD::FRINT, MVT::f64, Legal); in PPCTargetLowering()
1012 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); in PPCTargetLowering()
1013 setOperationAction(ISD::FRINT, MVT::v4f32, Legal); in PPCTargetLowering()
1014 setOperationAction(ISD::FROUND, MVT::v4f32, Legal); in PPCTargetLowering()
1015 setOperationAction(ISD::FROUND, MVT::f32, Legal); in PPCTargetLowering()
1016 setOperationAction(ISD::FRINT, MVT::f32, Legal); in PPCTargetLowering()
1018 setOperationAction(ISD::MUL, MVT::v2f64, Legal); in PPCTargetLowering()
1019 setOperationAction(ISD::FMA, MVT::v2f64, Legal); in PPCTargetLowering()
1021 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); in PPCTargetLowering()
1022 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); in PPCTargetLowering()
1025 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand); in PPCTargetLowering()
1026 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand); in PPCTargetLowering()
1027 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand); in PPCTargetLowering()
1028 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand); in PPCTargetLowering()
1030 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); in PPCTargetLowering()
1031 setOperationAction(ISD::STORE, MVT::v2f64, Legal); in PPCTargetLowering()
1033 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); in PPCTargetLowering()
1036 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass); in PPCTargetLowering()
1038 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass); in PPCTargetLowering()
1040 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass); in PPCTargetLowering()
1041 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass); in PPCTargetLowering()
1042 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass); in PPCTargetLowering()
1045 setOperationAction(ISD::SHL, MVT::v2i64, Legal); in PPCTargetLowering()
1046 setOperationAction(ISD::SRA, MVT::v2i64, Legal); in PPCTargetLowering()
1047 setOperationAction(ISD::SRL, MVT::v2i64, Legal); in PPCTargetLowering()
1053 setOperationAction(ISD::SHL, MVT::v1i128, Expand); in PPCTargetLowering()
1054 setOperationAction(ISD::SRL, MVT::v1i128, Expand); in PPCTargetLowering()
1055 setOperationAction(ISD::SRA, MVT::v1i128, Expand); in PPCTargetLowering()
1057 setOperationAction(ISD::SETCC, MVT::v2i64, Legal); in PPCTargetLowering()
1060 setOperationAction(ISD::SHL, MVT::v2i64, Expand); in PPCTargetLowering()
1061 setOperationAction(ISD::SRA, MVT::v2i64, Expand); in PPCTargetLowering()
1062 setOperationAction(ISD::SRL, MVT::v2i64, Expand); in PPCTargetLowering()
1064 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); in PPCTargetLowering()
1067 setOperationAction(ISD::ADD, MVT::v2i64, Expand); in PPCTargetLowering()
1068 setOperationAction(ISD::SUB, MVT::v2i64, Expand); in PPCTargetLowering()
1072 setOperationAction(ISD::SETCC, MVT::v1i128, Legal); in PPCTargetLowering()
1074 setOperationAction(ISD::SETCC, MVT::v1i128, Expand); in PPCTargetLowering()
1076 setOperationAction(ISD::LOAD, MVT::v2i64, Promote); in PPCTargetLowering()
1077 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64); in PPCTargetLowering()
1078 setOperationAction(ISD::STORE, MVT::v2i64, Promote); in PPCTargetLowering()
1079 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64); in PPCTargetLowering()
1081 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); in PPCTargetLowering()
1083 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i64, Legal); in PPCTargetLowering()
1084 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i64, Legal); in PPCTargetLowering()
1085 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2i64, Legal); in PPCTargetLowering()
1086 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2i64, Legal); in PPCTargetLowering()
1087 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal); in PPCTargetLowering()
1088 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal); in PPCTargetLowering()
1089 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal); in PPCTargetLowering()
1090 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal); in PPCTargetLowering()
1095 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i8, Custom); in PPCTargetLowering()
1096 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i8, Custom); in PPCTargetLowering()
1097 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i16, Custom); in PPCTargetLowering()
1098 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i16, Custom); in PPCTargetLowering()
1099 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i8, Custom); in PPCTargetLowering()
1100 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i8, Custom); in PPCTargetLowering()
1101 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i16, Custom); in PPCTargetLowering()
1102 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i16, Custom); in PPCTargetLowering()
1103 setOperationAction(ISD::UINT_TO_FP, MVT::v2i8, Custom); in PPCTargetLowering()
1104 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom); in PPCTargetLowering()
1105 setOperationAction(ISD::UINT_TO_FP, MVT::v2i16, Custom); in PPCTargetLowering()
1106 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom); in PPCTargetLowering()
1107 setOperationAction(ISD::SINT_TO_FP, MVT::v2i8, Custom); in PPCTargetLowering()
1108 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Custom); in PPCTargetLowering()
1109 setOperationAction(ISD::SINT_TO_FP, MVT::v2i16, Custom); in PPCTargetLowering()
1110 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom); in PPCTargetLowering()
1112 setOperationAction(ISD::FNEG, MVT::v4f32, Legal); in PPCTargetLowering()
1113 setOperationAction(ISD::FNEG, MVT::v2f64, Legal); in PPCTargetLowering()
1114 setOperationAction(ISD::FABS, MVT::v4f32, Legal); in PPCTargetLowering()
1115 setOperationAction(ISD::FABS, MVT::v2f64, Legal); in PPCTargetLowering()
1116 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal); in PPCTargetLowering()
1117 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Legal); in PPCTargetLowering()
1119 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); in PPCTargetLowering()
1120 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); in PPCTargetLowering()
1125 setOperationAction(ISD::STRICT_FADD, MVT::v4f32, Legal); in PPCTargetLowering()
1126 setOperationAction(ISD::STRICT_FSUB, MVT::v4f32, Legal); in PPCTargetLowering()
1127 setOperationAction(ISD::STRICT_FMUL, MVT::v4f32, Legal); in PPCTargetLowering()
1128 setOperationAction(ISD::STRICT_FDIV, MVT::v4f32, Legal); in PPCTargetLowering()
1129 setOperationAction(ISD::STRICT_FMA, MVT::v4f32, Legal); in PPCTargetLowering()
1130 setOperationAction(ISD::STRICT_FSQRT, MVT::v4f32, Legal); in PPCTargetLowering()
1131 setOperationAction(ISD::STRICT_FMAXNUM, MVT::v4f32, Legal); in PPCTargetLowering()
1132 setOperationAction(ISD::STRICT_FMINNUM, MVT::v4f32, Legal); in PPCTargetLowering()
1133 setOperationAction(ISD::STRICT_FRINT, MVT::v4f32, Legal); in PPCTargetLowering()
1134 setOperationAction(ISD::STRICT_FFLOOR, MVT::v4f32, Legal); in PPCTargetLowering()
1135 setOperationAction(ISD::STRICT_FCEIL, MVT::v4f32, Legal); in PPCTargetLowering()
1136 setOperationAction(ISD::STRICT_FTRUNC, MVT::v4f32, Legal); in PPCTargetLowering()
1137 setOperationAction(ISD::STRICT_FROUND, MVT::v4f32, Legal); in PPCTargetLowering()
1139 setOperationAction(ISD::STRICT_FADD, MVT::v2f64, Legal); in PPCTargetLowering()
1140 setOperationAction(ISD::STRICT_FSUB, MVT::v2f64, Legal); in PPCTargetLowering()
1141 setOperationAction(ISD::STRICT_FMUL, MVT::v2f64, Legal); in PPCTargetLowering()
1142 setOperationAction(ISD::STRICT_FDIV, MVT::v2f64, Legal); in PPCTargetLowering()
1143 setOperationAction(ISD::STRICT_FMA, MVT::v2f64, Legal); in PPCTargetLowering()
1144 setOperationAction(ISD::STRICT_FSQRT, MVT::v2f64, Legal); in PPCTargetLowering()
1145 setOperationAction(ISD::STRICT_FMAXNUM, MVT::v2f64, Legal); in PPCTargetLowering()
1146 setOperationAction(ISD::STRICT_FMINNUM, MVT::v2f64, Legal); in PPCTargetLowering()
1147 setOperationAction(ISD::STRICT_FRINT, MVT::v2f64, Legal); in PPCTargetLowering()
1148 setOperationAction(ISD::STRICT_FFLOOR, MVT::v2f64, Legal); in PPCTargetLowering()
1149 setOperationAction(ISD::STRICT_FCEIL, MVT::v2f64, Legal); in PPCTargetLowering()
1150 setOperationAction(ISD::STRICT_FTRUNC, MVT::v2f64, Legal); in PPCTargetLowering()
1151 setOperationAction(ISD::STRICT_FROUND, MVT::v2f64, Legal); in PPCTargetLowering()
1153 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass); in PPCTargetLowering()
1154 addRegisterClass(MVT::f128, &PPC::VRRCRegClass); in PPCTargetLowering()
1156 for (MVT FPT : MVT::fp_valuetypes()) in PPCTargetLowering()
1157 setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand); in PPCTargetLowering()
1160 setOperationAction(ISD::SELECT, MVT::f128, Expand); in PPCTargetLowering()
1162 setTruncStoreAction(MVT::f128, MVT::f64, Expand); in PPCTargetLowering()
1163 setTruncStoreAction(MVT::f128, MVT::f32, Expand); in PPCTargetLowering()
1166 setOperationAction(ISD::FSIN, MVT::f128, Expand); in PPCTargetLowering()
1167 setOperationAction(ISD::FCOS, MVT::f128, Expand); in PPCTargetLowering()
1168 setOperationAction(ISD::FPOW, MVT::f128, Expand); in PPCTargetLowering()
1169 setOperationAction(ISD::FPOWI, MVT::f128, Expand); in PPCTargetLowering()
1170 setOperationAction(ISD::FREM, MVT::f128, Expand); in PPCTargetLowering()
1174 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass); in PPCTargetLowering()
1175 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass); in PPCTargetLowering()
1179 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); in PPCTargetLowering()
1180 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in PPCTargetLowering()
1185 setOperationAction(ISD::SHL, MVT::v1i128, Legal); in PPCTargetLowering()
1186 setOperationAction(ISD::SRL, MVT::v1i128, Legal); in PPCTargetLowering()
1187 setOperationAction(ISD::SRA, MVT::v1i128, Expand); in PPCTargetLowering()
1189 setOperationAction(ISD::FADD, MVT::f128, Legal); in PPCTargetLowering()
1190 setOperationAction(ISD::FSUB, MVT::f128, Legal); in PPCTargetLowering()
1191 setOperationAction(ISD::FDIV, MVT::f128, Legal); in PPCTargetLowering()
1192 setOperationAction(ISD::FMUL, MVT::f128, Legal); in PPCTargetLowering()
1193 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal); in PPCTargetLowering()
1195 setOperationAction(ISD::FMA, MVT::f128, Legal); in PPCTargetLowering()
1196 setCondCodeAction(ISD::SETULT, MVT::f128, Expand); in PPCTargetLowering()
1197 setCondCodeAction(ISD::SETUGT, MVT::f128, Expand); in PPCTargetLowering()
1198 setCondCodeAction(ISD::SETUEQ, MVT::f128, Expand); in PPCTargetLowering()
1199 setCondCodeAction(ISD::SETOGE, MVT::f128, Expand); in PPCTargetLowering()
1200 setCondCodeAction(ISD::SETOLE, MVT::f128, Expand); in PPCTargetLowering()
1201 setCondCodeAction(ISD::SETONE, MVT::f128, Expand); in PPCTargetLowering()
1203 setOperationAction(ISD::FTRUNC, MVT::f128, Legal); in PPCTargetLowering()
1204 setOperationAction(ISD::FRINT, MVT::f128, Legal); in PPCTargetLowering()
1205 setOperationAction(ISD::FFLOOR, MVT::f128, Legal); in PPCTargetLowering()
1206 setOperationAction(ISD::FCEIL, MVT::f128, Legal); in PPCTargetLowering()
1207 setOperationAction(ISD::FNEARBYINT, MVT::f128, Legal); in PPCTargetLowering()
1208 setOperationAction(ISD::FROUND, MVT::f128, Legal); in PPCTargetLowering()
1210 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); in PPCTargetLowering()
1211 setOperationAction(ISD::FP_ROUND, MVT::f32, Legal); in PPCTargetLowering()
1212 setOperationAction(ISD::BITCAST, MVT::i128, Custom); in PPCTargetLowering()
1215 setOperationAction(ISD::STRICT_FADD, MVT::f128, Legal); in PPCTargetLowering()
1216 setOperationAction(ISD::STRICT_FSUB, MVT::f128, Legal); in PPCTargetLowering()
1217 setOperationAction(ISD::STRICT_FMUL, MVT::f128, Legal); in PPCTargetLowering()
1218 setOperationAction(ISD::STRICT_FDIV, MVT::f128, Legal); in PPCTargetLowering()
1219 setOperationAction(ISD::STRICT_FMA, MVT::f128, Legal); in PPCTargetLowering()
1220 setOperationAction(ISD::STRICT_FSQRT, MVT::f128, Legal); in PPCTargetLowering()
1221 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f128, Legal); in PPCTargetLowering()
1222 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Legal); in PPCTargetLowering()
1223 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal); in PPCTargetLowering()
1224 setOperationAction(ISD::STRICT_FRINT, MVT::f128, Legal); in PPCTargetLowering()
1225 setOperationAction(ISD::STRICT_FNEARBYINT, MVT::f128, Legal); in PPCTargetLowering()
1226 setOperationAction(ISD::STRICT_FFLOOR, MVT::f128, Legal); in PPCTargetLowering()
1227 setOperationAction(ISD::STRICT_FCEIL, MVT::f128, Legal); in PPCTargetLowering()
1228 setOperationAction(ISD::STRICT_FTRUNC, MVT::f128, Legal); in PPCTargetLowering()
1229 setOperationAction(ISD::STRICT_FROUND, MVT::f128, Legal); in PPCTargetLowering()
1230 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom); in PPCTargetLowering()
1231 setOperationAction(ISD::BSWAP, MVT::v8i16, Legal); in PPCTargetLowering()
1232 setOperationAction(ISD::BSWAP, MVT::v4i32, Legal); in PPCTargetLowering()
1233 setOperationAction(ISD::BSWAP, MVT::v2i64, Legal); in PPCTargetLowering()
1234 setOperationAction(ISD::BSWAP, MVT::v1i128, Legal); in PPCTargetLowering()
1236 setOperationAction(ISD::LOAD, MVT::f128, Promote); in PPCTargetLowering()
1237 setOperationAction(ISD::STORE, MVT::f128, Promote); in PPCTargetLowering()
1239 AddPromotedToType(ISD::LOAD, MVT::f128, MVT::v4i32); in PPCTargetLowering()
1240 AddPromotedToType(ISD::STORE, MVT::f128, MVT::v4i32); in PPCTargetLowering()
1244 setOperationAction(ISD::FADD, MVT::f128, LibCall); in PPCTargetLowering()
1245 setOperationAction(ISD::FSUB, MVT::f128, LibCall); in PPCTargetLowering()
1247 setOperationAction(ISD::FMUL, MVT::f128, Expand); in PPCTargetLowering()
1248 setOperationAction(ISD::FDIV, MVT::f128, Expand); in PPCTargetLowering()
1249 setOperationAction(ISD::FNEG, MVT::f128, Expand); in PPCTargetLowering()
1250 setOperationAction(ISD::FABS, MVT::f128, Expand); in PPCTargetLowering()
1251 setOperationAction(ISD::FSQRT, MVT::f128, Expand); in PPCTargetLowering()
1252 setOperationAction(ISD::FMA, MVT::f128, Expand); in PPCTargetLowering()
1253 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); in PPCTargetLowering()
1256 setOperationAction(ISD::FP_EXTEND, MVT::f128, Expand); in PPCTargetLowering()
1257 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f128, Expand); in PPCTargetLowering()
1260 for (MVT VT : {MVT::f32, MVT::f64}) { in PPCTargetLowering()
1265 setOperationAction(ISD::SETCC, MVT::f128, Custom); in PPCTargetLowering()
1266 setOperationAction(ISD::STRICT_FSETCC, MVT::f128, Custom); in PPCTargetLowering()
1267 setOperationAction(ISD::STRICT_FSETCCS, MVT::f128, Custom); in PPCTargetLowering()
1268 setOperationAction(ISD::BR_CC, MVT::f128, Expand); in PPCTargetLowering()
1272 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); in PPCTargetLowering()
1275 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in PPCTargetLowering()
1276 setOperationAction(ISD::SELECT_CC, MVT::i64, isPPC64 ? Custom : Expand); in PPCTargetLowering()
1281 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); in PPCTargetLowering()
1282 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Legal); in PPCTargetLowering()
1283 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Legal); in PPCTargetLowering()
1284 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal); in PPCTargetLowering()
1286 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); in PPCTargetLowering()
1287 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); in PPCTargetLowering()
1289 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal); in PPCTargetLowering()
1290 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal); in PPCTargetLowering()
1291 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal); in PPCTargetLowering()
1292 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Legal); in PPCTargetLowering()
1293 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal); in PPCTargetLowering()
1294 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal); in PPCTargetLowering()
1295 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal); in PPCTargetLowering()
1299 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); in PPCTargetLowering()
1304 addRegisterClass(MVT::v256i1, &PPC::VSRpRCRegClass); in PPCTargetLowering()
1305 setOperationAction(ISD::LOAD, MVT::v256i1, Custom); in PPCTargetLowering()
1306 setOperationAction(ISD::STORE, MVT::v256i1, Custom); in PPCTargetLowering()
1309 addRegisterClass(MVT::v512i1, &PPC::UACCRCRegClass); in PPCTargetLowering()
1310 setOperationAction(ISD::LOAD, MVT::v512i1, Custom); in PPCTargetLowering()
1311 setOperationAction(ISD::STORE, MVT::v512i1, Custom); in PPCTargetLowering()
1312 setOperationAction(ISD::BUILD_VECTOR, MVT::v512i1, Custom); in PPCTargetLowering()
1316 setOperationAction(ISD::PREFETCH, MVT::Other, Legal); in PPCTargetLowering()
1319 setOperationAction(ISD::SRA, MVT::v1i128, Legal); in PPCTargetLowering()
1321 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom); in PPCTargetLowering()
1324 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); in PPCTargetLowering()
1325 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); in PPCTargetLowering()
1329 setOperationAction(ISD::ATOMIC_LOAD, MVT::i128, Custom); in PPCTargetLowering()
1330 setOperationAction(ISD::ATOMIC_STORE, MVT::i128, Custom); in PPCTargetLowering()
1331 setOperationAction(ISD::INTRINSIC_VOID, MVT::i128, Custom); in PPCTargetLowering()
1781 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32; in getSetCCResultType()
1933 if (N->getValueType(0) != MVT::v16i8) in isVMerge()
2043 if (N->getValueType(0) != MVT::v16i8) in isVMerge()
2101 if (N->getValueType(0) != MVT::v16i8) in isVSLDOIShuffleMask()
2145 if (VT == MVT::v2i64 || VT == MVT::v2f64) in isSplatShuffleMask()
2148 assert(VT == MVT::v16i8 && isPowerOf2_32(EltSize) && in isSplatShuffleMask()
2292 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"); in isXXSLDWIShuffleMask()
2353 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"); in isXXBRShuffleMaskHelper()
2391 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"); in isXXPERMDIShuffleMask()
2451 if (VT == MVT::v2i64 || VT == MVT::v2f64) in getSplatIdxForPPCMnemonics()
2507 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef in get_VSPLTI_elt()
2510 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32); in get_VSPLTI_elt()
2514 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef in get_VSPLTI_elt()
2517 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32); in get_VSPLTI_elt()
2539 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); in get_VSPLTI_elt()
2561 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32); in get_VSPLTI_elt()
2578 if (N->getValueType(0) == MVT::i32) in isIntS16Immediate()
2609 if (Memop->getMemoryVT() == MVT::f64) { in SelectAddressEVXRegReg()
2697 if (VT != MVT::i64) in fixupFuncForFI()
2807 if ((CN->getValueType(0) == MVT::i32 || in SelectAddressRegImm()
2814 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32); in SelectAddressRegImm()
2817 MVT::i32); in SelectAddressRegImm()
2818 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; in SelectAddressRegImm()
2839 if (N.getValueType() != MVT::i64) in SelectAddressRegImm34()
2950 case MVT::i64: in usePartialVectorLoads()
2952 case MVT::i32: in usePartialVectorLoads()
2956 case MVT::i16: in usePartialVectorLoads()
2957 case MVT::i8: in usePartialVectorLoads()
3038 if (VT != MVT::i64) { in getPreIndexedAddressParts()
3053 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 && in getPreIndexedAddressParts()
3113 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; in getTOCEntry()
3120 PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT, in getTOCEntry()
3344 SDValue TLSReg = DAG.getRegister(PPC::X13, MVT::i64); in LowerGlobalTLSAddressLinux()
3356 SDValue TLSReg = is64bit ? DAG.getRegister(PPC::X13, MVT::i64) in LowerGlobalTLSAddressLinux()
3357 : DAG.getRegister(PPC::R2, MVT::i32); in LowerGlobalTLSAddressLinux()
3373 TPOffset = DAG.getLoad(MVT::i64, dl, DAG.getEntryNode(), MatPCRel, in LowerGlobalTLSAddressLinux()
3379 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); in LowerGlobalTLSAddressLinux()
3406 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); in LowerGlobalTLSAddressLinux()
3432 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); in LowerGlobalTLSAddressLinux()
3468 SDValue Load = DAG.getLoad(MVT::i64, DL, DAG.getEntryNode(), MatPCRel, in LowerGlobalAddress()
3512 if (LHSVT == MVT::f128) { in LowerSETCC()
3527 if (Op.getValueType() == MVT::v2i64) { in LowerSETCC()
3530 if (LHS.getValueType() == MVT::v2i64) { in LowerSETCC()
3536 dl, MVT::v4i32, DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, LHS), in LowerSETCC()
3537 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, RHS), CC); in LowerSETCC()
3540 DAG.getVectorShuffle(MVT::v4i32, dl, SetCC32, SetCC32, ShuffV); in LowerSETCC()
3541 return DAG.getBitcast(MVT::v2i64, in LowerSETCC()
3543 dl, MVT::v4i32, Shuff, SetCC32)); in LowerSETCC()
3589 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, in LowerVAARG()
3590 VAListPtr, MachinePointerInfo(SV), MVT::i8); in LowerVAARG()
3593 if (VT == MVT::i64) { in LowerVAARG()
3595 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex, in LowerVAARG()
3596 DAG.getConstant(1, dl, MVT::i32)); in LowerVAARG()
3597 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd, in LowerVAARG()
3598 DAG.getConstant(0, dl, MVT::i32), ISD::SETNE); in LowerVAARG()
3599 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex, in LowerVAARG()
3600 DAG.getConstant(1, dl, MVT::i32)); in LowerVAARG()
3602 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne, in LowerVAARG()
3608 DAG.getConstant(1, dl, MVT::i32)); in LowerVAARG()
3611 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, in LowerVAARG()
3612 FprPtr, MachinePointerInfo(SV), MVT::i8); in LowerVAARG()
3616 DAG.getConstant(8, dl, MVT::i32)); in LowerVAARG()
3619 DAG.getConstant(4, dl, MVT::i32)); in LowerVAARG()
3623 DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr, MachinePointerInfo()); in LowerVAARG()
3627 DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr, MachinePointerInfo()); in LowerVAARG()
3631 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex, in LowerVAARG()
3632 DAG.getConstant(8, dl, MVT::i32), ISD::SETLT); in LowerVAARG()
3635 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32, in LowerVAARG()
3638 MVT::i32)); in LowerVAARG()
3647 DAG.getConstant(32, dl, MVT::i32)); in LowerVAARG()
3650 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32, in LowerVAARG()
3652 DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl, in LowerVAARG()
3653 MVT::i32)); in LowerVAARG()
3657 MachinePointerInfo(SV), MVT::i8); in LowerVAARG()
3665 dl, MVT::i32)); in LowerVAARG()
3667 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea, in LowerVAARG()
3671 MachinePointerInfo(), MVT::i32); in LowerVAARG()
3682 DAG.getConstant(12, SDLoc(Op), MVT::i32), Align(8), in LowerVACOPY()
3711 if (Op.getOperand(NumOps - 1).getValueType() == MVT::Glue) in LowerINLINEASM()
3758 bool isPPC64 = (PtrVT == MVT::i64); in LowerINIT_TRAMPOLINE()
3769 isPPC64 ? MVT::i64 : MVT::i32); in LowerINIT_TRAMPOLINE()
3825 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32); in LowerVASTART()
3826 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32); in LowerVASTART()
3846 MachinePointerInfo(SV), MVT::i8); in LowerVASTART()
3854 MachinePointerInfo(SV, nextOffset), MVT::i8); in LowerVASTART()
3899 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 || in CalculateStackSlotAlignment()
3900 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 || in CalculateStackSlotAlignment()
3901 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 || in CalculateStackSlotAlignment()
3902 ArgVT == MVT::v1i128 || ArgVT == MVT::f128) in CalculateStackSlotAlignment()
3922 if (Flags.isSplit() && OrigVT != MVT::ppcf128) in CalculateStackSlotAlignment()
3963 if (ArgVT == MVT::f32 || ArgVT == MVT::f64) in CalculateStackSlotUsed()
3968 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 || in CalculateStackSlotUsed()
3969 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 || in CalculateStackSlotUsed()
3970 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 || in CalculateStackSlotUsed()
3971 ArgVT == MVT::v1i128 || ArgVT == MVT::f128) in CalculateStackSlotUsed()
4072 case MVT::i1: in LowerFormalArguments_32SVR4()
4073 case MVT::i32: in LowerFormalArguments_32SVR4()
4076 case MVT::f32: in LowerFormalArguments_32SVR4()
4084 case MVT::f64: in LowerFormalArguments_32SVR4()
4093 case MVT::v16i8: in LowerFormalArguments_32SVR4()
4094 case MVT::v8i16: in LowerFormalArguments_32SVR4()
4095 case MVT::v4i32: in LowerFormalArguments_32SVR4()
4098 case MVT::v4f32: in LowerFormalArguments_32SVR4()
4101 case MVT::v2f64: in LowerFormalArguments_32SVR4()
4102 case MVT::v2i64: in LowerFormalArguments_32SVR4()
4110 if (VA.getLocVT() == MVT::f64 && Subtarget.hasSPE()) { in LowerFormalArguments_32SVR4()
4114 SDValue ArgValueLo = DAG.getCopyFromReg(Chain, dl, RegLo, MVT::i32); in LowerFormalArguments_32SVR4()
4115 SDValue ArgValueHi = DAG.getCopyFromReg(Chain, dl, RegHi, MVT::i32); in LowerFormalArguments_32SVR4()
4118 ArgValue = DAG.getNode(PPCISD::BUILD_SPE64, dl, MVT::f64, ArgValueLo, in LowerFormalArguments_32SVR4()
4123 ValVT == MVT::i1 ? MVT::i32 : ValVT); in LowerFormalArguments_32SVR4()
4124 if (ValVT == MVT::i1) in LowerFormalArguments_32SVR4()
4125 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue); in LowerFormalArguments_32SVR4()
4198 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8; in LowerFormalArguments_32SVR4()
4236 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64); in LowerFormalArguments_32SVR4()
4241 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl, in LowerFormalArguments_32SVR4()
4248 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); in LowerFormalArguments_32SVR4()
4260 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal, in extendArgForPPC64()
4263 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal, in extendArgForPPC64()
4464 case MVT::i1: in LowerFormalArguments_64SVR4()
4465 case MVT::i32: in LowerFormalArguments_64SVR4()
4466 case MVT::i64: in LowerFormalArguments_64SVR4()
4470 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); in LowerFormalArguments_64SVR4()
4472 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1) in LowerFormalArguments_64SVR4()
4484 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); in LowerFormalArguments_64SVR4()
4486 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1) in LowerFormalArguments_64SVR4()
4501 case MVT::f32: in LowerFormalArguments_64SVR4()
4502 case MVT::f64: in LowerFormalArguments_64SVR4()
4509 if (ObjectVT == MVT::f32) in LowerFormalArguments_64SVR4()
4530 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); in LowerFormalArguments_64SVR4()
4532 if (ObjectVT == MVT::f32) { in LowerFormalArguments_64SVR4()
4534 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal, in LowerFormalArguments_64SVR4()
4535 DAG.getConstant(32, dl, MVT::i32)); in LowerFormalArguments_64SVR4()
4536 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal); in LowerFormalArguments_64SVR4()
4557 case MVT::v4f32: in LowerFormalArguments_64SVR4()
4558 case MVT::v4i32: in LowerFormalArguments_64SVR4()
4559 case MVT::v8i16: in LowerFormalArguments_64SVR4()
4560 case MVT::v16i8: in LowerFormalArguments_64SVR4()
4561 case MVT::v2f64: in LowerFormalArguments_64SVR4()
4562 case MVT::v2i64: in LowerFormalArguments_64SVR4()
4563 case MVT::v1i128: in LowerFormalArguments_64SVR4()
4564 case MVT::f128: in LowerFormalArguments_64SVR4()
4640 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); in LowerFormalArguments_64SVR4()
5011 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; in EmitTailCallStoreFPAndRetAddr()
5028 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; in CalculateTailCallArgDest()
5045 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in EmitTailCallLoadFPAndRetAddr()
5062 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32); in CreateCopyOfByValArgument()
5080 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); in LowerMemOpCallTo()
5082 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); in LowerMemOpCallTo()
5106 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2); in PrepareTailCall()
5151 if (Subtarget.hasSPE() && VA.getLocVT() == MVT::f64) { in LowerCallResult()
5152 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
5157 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
5163 Val = DAG.getNode(PPCISD::BUILD_SPE64, dl, MVT::f64, Lo, Hi); in LowerCallResult()
5313 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()); in transformCallee()
5369 if (LastValue.getValueType() != MVT::Glue) in getOutputChainFromCallSeq()
5381 EVT ReturnTypes[] = {MVT::Other, MVT::Glue}; in prepareIndirectCall()
5437 const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in prepareDescriptorIndirectCall()
5489 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32; in buildCallOperands()
5532 Ops.push_back(DAG.getConstant(SPDiff, dl, MVT::i32)); in buildCallOperands()
5549 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32)); in buildCallOperands()
5608 return DAG.getNode(CallOpc, dl, MVT::Other, Ops); in FinishCall()
5611 std::array<EVT, 2> ReturnTypes = {{MVT::Other, MVT::Glue}}; in FinishCall()
5762 MVT ArgVT = Outs[i].VT; in LowerCall_32SVR4()
5819 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32); in LowerCall_32SVR4()
5877 if (Arg.getValueType() == MVT::i1) in LowerCall_32SVR4()
5879 dl, MVT::i32, Arg); in LowerCall_32SVR4()
5884 if (Subtarget.hasSPE() && Arg.getValueType() == MVT::f64) { in LowerCall_32SVR4()
5886 SDValue SVal = DAG.getNode(PPCISD::EXTRACT_SPE, dl, MVT::i32, Arg, in LowerCall_32SVR4()
5889 SVal = DAG.getNode(PPCISD::EXTRACT_SPE, dl, MVT::i32, Arg, in LowerCall_32SVR4()
5916 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall_32SVR4()
5930 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); in LowerCall_32SVR4()
6062 case MVT::i1: in LowerCall_64SVR4()
6063 case MVT::i32: in LowerCall_64SVR4()
6064 case MVT::i64: in LowerCall_64SVR4()
6068 case MVT::v4i32: in LowerCall_64SVR4()
6069 case MVT::v8i16: in LowerCall_64SVR4()
6070 case MVT::v16i8: in LowerCall_64SVR4()
6071 case MVT::v2f64: in LowerCall_64SVR4()
6072 case MVT::v2i64: in LowerCall_64SVR4()
6073 case MVT::v1i128: in LowerCall_64SVR4()
6074 case MVT::f128: in LowerCall_64SVR4()
6078 case MVT::v4f32: in LowerCall_64SVR4()
6082 case MVT::f32: in LowerCall_64SVR4()
6083 case MVT::f64: in LowerCall_64SVR4()
6147 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64); in LowerCall_64SVR4()
6192 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) { in LowerCall_64SVR4()
6195 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); in LowerCall_64SVR4()
6219 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32); in LowerCall_64SVR4()
6309 case MVT::i1: in LowerCall_64SVR4()
6310 case MVT::i32: in LowerCall_64SVR4()
6311 case MVT::i64: in LowerCall_64SVR4()
6338 case MVT::f32: in LowerCall_64SVR4()
6339 case MVT::f64: { in LowerCall_64SVR4()
6369 if (Arg.getValueType() != MVT::f32) { in LowerCall_64SVR4()
6370 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); in LowerCall_64SVR4()
6374 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); in LowerCall_64SVR4()
6375 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal); in LowerCall_64SVR4()
6381 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]); in LowerCall_64SVR4()
6382 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); in LowerCall_64SVR4()
6385 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in LowerCall_64SVR4()
6389 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); in LowerCall_64SVR4()
6390 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal); in LowerCall_64SVR4()
6392 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal, in LowerCall_64SVR4()
6393 DAG.getConstant(32, dl, MVT::i32)); in LowerCall_64SVR4()
6408 if (Arg.getValueType() == MVT::f32 && in LowerCall_64SVR4()
6426 ArgOffset += (Arg.getValueType() == MVT::f32 && in LowerCall_64SVR4()
6433 case MVT::v4f32: in LowerCall_64SVR4()
6434 case MVT::v4i32: in LowerCall_64SVR4()
6435 case MVT::v8i16: in LowerCall_64SVR4()
6436 case MVT::v16i8: in LowerCall_64SVR4()
6437 case MVT::v2f64: in LowerCall_64SVR4()
6438 case MVT::v2i64: in LowerCall_64SVR4()
6439 case MVT::v1i128: in LowerCall_64SVR4()
6440 case MVT::f128: in LowerCall_64SVR4()
6459 DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, MachinePointerInfo()); in LowerCall_64SVR4()
6504 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall_64SVR4()
6516 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64); in LowerCall_64SVR4()
6582 static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT, in CC_AIX()
6590 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32; in CC_AIX()
6592 if (ValVT == MVT::f128) in CC_AIX()
6620 State.addLoc(CCValAssign::getMem(ValNo, MVT::INVALID_SIMPLE_VALUE_TYPE, in CC_AIX()
6633 State.addLoc(CCValAssign::getMem(ValNo, MVT::INVALID_SIMPLE_VALUE_TYPE, in CC_AIX()
6634 Offset, MVT::INVALID_SIMPLE_VALUE_TYPE, in CC_AIX()
6646 case MVT::i64: in CC_AIX()
6650 case MVT::i1: in CC_AIX()
6651 case MVT::i32: { in CC_AIX()
6664 case MVT::f32: in CC_AIX()
6665 case MVT::f64: { in CC_AIX()
6705 case MVT::v4f32: in CC_AIX()
6706 case MVT::v4i32: in CC_AIX()
6707 case MVT::v8i16: in CC_AIX()
6708 case MVT::v16i8: in CC_AIX()
6709 case MVT::v2i64: in CC_AIX()
6710 case MVT::v2f64: in CC_AIX()
6711 case MVT::v1i128: { in CC_AIX()
6810 static const TargetRegisterClass *getRegClassForSVT(MVT::SimpleValueType SVT, in getRegClassForSVT()
6814 assert((IsPPC64 || SVT != MVT::i64) && in getRegClassForSVT()
6820 case MVT::i1: in getRegClassForSVT()
6821 case MVT::i32: in getRegClassForSVT()
6822 case MVT::i64: in getRegClassForSVT()
6824 case MVT::f32: in getRegClassForSVT()
6826 case MVT::f64: in getRegClassForSVT()
6828 case MVT::v4f32: in getRegClassForSVT()
6829 case MVT::v4i32: in getRegClassForSVT()
6830 case MVT::v8i16: in getRegClassForSVT()
6831 case MVT::v16i8: in getRegClassForSVT()
6832 case MVT::v2i64: in getRegClassForSVT()
6833 case MVT::v2f64: in getRegClassForSVT()
6834 case MVT::v1i128: in getRegClassForSVT()
6841 MVT LocVT, const SDLoc &dl) { in truncateScalarIntegerArg()
6950 MVT LocVT = VA.getLocVT(); in LowerFormalArguments_AIX()
6951 MVT ValVT = VA.getValVT(); in LowerFormalArguments_AIX()
7001 MVT::SimpleValueType SVT = VA.getLocVT().SimpleTy; in LowerFormalArguments_AIX()
7033 case MVT::f32: in LowerFormalArguments_AIX()
7036 case MVT::f64: in LowerFormalArguments_AIX()
7044 case MVT::v16i8: in LowerFormalArguments_AIX()
7047 case MVT::v8i16: in LowerFormalArguments_AIX()
7050 case MVT::v4i32: in LowerFormalArguments_AIX()
7051 case MVT::v2i64: in LowerFormalArguments_AIX()
7052 case MVT::v1i128: in LowerFormalArguments_AIX()
7055 case MVT::v4f32: in LowerFormalArguments_AIX()
7056 case MVT::v2f64: in LowerFormalArguments_AIX()
7142 MVT::SimpleValueType SVT = ValVT.SimpleTy; in LowerFormalArguments_AIX()
7210 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); in LowerFormalArguments_AIX()
7272 const SDValue StackPtr = IsPPC64 ? DAG.getRegister(PPC::X1, MVT::i64) in LowerCall_AIX()
7273 : DAG.getRegister(PPC::R1, MVT::i32); in LowerCall_AIX()
7345 const MVT VT = in LowerCall_AIX()
7346 N == 1 ? MVT::i8 in LowerCall_AIX()
7347 : ((N == 2) ? MVT::i16 : (N == 4 ? MVT::i32 : MVT::i64)); in LowerCall_AIX()
7376 const MVT LocVT = VA.getLocVT(); in LowerCall_AIX()
7377 const MVT ValVT = VA.getValVT(); in LowerCall_AIX()
7464 DAG.getBitcast(MVT::getIntegerVT(ValVT.getSizeInBits()), Arg); in LowerCall_AIX()
7478 assert(Arg.getValueType() == MVT::f64 && CFlags.IsVarArg && !IsPPC64 && in LowerCall_AIX()
7481 SDValue MSWAsI64 = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgAsInt, in LowerCall_AIX()
7482 DAG.getConstant(32, dl, MVT::i8)); in LowerCall_AIX()
7484 GPR1.getLocReg(), DAG.getZExtOrTrunc(MSWAsI64, dl, MVT::i32))); in LowerCall_AIX()
7494 GPR2.getLocReg(), DAG.getZExtOrTrunc(ArgAsInt, dl, MVT::i32))); in LowerCall_AIX()
7501 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall_AIX()
7509 const MVT PtrVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in LowerCall_AIX()
7586 if (Subtarget.hasSPE() && VA.getLocVT() == MVT::f64) { in LowerReturn()
7590 DAG.getNode(PPCISD::EXTRACT_SPE, dl, MVT::i32, Arg, in LowerReturn()
7594 SVal = DAG.getNode(PPCISD::EXTRACT_SPE, dl, MVT::i32, Arg, in LowerReturn()
7611 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps); in LowerReturn()
7720 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); in LowerDYNAMIC_STACKALLOC()
7741 DAG.getVTList(MVT::i32, MVT::Other), in lowerEH_SJLJ_SETJMP()
7748 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other, in lowerEH_SJLJ_LONGJMP()
7756 assert(Op.getValueType() == MVT::i1 && in LowerLOAD()
7770 BasePtr, MVT::i8, MMO); in LowerLOAD()
7771 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD); in LowerLOAD()
7781 assert(Op.getOperand(1).getValueType() == MVT::i1 && in LowerSTORE()
7796 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO); in LowerSTORE()
7801 assert(Op.getValueType() == MVT::i1 && in LowerTRUNCATE()
7805 return DAG.getNode(PPCISD::ANDI_rec_1_GT_BIT, DL, MVT::i1, Op.getOperand(0)); in LowerTRUNCATE()
7902 if (!Subtarget.hasP9Vector() && CmpVT == MVT::f128) { in LowerSELECT_CC()
7950 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
7951 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
7953 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
7954 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1); in LowerSELECT_CC()
7956 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV); in LowerSELECT_CC()
7963 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
7964 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
7972 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
7973 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
7975 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV); in LowerSELECT_CC()
7986 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
7987 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
7989 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
7990 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1); in LowerSELECT_CC()
7992 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV); in LowerSELECT_CC()
7996 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
7997 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
8002 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
8003 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
8008 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
8009 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
8014 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
8015 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
8059 if (Src.getValueType() == MVT::f32) { in convertFPToInt()
8063 DAG.getVTList(MVT::f64, MVT::Other), {Chain, Src}, Flags); in convertFPToInt()
8066 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); in convertFPToInt()
8072 case MVT::i32: in convertFPToInt()
8076 case MVT::i64: in convertFPToInt()
8083 Conv = DAG.getNode(Opc, dl, DAG.getVTList(MVT::f64, MVT::Other), in convertFPToInt()
8086 Conv = DAG.getNode(Opc, dl, MVT::f64, Src); in convertFPToInt()
8100 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() && in LowerFP_TO_INTForReuse()
8102 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64); in LowerFP_TO_INTForReuse()
8117 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO); in LowerFP_TO_INTForReuse()
8123 if (Op.getValueType() == MVT::i32 && !i32Stack) { in LowerFP_TO_INTForReuse()
8159 if (SrcVT == MVT::f128) in LowerFP_TO_INT()
8164 if (SrcVT == MVT::ppcf128) { in LowerFP_TO_INT()
8165 if (DstVT == MVT::i32) { in LowerFP_TO_INT()
8173 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::f64, Src, in LowerFP_TO_INT()
8175 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::f64, Src, in LowerFP_TO_INT()
8182 DAG.getVTList(MVT::f64, MVT::Other), in LowerFP_TO_INT()
8185 DAG.getVTList(MVT::i32, MVT::Other), in LowerFP_TO_INT()
8188 SDValue Res = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi); in LowerFP_TO_INT()
8189 return DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Res); in LowerFP_TO_INT()
8215 DAG.getVTList(SrcVT, MVT::Other), in LowerFP_TO_INT()
8219 DAG.getVTList(DstVT, MVT::Other), in LowerFP_TO_INT()
8229 SDValue True = DAG.getNode(ISD::FSUB, dl, MVT::ppcf128, Src, Cst); in LowerFP_TO_INT()
8230 True = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, True); in LowerFP_TO_INT()
8231 True = DAG.getNode(ISD::ADD, dl, MVT::i32, True, SignMask); in LowerFP_TO_INT()
8232 SDValue False = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Src); in LowerFP_TO_INT()
8269 (Subtarget.hasFPCVT() || Op.getValueType() == MVT::i32); in canReuseLoadAddress()
8325 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, in spliceIntoChain()
8326 NewResChain, DAG.getUNDEF(MVT::Other)); in spliceIntoChain()
8379 bool IsSingle = Op.getValueType() == MVT::f32 && Subtarget.hasFPCVT(); in convertIntToFP()
8382 EVT ConvTy = IsSingle ? MVT::f32 : MVT::f64; in convertIntToFP()
8387 DAG.getVTList(ConvTy, MVT::Other), {Chain, Src}, Flags); in convertIntToFP()
8398 assert((Op.getValueType() == MVT::f32 || in LowerINT_TO_FPDirectMove()
8399 Op.getValueType() == MVT::f64) && in LowerINT_TO_FPDirectMove()
8404 bool WordInt = Src.getSimpleValueType().SimpleTy == MVT::i32; in LowerINT_TO_FPDirectMove()
8408 SDValue Mov = DAG.getNode(MovOpc, dl, MVT::f64, Src); in LowerINT_TO_FPDirectMove()
8440 assert((Op.getValueType() == MVT::v2f64 || Op.getValueType() == MVT::v4f32) && in LowerINT_TO_FPVector()
8448 bool FourEltRes = Op.getValueType() == MVT::v4f32; in LowerINT_TO_FPVector()
8453 MVT IntermediateVT = FourEltRes ? MVT::v4i32 : MVT::v2i64; in LowerINT_TO_FPVector()
8486 return DAG.getNode(Opc, dl, DAG.getVTList(Op.getValueType(), MVT::Other), in LowerINT_TO_FPVector()
8512 if (Op.getValueType() == MVT::f128) in LowerINT_TO_FP()
8516 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) in LowerINT_TO_FP()
8519 if (Src.getValueType() == MVT::i1) { in LowerINT_TO_FP()
8538 if (Src.getValueType() == MVT::i64) { in LowerINT_TO_FP()
8550 if (Op.getValueType() == MVT::f32 && in LowerINT_TO_FP()
8560 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64, in LowerINT_TO_FP()
8561 SINT, DAG.getConstant(2047, dl, MVT::i64)); in LowerINT_TO_FP()
8562 Round = DAG.getNode(ISD::ADD, dl, MVT::i64, in LowerINT_TO_FP()
8563 Round, DAG.getConstant(2047, dl, MVT::i64)); in LowerINT_TO_FP()
8564 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT); in LowerINT_TO_FP()
8565 Round = DAG.getNode(ISD::AND, dl, MVT::i64, in LowerINT_TO_FP()
8566 Round, DAG.getConstant(-2048, dl, MVT::i64)); in LowerINT_TO_FP()
8576 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64, in LowerINT_TO_FP()
8577 SINT, DAG.getConstant(53, dl, MVT::i32)); in LowerINT_TO_FP()
8578 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64, in LowerINT_TO_FP()
8579 Cond, DAG.getConstant(1, dl, MVT::i64)); in LowerINT_TO_FP()
8582 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64), in LowerINT_TO_FP()
8583 Cond, DAG.getConstant(1, dl, MVT::i64), ISD::SETUGT); in LowerINT_TO_FP()
8585 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT); in LowerINT_TO_FP()
8592 if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) { in LowerINT_TO_FP()
8593 Bits = DAG.getLoad(MVT::f64, dl, RLI.Chain, RLI.Ptr, RLI.MPI, in LowerINT_TO_FP()
8597 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) { in LowerINT_TO_FP()
8603 DAG.getVTList(MVT::f64, MVT::Other), in LowerINT_TO_FP()
8604 Ops, MVT::i32, MMO); in LowerINT_TO_FP()
8607 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) { in LowerINT_TO_FP()
8613 DAG.getVTList(MVT::f64, MVT::Other), in LowerINT_TO_FP()
8614 Ops, MVT::i32, MMO); in LowerINT_TO_FP()
8620 SINT.getOperand(0).getValueType() == MVT::i32) { in LowerINT_TO_FP()
8632 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 && in LowerINT_TO_FP()
8647 dl, DAG.getVTList(MVT::f64, MVT::Other), in LowerINT_TO_FP()
8648 Ops, MVT::i32, MMO); in LowerINT_TO_FP()
8651 Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT); in LowerINT_TO_FP()
8657 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) { in LowerINT_TO_FP()
8660 DAG.getVTList(MVT::f32, MVT::Other), in LowerINT_TO_FP()
8663 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, in LowerINT_TO_FP()
8669 assert(Src.getValueType() == MVT::i32 && in LowerINT_TO_FP()
8683 if (!(ReusingLoad = canReuseLoadAddress(Src, MVT::i32, RLI, DAG))) { in LowerINT_TO_FP()
8692 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 && in LowerINT_TO_FP()
8707 DAG.getVTList(MVT::f64, MVT::Other), Ops, in LowerINT_TO_FP()
8708 MVT::i32, MMO); in LowerINT_TO_FP()
8719 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64, Src); in LowerINT_TO_FP()
8729 MVT::f64, dl, Chain, FIdx, in LowerINT_TO_FP()
8738 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) { in LowerINT_TO_FP()
8741 DAG.getVTList(MVT::f32, MVT::Other), in LowerINT_TO_FP()
8744 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, in LowerINT_TO_FP()
8778 SDValue MFFS = DAG.getNode(PPCISD::MFFS, dl, {MVT::f64, MVT::Other}, Chain); in LowerFLT_ROUNDS_()
8782 if (isTypeLegal(MVT::i64)) { in LowerFLT_ROUNDS_()
8783 CWD = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, in LowerFLT_ROUNDS_()
8784 DAG.getNode(ISD::BITCAST, dl, MVT::i64, MFFS)); in LowerFLT_ROUNDS_()
8792 assert(hasBigEndianPartOrdering(MVT::i64, MF.getDataLayout()) && in LowerFLT_ROUNDS_()
8796 CWD = DAG.getLoad(MVT::i32, dl, Chain, Addr, MachinePointerInfo()); in LowerFLT_ROUNDS_()
8802 DAG.getNode(ISD::AND, dl, MVT::i32, in LowerFLT_ROUNDS_()
8803 CWD, DAG.getConstant(3, dl, MVT::i32)); in LowerFLT_ROUNDS_()
8805 DAG.getNode(ISD::SRL, dl, MVT::i32, in LowerFLT_ROUNDS_()
8806 DAG.getNode(ISD::AND, dl, MVT::i32, in LowerFLT_ROUNDS_()
8807 DAG.getNode(ISD::XOR, dl, MVT::i32, in LowerFLT_ROUNDS_()
8808 CWD, DAG.getConstant(3, dl, MVT::i32)), in LowerFLT_ROUNDS_()
8809 DAG.getConstant(3, dl, MVT::i32)), in LowerFLT_ROUNDS_()
8810 DAG.getConstant(1, dl, MVT::i32)); in LowerFLT_ROUNDS_()
8813 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2); in LowerFLT_ROUNDS_()
8942 static const MVT VTys[] = { // canonical VT to use for each size. in getCanonicalConstSplat()
8943 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 in getCanonicalConstSplat()
8946 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; in getCanonicalConstSplat()
8963 const SDLoc &dl, EVT DestVT = MVT::Other) { in BuildIntrinsicOp()
8964 if (DestVT == MVT::Other) DestVT = Op.getValueType(); in BuildIntrinsicOp()
8966 DAG.getConstant(IID, dl, MVT::i32), Op); in BuildIntrinsicOp()
8973 EVT DestVT = MVT::Other) { in BuildIntrinsicOp()
8974 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); in BuildIntrinsicOp()
8976 DAG.getConstant(IID, dl, MVT::i32), LHS, RHS); in BuildIntrinsicOp()
8983 EVT DestVT = MVT::Other) { in BuildIntrinsicOp()
8984 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); in BuildIntrinsicOp()
8986 DAG.getConstant(IID, dl, MVT::i32), Op0, Op1, Op2); in BuildIntrinsicOp()
8994 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS); in BuildVSLDOI()
8995 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS); in BuildVSLDOI()
9000 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops); in BuildVSLDOI()
9020 bool RightType = VecVT == MVT::v2f64 || in haveEfficientBuildVectorPattern()
9021 (HasP8Vector && VecVT == MVT::v4f32) || in haveEfficientBuildVectorPattern()
9022 (HasDirectMove && (VecVT == MVT::v2i64 || VecVT == MVT::v4i32)); in haveEfficientBuildVectorPattern()
9063 if ((Op.getValueType() != MVT::f128) || in LowerBITCAST()
9065 (Op0.getOperand(0).getValueType() != MVT::i64) || in LowerBITCAST()
9066 (Op0.getOperand(1).getValueType() != MVT::i64)) in LowerBITCAST()
9069 return DAG.getNode(PPCISD::BUILD_FP128, dl, MVT::f128, Op0.getOperand(0), in LowerBITCAST()
9137 if ((Ty == MVT::v2f64 || Ty == MVT::v4f32 || Ty == MVT::v4i32) && in isValidSplatLoad()
9146 if ((Ty == MVT::v8i16 || Ty == MVT::v16i8) && ISD::isEXTLoad(InputNode) && in isValidSplatLoad()
9150 if (Ty == MVT::v2i64) { in isValidSplatLoad()
9153 if (MemVT == MVT::i32) { in isValidSplatLoad()
9191 if ((Op->getValueType(0) == MVT::v2f64) && in LowerBUILD_VECTOR()
9194 PPCISD::XXSPLTI_SP_TO_DP, dl, MVT::v2f64, in LowerBUILD_VECTOR()
9195 DAG.getTargetConstant(APSplatBits.getZExtValue(), dl, MVT::i32)); in LowerBUILD_VECTOR()
9204 SDValue SplatNode = DAG.getUNDEF(MVT::v2i64); in LowerBUILD_VECTOR()
9208 SplatNode = DAG.getTargetConstant(0, dl, MVT::v2i64); in LowerBUILD_VECTOR()
9212 PPCISD::XXSPLTI32DX, dl, MVT::v2i64, SplatNode, in LowerBUILD_VECTOR()
9213 DAG.getTargetConstant(0, dl, MVT::i32), in LowerBUILD_VECTOR()
9214 DAG.getTargetConstant(Hi, dl, MVT::i32)); in LowerBUILD_VECTOR()
9218 DAG.getNode(PPCISD::XXSPLTI32DX, dl, MVT::v2i64, SplatNode, in LowerBUILD_VECTOR()
9219 DAG.getTargetConstant(1, dl, MVT::i32), in LowerBUILD_VECTOR()
9220 DAG.getTargetConstant(Lo, dl, MVT::i32)); in LowerBUILD_VECTOR()
9269 (Op->getValueType(0) == MVT::v2i64 && NewOpcode != PPCISD::LD_SPLAT && in LowerBUILD_VECTOR()
9292 NewOpcode, dl, DAG.getVTList(Op.getValueType(), MVT::Other), Ops, in LowerBUILD_VECTOR()
9321 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { in LowerBUILD_VECTOR()
9322 SDValue Z = DAG.getConstant(0, dl, MVT::v4i32); in LowerBUILD_VECTOR()
9366 SDValue Elt = DAG.getConstant(SextVal, dl, MVT::i32); in LowerBUILD_VECTOR()
9367 EVT VT = (SplatSize == 1 ? MVT::v16i8 : in LowerBUILD_VECTOR()
9368 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32)); in LowerBUILD_VECTOR()
9369 SDValue EltSize = DAG.getConstant(SplatSize, dl, MVT::i32); in LowerBUILD_VECTOR()
9382 SDValue OnesV = getCanonicalConstSplat(-1, 4, MVT::v4i32, DAG, dl); in LowerBUILD_VECTOR()
9389 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV); in LowerBUILD_VECTOR()
9410 SDValue Res = getCanonicalConstSplat(i, SplatSize, MVT::Other, DAG, dl); in LowerBUILD_VECTOR()
9421 SDValue Res = getCanonicalConstSplat(i, SplatSize, MVT::Other, DAG, dl); in LowerBUILD_VECTOR()
9433 SDValue Res = getCanonicalConstSplat(i, SplatSize, MVT::Other, DAG, dl); in LowerBUILD_VECTOR()
9444 SDValue T = getCanonicalConstSplat(i, SplatSize, MVT::v16i8, DAG, dl); in LowerBUILD_VECTOR()
9450 SDValue T = getCanonicalConstSplat(i, SplatSize, MVT::v16i8, DAG, dl); in LowerBUILD_VECTOR()
9456 SDValue T = getCanonicalConstSplat(i, SplatSize, MVT::v16i8, DAG, dl); in LowerBUILD_VECTOR()
9536 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS); in GeneratePerfectShuffle()
9537 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS); in GeneratePerfectShuffle()
9538 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs); in GeneratePerfectShuffle()
9634 SDValue Shl = DAG.getNode(PPCISD::VECSHL, dl, MVT::v16i8, V2, V2, in lowerToVINSERTB()
9635 DAG.getConstant(ShiftElts, dl, MVT::i32)); in lowerToVINSERTB()
9636 return DAG.getNode(PPCISD::VECINSERT, dl, MVT::v16i8, V1, Shl, in lowerToVINSERTB()
9637 DAG.getConstant(InsertAtByte, dl, MVT::i32)); in lowerToVINSERTB()
9639 return DAG.getNode(PPCISD::VECINSERT, dl, MVT::v16i8, V1, V2, in lowerToVINSERTB()
9640 DAG.getConstant(InsertAtByte, dl, MVT::i32)); in lowerToVINSERTB()
9739 SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); in lowerToVINSERTH()
9742 SDValue Shl = DAG.getNode(PPCISD::VECSHL, dl, MVT::v16i8, V2, V2, in lowerToVINSERTH()
9743 DAG.getConstant(2 * ShiftElts, dl, MVT::i32)); in lowerToVINSERTH()
9744 SDValue Conv2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, Shl); in lowerToVINSERTH()
9745 SDValue Ins = DAG.getNode(PPCISD::VECINSERT, dl, MVT::v8i16, Conv1, Conv2, in lowerToVINSERTH()
9746 DAG.getConstant(InsertAtByte, dl, MVT::i32)); in lowerToVINSERTH()
9747 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Ins); in lowerToVINSERTH()
9749 SDValue Conv2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2); in lowerToVINSERTH()
9750 SDValue Ins = DAG.getNode(PPCISD::VECINSERT, dl, MVT::v8i16, Conv1, Conv2, in lowerToVINSERTH()
9751 DAG.getConstant(InsertAtByte, dl, MVT::i32)); in lowerToVINSERTH()
9752 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Ins); in lowerToVINSERTH()
9806 Index = DAG.getTargetConstant(IsLE ? 0 : 1, DL, MVT::i32); in lowerToXXSPLTI32DX()
9810 Index = DAG.getTargetConstant(IsLE ? 1 : 0, DL, MVT::i32); in lowerToXXSPLTI32DX()
9821 PPCISD::XXSPLTI32DX, DL, MVT::v2i64, DAG.getBitcast(MVT::v2i64, LHS), in lowerToXXSPLTI32DX()
9822 Index, DAG.getTargetConstant(SplatVal, DL, MVT::i32)); in lowerToXXSPLTI32DX()
9823 return DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, SplatNode); in lowerToXXSPLTI32DX()
9832 assert(Op.getValueType() == MVT::v1i128 && in LowerROTL()
9843 DAG.getVectorShuffle(MVT::v16i8, dl, DAG.getBitcast(MVT::v16i8, N0), in LowerROTL()
9844 DAG.getUNDEF(MVT::v16i8), Mask)) in LowerROTL()
9845 return DAG.getNode(ISD::BITCAST, dl, MVT::v1i128, Shuffle); in LowerROTL()
9847 SDValue ArgVal = DAG.getBitcast(MVT::i128, N0); in LowerROTL()
9848 SDValue SHLOp = DAG.getNode(ISD::SHL, dl, MVT::i128, ArgVal, in LowerROTL()
9849 DAG.getConstant(SHLAmt, dl, MVT::i32)); in LowerROTL()
9850 SDValue SRLOp = DAG.getNode(ISD::SRL, dl, MVT::i128, ArgVal, in LowerROTL()
9851 DAG.getConstant(128 - SHLAmt, dl, MVT::i32)); in LowerROTL()
9852 SDValue OROp = DAG.getNode(ISD::OR, dl, MVT::i128, SHLOp, SRLOp); in LowerROTL()
9853 return DAG.getNode(ISD::BITCAST, dl, MVT::v1i128, OROp); in LowerROTL()
9931 DAG.getVTList(IsFourByte ? MVT::v4i32 : MVT::v2i64, MVT::Other); in LowerVECTOR_SHUFFLE()
9943 if (VT == MVT::v2i64 || VT == MVT::v2f64) in LowerVECTOR_SHUFFLE()
9951 SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1); in LowerVECTOR_SHUFFLE()
9952 SDValue Conv2 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V2); in LowerVECTOR_SHUFFLE()
9954 SDValue Shl = DAG.getNode(PPCISD::VECSHL, dl, MVT::v4i32, Conv2, Conv2, in LowerVECTOR_SHUFFLE()
9955 DAG.getConstant(ShiftElts, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
9956 SDValue Ins = DAG.getNode(PPCISD::VECINSERT, dl, MVT::v4i32, Conv1, Shl, in LowerVECTOR_SHUFFLE()
9957 DAG.getConstant(InsertAtByte, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
9958 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Ins); in LowerVECTOR_SHUFFLE()
9960 SDValue Ins = DAG.getNode(PPCISD::VECINSERT, dl, MVT::v4i32, Conv1, Conv2, in LowerVECTOR_SHUFFLE()
9961 DAG.getConstant(InsertAtByte, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
9962 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Ins); in LowerVECTOR_SHUFFLE()
9984 SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1); in LowerVECTOR_SHUFFLE()
9986 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V2.isUndef() ? V1 : V2); in LowerVECTOR_SHUFFLE()
9988 SDValue Shl = DAG.getNode(PPCISD::VECSHL, dl, MVT::v4i32, Conv1, Conv2, in LowerVECTOR_SHUFFLE()
9989 DAG.getConstant(ShiftElts, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
9990 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Shl); in LowerVECTOR_SHUFFLE()
9997 SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1); in LowerVECTOR_SHUFFLE()
9999 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2.isUndef() ? V1 : V2); in LowerVECTOR_SHUFFLE()
10001 SDValue PermDI = DAG.getNode(PPCISD::XXPERMDI, dl, MVT::v2i64, Conv1, Conv2, in LowerVECTOR_SHUFFLE()
10002 DAG.getConstant(ShiftElts, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
10003 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, PermDI); in LowerVECTOR_SHUFFLE()
10008 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); in LowerVECTOR_SHUFFLE()
10009 SDValue ReveHWord = DAG.getNode(ISD::BSWAP, dl, MVT::v8i16, Conv); in LowerVECTOR_SHUFFLE()
10010 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, ReveHWord); in LowerVECTOR_SHUFFLE()
10012 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1); in LowerVECTOR_SHUFFLE()
10013 SDValue ReveWord = DAG.getNode(ISD::BSWAP, dl, MVT::v4i32, Conv); in LowerVECTOR_SHUFFLE()
10014 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, ReveWord); in LowerVECTOR_SHUFFLE()
10016 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1); in LowerVECTOR_SHUFFLE()
10017 SDValue ReveDWord = DAG.getNode(ISD::BSWAP, dl, MVT::v2i64, Conv); in LowerVECTOR_SHUFFLE()
10018 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, ReveDWord); in LowerVECTOR_SHUFFLE()
10020 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v1i128, V1); in LowerVECTOR_SHUFFLE()
10021 SDValue ReveQWord = DAG.getNode(ISD::BSWAP, dl, MVT::v1i128, Conv); in LowerVECTOR_SHUFFLE()
10022 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, ReveQWord); in LowerVECTOR_SHUFFLE()
10030 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1); in LowerVECTOR_SHUFFLE()
10031 SDValue Splat = DAG.getNode(PPCISD::XXSPLT, dl, MVT::v4i32, Conv, in LowerVECTOR_SHUFFLE()
10032 DAG.getConstant(SplatIdx, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
10033 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Splat); in LowerVECTOR_SHUFFLE()
10038 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); in LowerVECTOR_SHUFFLE()
10039 SDValue Swap = DAG.getNode(PPCISD::SWAP_NO_CHAIN, dl, MVT::v2f64, Conv); in LowerVECTOR_SHUFFLE()
10040 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Swap); in LowerVECTOR_SHUFFLE()
10167 dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
10170 MVT::i32)); in LowerVECTOR_SHUFFLE()
10174 SDValue VPermMask = DAG.getBuildVector(MVT::v16i8, dl, ResultMask); in LowerVECTOR_SHUFFLE()
10488 return DAG.getRegister(PPC::X13, MVT::i64); in LowerINTRINSIC_WO_CHAIN()
10489 return DAG.getRegister(PPC::R2, MVT::i32); in LowerINTRINSIC_WO_CHAIN()
10497 WideVec = DAG.getNode(PPCISD::XXMFACC, dl, MVT::v512i1, WideVec); in LowerINTRINSIC_WO_CHAIN()
10502 PPCISD::EXTRACT_VSX_REG, dl, MVT::v16i8, WideVec, in LowerINTRINSIC_WO_CHAIN()
10515 return DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::f64, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
10541 PPC::SELECT_CC_I4, dl, MVT::i32, in LowerINTRINSIC_WO_CHAIN()
10542 {SDValue(DAG.getMachineNode(PPC::XSCMPEXPDP, dl, MVT::i32, in LowerINTRINSIC_WO_CHAIN()
10545 DAG.getConstant(1, dl, MVT::i32), DAG.getConstant(0, dl, MVT::i32), in LowerINTRINSIC_WO_CHAIN()
10546 DAG.getTargetConstant(Pred, dl, MVT::i32)}), in LowerINTRINSIC_WO_CHAIN()
10556 PPC::SELECT_CC_I4, dl, MVT::i32, in LowerINTRINSIC_WO_CHAIN()
10557 {SDValue(DAG.getMachineNode(CmprOpc, dl, MVT::i32, Op.getOperand(2), in LowerINTRINSIC_WO_CHAIN()
10560 DAG.getConstant(1, dl, MVT::i32), DAG.getConstant(0, dl, MVT::i32), in LowerINTRINSIC_WO_CHAIN()
10561 DAG.getTargetConstant(PPC::PRED_EQ, dl, MVT::i32)}), in LowerINTRINSIC_WO_CHAIN()
10566 if (!Subtarget.hasVSX() || (!Subtarget.hasFloat128() && VT == MVT::f128)) in LowerINTRINSIC_WO_CHAIN()
10623 DAG.getConstant(CompareOpc, dl, MVT::i32)); in LowerINTRINSIC_WO_CHAIN()
10631 DAG.getConstant(CompareOpc, dl, MVT::i32) in LowerINTRINSIC_WO_CHAIN()
10633 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue }; in LowerINTRINSIC_WO_CHAIN()
10638 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32, in LowerINTRINSIC_WO_CHAIN()
10639 DAG.getRegister(PPC::CR6, MVT::i32), in LowerINTRINSIC_WO_CHAIN()
10662 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags, in LowerINTRINSIC_WO_CHAIN()
10663 DAG.getConstant(8 - (3 - BitNo), dl, MVT::i32)); in LowerINTRINSIC_WO_CHAIN()
10665 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags, in LowerINTRINSIC_WO_CHAIN()
10666 DAG.getConstant(1, dl, MVT::i32)); in LowerINTRINSIC_WO_CHAIN()
10670 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags, in LowerINTRINSIC_WO_CHAIN()
10671 DAG.getConstant(1, dl, MVT::i32)); in LowerINTRINSIC_WO_CHAIN()
10687 if (Ty == MVT::i128) { in LowerINTRINSIC_VOID()
10690 Val = DAG.getNode(ISD::TRUNCATE, DL, MVT::i64, Val); in LowerINTRINSIC_VOID()
10693 DAG.getMachineNode(PPC::CFENCE8, DL, MVT::Other, in LowerINTRINSIC_VOID()
10694 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Val), in LowerINTRINSIC_VOID()
10710 Op = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, Op.getOperand(0), in LowerBSWAP()
10713 Op = DAG.getNode(ISD::BSWAP, dl, MVT::v2i64, Op); in LowerBSWAP()
10718 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Op, in LowerBSWAP()
10719 DAG.getTargetConstant(VectorIndex, dl, MVT::i32)); in LowerBSWAP()
10744 DAG.getNode(ISD::AND, dl, MVT::i32, CmpOp, in LowerATOMIC_CMP_SWAP()
10745 DAG.getConstant(MaskVal, dl, MVT::i32)); in LowerATOMIC_CMP_SWAP()
10753 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::Other); in LowerATOMIC_CMP_SWAP()
10755 (MemVT == MVT::i8) ? PPCISD::ATOMIC_CMP_SWAP_8 : PPCISD::ATOMIC_CMP_SWAP_16; in LowerATOMIC_CMP_SWAP()
10763 assert(MemVT.getSimpleVT() == MVT::i128 && in LowerATOMIC_LOAD_STORE()
10771 SDVTList Tys = DAG.getVTList(MVT::i64, MVT::i64, MVT::Other); in LowerATOMIC_LOAD_STORE()
10774 DAG.getConstant(Intrinsic::ppc_atomic_load_i128, dl, MVT::i32)}; in LowerATOMIC_LOAD_STORE()
10779 SDValue ValLo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i128, LoadedVal); in LowerATOMIC_LOAD_STORE()
10781 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i128, LoadedVal.getValue(1)); in LowerATOMIC_LOAD_STORE()
10782 ValHi = DAG.getNode(ISD::SHL, dl, MVT::i128, ValHi, in LowerATOMIC_LOAD_STORE()
10783 DAG.getConstant(64, dl, MVT::i32)); in LowerATOMIC_LOAD_STORE()
10785 DAG.getNode(ISD::OR, dl, {MVT::i128, MVT::Other}, {ValLo, ValHi}); in LowerATOMIC_LOAD_STORE()
10786 return DAG.getNode(ISD::MERGE_VALUES, dl, {MVT::i128, MVT::Other}, in LowerATOMIC_LOAD_STORE()
10792 SDVTList Tys = DAG.getVTList(MVT::Other); in LowerATOMIC_LOAD_STORE()
10795 DAG.getConstant(Intrinsic::ppc_atomic_store_i128, dl, MVT::i32)}; in LowerATOMIC_LOAD_STORE()
10797 SDValue ValLo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i64, Val); in LowerATOMIC_LOAD_STORE()
10798 SDValue ValHi = DAG.getNode(ISD::SRL, dl, MVT::i128, Val, in LowerATOMIC_LOAD_STORE()
10799 DAG.getConstant(64, dl, MVT::i32)); in LowerATOMIC_LOAD_STORE()
10800 ValHi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i64, ValHi); in LowerATOMIC_LOAD_STORE()
10840 if (VT == MVT::v2f64 && C) in LowerINSERT_VECTOR_ELT()
10852 if ((VT == MVT::v4f32) && (V2.getValueType() == MVT::f32) && in LowerINSERT_VECTOR_ELT()
10854 SDValue BitcastVector = DAG.getBitcast(MVT::v4i32, V1); in LowerINSERT_VECTOR_ELT()
10855 SDValue BitcastLoad = DAG.getBitcast(MVT::i32, V2); in LowerINSERT_VECTOR_ELT()
10857 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v4i32, BitcastVector, in LowerINSERT_VECTOR_ELT()
10859 return DAG.getBitcast(MVT::v4f32, InsVecElt); in LowerINSERT_VECTOR_ELT()
10864 if ((VT == MVT::v2i64 || VT == MVT::v2f64) && !Subtarget.isPPC64()) in LowerINSERT_VECTOR_ELT()
10868 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 || in LowerINSERT_VECTOR_ELT()
10869 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64) in LowerINSERT_VECTOR_ELT()
10879 if (VT == MVT::v8i16 || VT == MVT::v16i8) { in LowerINSERT_VECTOR_ELT()
10888 DAG.getConstant(InsertAtByte, dl, MVT::i32)); in LowerINSERT_VECTOR_ELT()
10901 if (VT != MVT::v256i1 && VT != MVT::v512i1) in LowerVectorLoad()
10907 assert((VT != MVT::v512i1 || Subtarget.hasMMA()) && in LowerVectorLoad()
10909 assert((VT != MVT::v256i1 || Subtarget.pairedVectorMemops()) && in LowerVectorLoad()
10917 DAG.getLoad(MVT::v16i8, dl, LoadChain, BasePtr, in LowerVectorLoad()
10930 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains); in LowerVectorLoad()
10932 DAG.getNode(VT == MVT::v512i1 ? PPCISD::ACC_BUILD : PPCISD::PAIR_BUILD, in LowerVectorLoad()
10947 if (StoreVT != MVT::v256i1 && StoreVT != MVT::v512i1) in LowerVectorStore()
10953 assert((StoreVT != MVT::v512i1 || Subtarget.hasMMA()) && in LowerVectorStore()
10955 assert((StoreVT != MVT::v256i1 || Subtarget.pairedVectorMemops()) && in LowerVectorStore()
10960 if (StoreVT == MVT::v512i1) { in LowerVectorStore()
10961 Value = DAG.getNode(PPCISD::XXMFACC, dl, MVT::v512i1, Value); in LowerVectorStore()
10966 SDValue Elt = DAG.getNode(PPCISD::EXTRACT_VSX_REG, dl, MVT::v16i8, Value, in LowerVectorStore()
10983 if (Op.getValueType() == MVT::v4i32) { in LowerMUL()
10986 SDValue Zero = getCanonicalConstSplat(0, 1, MVT::v4i32, DAG, dl); in LowerMUL()
10988 SDValue Neg16 = getCanonicalConstSplat(-16, 4, MVT::v4i32, DAG, dl); in LowerMUL()
10993 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS); in LowerMUL()
10994 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS); in LowerMUL()
10995 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap); in LowerMUL()
11000 LHS, RHS, DAG, dl, MVT::v4i32); in LowerMUL()
11003 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32); in LowerMUL()
11007 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd); in LowerMUL()
11008 } else if (Op.getValueType() == MVT::v16i8) { in LowerMUL()
11014 LHS, RHS, DAG, dl, MVT::v8i16); in LowerMUL()
11015 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts); in LowerMUL()
11019 LHS, RHS, DAG, dl, MVT::v8i16); in LowerMUL()
11020 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts); in LowerMUL()
11037 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops); in LowerMUL()
11039 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops); in LowerMUL()
11047 if (Op.getOperand(IsStrict ? 1 : 0).getValueType() == MVT::f128 && in LowerFP_ROUND()
11062 if (Op.getValueType() != MVT::v2f64 || in LowerFP_EXTEND()
11063 Op.getOperand(0).getValueType() != MVT::v2f32) in LowerFP_EXTEND()
11077 if (Op0.getOperand(0).getValueType() != MVT::v4f32) in LowerFP_EXTEND()
11093 return DAG.getNode(PPCISD::FP_EXTEND_HALF, dl, MVT::v2f64, in LowerFP_EXTEND()
11094 Op0.getOperand(0), DAG.getConstant(DWord, dl, MVT::i32)); in LowerFP_EXTEND()
11109 PPCISD::LD_VSX_LH, dl, DAG.getVTList(MVT::v4f32, MVT::Other), LoadOps, in LowerFP_EXTEND()
11113 DAG.getNode(Op0.getOpcode(), SDLoc(Op0), MVT::v4f32, NewLoad[0], in LowerFP_EXTEND()
11115 return DAG.getNode(PPCISD::FP_EXTEND_HALF, dl, MVT::v2f64, NewOp, in LowerFP_EXTEND()
11116 DAG.getConstant(0, dl, MVT::i32)); in LowerFP_EXTEND()
11122 PPCISD::LD_VSX_LH, dl, DAG.getVTList(MVT::v4f32, MVT::Other), LoadOps, in LowerFP_EXTEND()
11124 return DAG.getNode(PPCISD::FP_EXTEND_HALF, dl, MVT::v2f64, NewLd, in LowerFP_EXTEND()
11125 DAG.getConstant(0, dl, MVT::i32)); in LowerFP_EXTEND()
11239 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); in ReplaceNodeResults()
11243 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, RTB, RTB.getValue(1))); in ReplaceNodeResults()
11252 assert(N->getValueType(0) == MVT::i1 && in ReplaceNodeResults()
11256 SDVTList VTs = DAG.getVTList(SVT, MVT::Other); in ReplaceNodeResults()
11260 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewInt)); in ReplaceNodeResults()
11267 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128, in ReplaceNodeResults()
11285 if (VT == MVT::i64) { in ReplaceNodeResults()
11299 MVT::ppcf128) in ReplaceNodeResults()
11774 assert(TRI->isTypeLegalForClass(*RC, MVT::i32) && "Invalid destination!"); in emitEHSjLjSetJmp()
11778 MVT PVT = getPointerTy(MF->getDataLayout()); in emitEHSjLjSetJmp()
11779 assert((PVT == MVT::i64 || PVT == MVT::i32) && in emitEHSjLjSetJmp()
11910 MVT PVT = getPointerTy(MF->getDataLayout()); in emitEHSjLjLongJmp()
11911 assert((PVT == MVT::i64 || PVT == MVT::i32) && in emitEHSjLjLongJmp()
11915 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass; in emitEHSjLjLongJmp()
11918 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31; in emitEHSjLjLongJmp()
11919 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1; in emitEHSjLjLongJmp()
11921 (PVT == MVT::i64) in emitEHSjLjLongJmp()
11938 if (PVT == MVT::i64) { in emitEHSjLjLongJmp()
11950 if (PVT == MVT::i64) { in emitEHSjLjLongJmp()
11962 if (PVT == MVT::i64) { in emitEHSjLjLongJmp()
11974 if (PVT == MVT::i64) { in emitEHSjLjLongJmp()
11986 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) { in emitEHSjLjLongJmp()
11996 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp); in emitEHSjLjLongJmp()
11997 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR)); in emitEHSjLjLongJmp()
13036 if (VT.getScalarType() == MVT::f64) in getEstimateRefinementSteps()
13045 if (!isTypeLegal(MVT::i1) || in getSqrtInputTest()
13046 (VT != MVT::f64 && in getSqrtInputTest()
13047 ((VT != MVT::v2f64 && VT != MVT::v4f32) || !Subtarget.hasVSX()))) in getSqrtInputTest()
13052 SDValue FTSQRT = DAG.getNode(PPCISD::FTSQRT, DL, MVT::i32, Op); in getSqrtInputTest()
13064 SDValue SRIdxVal = DAG.getTargetConstant(PPC::sub_eq, DL, MVT::i32); in getSqrtInputTest()
13065 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::i1, in getSqrtInputTest()
13075 if (VT != MVT::f64 && in getSqrtResultForDenormInput()
13076 ((VT != MVT::v2f64 && VT != MVT::v4f32) || !Subtarget.hasVSX())) in getSqrtResultForDenormInput()
13087 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) || in getSqrtEstimate()
13088 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) || in getSqrtEstimate()
13089 (VT == MVT::v4f32 && Subtarget.hasAltivec()) || in getSqrtEstimate()
13090 (VT == MVT::v2f64 && Subtarget.hasVSX())) { in getSqrtEstimate()
13106 if ((VT == MVT::f32 && Subtarget.hasFRES()) || in getRecipEstimate()
13107 (VT == MVT::f64 && Subtarget.hasFRE()) || in getRecipEstimate()
13108 (VT == MVT::v4f32 && Subtarget.hasAltivec()) || in getRecipEstimate()
13109 (VT == MVT::v2f64 && Subtarget.hasVSX())) { in getRecipEstimate()
13211 VT = MVT::v4i32; in isConsecutiveLS()
13215 VT = MVT::v2f64; in isConsecutiveLS()
13218 VT = MVT::i8; in isConsecutiveLS()
13221 VT = MVT::i16; in isConsecutiveLS()
13224 VT = MVT::i32; in isConsecutiveLS()
13238 VT = MVT::v4i32; in isConsecutiveLS()
13241 VT = MVT::v2f64; in isConsecutiveLS()
13244 VT = MVT::v4i32; in isConsecutiveLS()
13247 VT = MVT::v2f64; in isConsecutiveLS()
13250 VT = MVT::i8; in isConsecutiveLS()
13253 VT = MVT::i16; in isConsecutiveLS()
13256 VT = MVT::i32; in isConsecutiveLS()
13344 auto Op0 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, N->getOperand(0), in generateEquivalentSub()
13345 DAG.getConstant(Size, DL, MVT::i32)); in generateEquivalentSub()
13346 auto Op1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, N->getOperand(1), in generateEquivalentSub()
13347 DAG.getConstant(Size, DL, MVT::i32)); in generateEquivalentSub()
13354 auto SubNode = DAG.getNode(ISD::SUB, DL, MVT::i64, Op0, Op1); in generateEquivalentSub()
13358 auto Shifted = DAG.getNode(ISD::SRL, DL, MVT::i64, SubNode, in generateEquivalentSub()
13359 DAG.getConstant(Size - 1, DL, MVT::i32)); in generateEquivalentSub()
13364 Final = DAG.getNode(ISD::XOR, DL, MVT::i64, Shifted, in generateEquivalentSub()
13365 DAG.getConstant(1, DL, MVT::i64)); in generateEquivalentSub()
13367 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Final); in generateEquivalentSub()
13426 N->getValueType(0) != MVT::i1) in DAGCombineTruncBoolExt()
13429 if (N->getOperand(0).getValueType() != MVT::i32 && in DAGCombineTruncBoolExt()
13430 N->getOperand(0).getValueType() != MVT::i64) in DAGCombineTruncBoolExt()
13505 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) || in DAGCombineTruncBoolExt()
13535 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) || in DAGCombineTruncBoolExt()
13632 PromOp.getOperand(0).getValueType() != MVT::i1) { in DAGCombineTruncBoolExt()
13640 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue); in DAGCombineTruncBoolExt()
13654 PromOp.getOperand(C).getValueType() != MVT::i1) || in DAGCombineTruncBoolExt()
13656 PromOp.getOperand(C+1).getValueType() != MVT::i1)) { in DAGCombineTruncBoolExt()
13671 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]); in DAGCombineTruncBoolExt()
13674 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops)); in DAGCombineTruncBoolExt()
13705 if (N->getValueType(0) != MVT::i32 && in DAGCombineExtBoolTrunc()
13706 N->getValueType(0) != MVT::i64) in DAGCombineExtBoolTrunc()
13709 if (!((N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) || in DAGCombineExtBoolTrunc()
13710 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64()))) in DAGCombineExtBoolTrunc()
13997 Op.getValueType() == MVT::f64; in isFPExtLoad()
14067 MVT::f32, In.getOperand(0), in combineElementTruncationToVectorTruncation()
14082 EVT NewVT = TargetVT == MVT::v2i64 ? MVT::v2f64 : MVT::v4f32; in combineElementTruncationToVectorTruncation()
14326 if (N->getValueType(0) != MVT::v1i128) in combineBVZEXTLOAD()
14340 bool ValidLDType = MemoryType == MVT::i8 || MemoryType == MVT::i16 || in combineBVZEXTLOAD()
14341 MemoryType == MVT::i32 || MemoryType == MVT::i64; in combineBVZEXTLOAD()
14354 DAG.getVTList(MVT::v1i128, MVT::Other), in combineBVZEXTLOAD()
14404 if (N->getValueType(0) != MVT::v2f64) in DAGCombineBuildVector()
14428 if (Ext1.getOperand(0).getValueType() != MVT::v4i32 || in DAGCombineBuildVector()
14445 return DAG.getNode(NodeType, dl, MVT::v2f64, in DAGCombineBuildVector()
14464 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) in combineFPToIntToFP()
14468 if (Op.getOperand(0).getValueType().getSimpleVT() <= MVT(MVT::i1) || in combineFPToIntToFP()
14469 Op.getOperand(0).getValueType().getSimpleVT() > MVT(MVT::i64)) in combineFPToIntToFP()
14474 (FirstOperand.getValueType() == MVT::i8 || in combineFPToIntToFP()
14475 FirstOperand.getValueType() == MVT::i16); in combineFPToIntToFP()
14478 bool DstDouble = Op.getValueType() == MVT::f64; in combineFPToIntToFP()
14483 DAG.getIntPtrConstant(FirstOperand.getValueType() == MVT::i8 ? 1 : 2, in combineFPToIntToFP()
14488 DAG.getVTList(MVT::f64, MVT::Other), in combineFPToIntToFP()
14489 Ops, MVT::i8, LDN->getMemOperand()); in combineFPToIntToFP()
14494 SDValue Ext = DAG.getNode(PPCISD::VEXTS, dl, MVT::f64, ExtOps); in combineFPToIntToFP()
14495 return DAG.getNode(ConvOp, dl, DstDouble ? MVT::f64 : MVT::f32, Ext); in combineFPToIntToFP()
14497 return DAG.getNode(ConvOp, dl, DstDouble ? MVT::f64 : MVT::f32, Ld); in combineFPToIntToFP()
14505 if (Op.getOperand(0).getValueType() == MVT::i32) in combineFPToIntToFP()
14513 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) in combineFPToIntToFP()
14518 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) in combineFPToIntToFP()
14519 ? MVT::f32 in combineFPToIntToFP()
14520 : MVT::f64; in combineFPToIntToFP()
14528 if (Src.getValueType() == MVT::f32) { in combineFPToIntToFP()
14529 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); in combineFPToIntToFP()
14531 } else if (Src.getValueType() != MVT::f64) { in combineFPToIntToFP()
14540 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src); in combineFPToIntToFP()
14543 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) { in combineFPToIntToFP()
14545 MVT::f32, FP, DAG.getIntPtrConstant(0, dl)); in combineFPToIntToFP()
14596 MVT VecTy = N->getValueType(0).getSimpleVT(); in expandVSXLoadForLE()
14600 DAG.getVTList(MVT::v2f64, MVT::Other), in expandVSXLoadForLE()
14601 LoadOps, MVT::v2f64, MMO); in expandVSXLoadForLE()
14606 PPCISD::XXSWAPD, dl, DAG.getVTList(MVT::v2f64, MVT::Other), Chain, Load); in expandVSXLoadForLE()
14610 if (VecTy != MVT::v2f64) { in expandVSXLoadForLE()
14614 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(VecTy, MVT::Other), in expandVSXLoadForLE()
14665 MVT VecTy = Src.getValueType().getSimpleVT(); in expandVSXStoreForLE()
14668 if (VecTy != MVT::v2f64) { in expandVSXStoreForLE()
14669 Src = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Src); in expandVSXStoreForLE()
14674 DAG.getVTList(MVT::v2f64, MVT::Other), Chain, Src); in expandVSXStoreForLE()
14679 DAG.getVTList(MVT::Other), in expandVSXStoreForLE()
14705 (Op1VT == MVT::i32 || Op1VT == MVT::i64 || in combineStoreFPToInt()
14706 (Subtarget.hasP9Vector() && (Op1VT == MVT::i16 || Op1VT == MVT::i8))); in combineStoreFPToInt()
14708 if (ResVT == MVT::f128 && !Subtarget.hasP9Vector()) in combineStoreFPToInt()
14711 if (ResVT == MVT::ppcf128 || !Subtarget.hasP8Vector() || in combineStoreFPToInt()
14717 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); in combineStoreFPToInt()
14727 dl, ResVT == MVT::f128 ? MVT::f128 : MVT::f64, Val); in combineStoreFPToInt()
14737 DAG.getVTList(MVT::Other), Ops, in combineStoreFPToInt()
15078 PPCISD::LOAD_VEC_BE, dl, DAG.getVTList(VT, MVT::Other), LoadOps, in combineVReverseMemOP()
15093 PPCISD::STORE_VEC_BE, dl, DAG.getVTList(MVT::Other), StoreOps, in combineVReverseMemOP()
15176 (Op1VT == MVT::i32 || Op1VT == MVT::i16 || in PerformDAGCombine()
15177 (Subtarget.hasLDBRX() && Subtarget.isPPC64() && Op1VT == MVT::i64))) { in PerformDAGCombine()
15187 if (BSwapOp.getValueType() == MVT::i16) in PerformDAGCombine()
15188 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp); in PerformDAGCombine()
15195 DAG.getConstant(Shift, dl, MVT::i32)); in PerformDAGCombine()
15197 if (Op1VT == MVT::i64) in PerformDAGCombine()
15198 BSwapOp = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BSwapOp); in PerformDAGCombine()
15205 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other), in PerformDAGCombine()
15213 isa<ConstantSDNode>(N->getOperand(1)) && Op1VT == MVT::i32) { in PerformDAGCombine()
15218 SDValue Const64 = DAG.getConstant(Val64, dl, MVT::i64); in PerformDAGCombine()
15232 MVT StoreVT = Op1VT.getSimpleVT(); in PerformDAGCombine()
15234 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 || in PerformDAGCombine()
15235 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32)) in PerformDAGCombine()
15247 MVT LoadVT = VT.getSimpleVT(); in PerformDAGCombine()
15249 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 || in PerformDAGCombine()
15250 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32)) in PerformDAGCombine()
15262 if (VT != MVT::i64) in PerformDAGCombine()
15289 Trunc->getValueType(0) != MVT::i32 || in PerformDAGCombine()
15300 Trunc2->getValueType(0) != MVT::i32 || in PerformDAGCombine()
15308 Bitcast->getValueType(0) != MVT::f32) in PerformDAGCombine()
15311 Bitcast2->getValueType(0) != MVT::f32) in PerformDAGCombine()
15331 SDValue FloatLoad = DAG.getLoad(MVT::f32, dl, LD->getChain(), BasePtr, in PerformDAGCombine()
15338 MVT::f32, dl, SDValue(FloatLoad.getNode(), 1), AddPtr, in PerformDAGCombine()
15366 (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 || in PerformDAGCombine()
15367 VT == MVT::v4f32))) && in PerformDAGCombine()
15399 MVT PermCntlTy, PermTy, LDTy; in PerformDAGCombine()
15404 PermCntlTy = MVT::v16i8; in PerformDAGCombine()
15405 PermTy = MVT::v4i32; in PerformDAGCombine()
15406 LDTy = MVT::v4i32; in PerformDAGCombine()
15427 DAG.getVTList(PermTy, MVT::Other), in PerformDAGCombine()
15457 DAG.getVTList(PermTy, MVT::Other), in PerformDAGCombine()
15460 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, in PerformDAGCombine()
15480 DAG.getTargetConstant(1, dl, MVT::i64)); in PerformDAGCombine()
15547 if ((V1.getSimpleValueType() == MVT::v4i32 || in PerformDAGCombine()
15548 V1.getSimpleValueType() == MVT::v8i16 || in PerformDAGCombine()
15549 V1.getSimpleValueType() == MVT::v16i8) && in PerformDAGCombine()
15605 Subtarget.isPPC64() && N->getValueType(0) == MVT::i64; in PerformDAGCombine()
15609 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 || in PerformDAGCombine()
15621 DAG.getVTList(N->getValueType(0) == MVT::i64 ? in PerformDAGCombine()
15622 MVT::i64 : MVT::i32, MVT::Other), in PerformDAGCombine()
15627 if (N->getValueType(0) == MVT::i16) in PerformDAGCombine()
15628 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad); in PerformDAGCombine()
15652 SDValue Lo = DAG.getLoad(MVT::i32, dl, LD->getChain(), BasePtr, in PerformDAGCombine()
15654 Lo = DAG.getNode(ISD::BSWAP, dl, MVT::i32, Lo); in PerformDAGCombine()
15659 SDValue Hi = DAG.getLoad(MVT::i32, dl, LD->getChain(), BasePtr, NewMMO); in PerformDAGCombine()
15660 Hi = DAG.getNode(ISD::BSWAP, dl, MVT::i32, Hi); in PerformDAGCombine()
15663 Res = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Hi, Lo); in PerformDAGCombine()
15665 Res = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in PerformDAGCombine()
15667 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, in PerformDAGCombine()
15736 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other, in PerformDAGCombine()
15776 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other, in PerformDAGCombine()
15795 return DAG.getNode(ISD::BR, dl, MVT::Other, in PerformDAGCombine()
15805 DAG.getConstant(CompareOpc, dl, MVT::i32) in PerformDAGCombine()
15807 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue }; in PerformDAGCombine()
15828 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0), in PerformDAGCombine()
15829 DAG.getConstant(CompOpc, dl, MVT::i32), in PerformDAGCombine()
15830 DAG.getRegister(PPC::CR6, MVT::i32), in PerformDAGCombine()
15852 if (VT == MVT::i64 && !Subtarget.isPPC64()) in BuildSDIVPow2()
15854 if ((VT != MVT::i32 && VT != MVT::i64) || in BuildSDIVPow2()
15890 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16) in computeKnownBitsForTargetNode()
16078 MVT VT) const { in getRegForInlineAsmConstraint()
16083 if (VT == MVT::i64 && Subtarget.isPPC64()) in getRegForInlineAsmConstraint()
16087 if (VT == MVT::i64 && Subtarget.isPPC64()) in getRegForInlineAsmConstraint()
16096 if (VT == MVT::f32 || VT == MVT::i32) in getRegForInlineAsmConstraint()
16098 if (VT == MVT::f64 || VT == MVT::i64) in getRegForInlineAsmConstraint()
16101 if (VT == MVT::f32 || VT == MVT::i32) in getRegForInlineAsmConstraint()
16103 if (VT == MVT::f64 || VT == MVT::i64) in getRegForInlineAsmConstraint()
16127 if (VT == MVT::f32 && Subtarget.hasP8Vector()) in getRegForInlineAsmConstraint()
16131 if (VT == MVT::f32 && Subtarget.hasP8Vector()) in getRegForInlineAsmConstraint()
16136 if (VT == MVT::i64) in getRegForInlineAsmConstraint()
16163 if (VT == MVT::f32 || VT == MVT::i32) in getRegForInlineAsmConstraint()
16167 if (VT == MVT::f64 || VT == MVT::i64) in getRegForInlineAsmConstraint()
16183 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() && in getRegForInlineAsmConstraint()
16233 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative in LowerAsmOperandForConstraint()
16356 isPPC64 ? MVT::i64 : MVT::i32); in LowerRETURNADDR()
16378 bool isPPC64 = PtrVT == MVT::i64; in LowerFRAMEADDR()
16463 Info.memVT = MVT::i128; in getTgtMemIntrinsic()
16472 Info.memVT = MVT::i128; in getTgtMemIntrinsic()
16480 Info.memVT = MVT::i128; in getTgtMemIntrinsic()
16500 VT = MVT::i8; in getTgtMemIntrinsic()
16503 VT = MVT::i16; in getTgtMemIntrinsic()
16506 VT = MVT::i32; in getTgtMemIntrinsic()
16510 VT = MVT::v2f64; in getTgtMemIntrinsic()
16513 VT = MVT::v4i32; in getTgtMemIntrinsic()
16540 VT = MVT::i8; in getTgtMemIntrinsic()
16543 VT = MVT::i16; in getTgtMemIntrinsic()
16546 VT = MVT::i32; in getTgtMemIntrinsic()
16550 VT = MVT::v2f64; in getTgtMemIntrinsic()
16553 VT = MVT::v4i32; in getTgtMemIntrinsic()
16583 return MVT::v4i32; in getOptimalMemOpType()
16587 return MVT::i64; in getOptimalMemOpType()
16590 return MVT::i32; in getOptimalMemOpType()
16624 if ((MemVT == MVT::i1 || MemVT == MVT::i8 || MemVT == MVT::i16 || in isZExtFree()
16625 (Subtarget.isPPC64() && MemVT == MVT::i32)) && in isZExtFree()
16643 if (DestVT == MVT::f128) in isFPExtFree()
16677 if (VT != MVT::v2f64 && VT != MVT::v2i64 && in allowsMisalignedMemoryAccesses()
16678 VT != MVT::v4f32 && VT != MVT::v4i32) in allowsMisalignedMemoryAccesses()
16685 if (VT == MVT::ppcf128) in allowsMisalignedMemoryAccesses()
16818 if (VT == MVT::v2i64) in shouldExpandBuildVectorWithShuffles()
16954 case MVT::f32: in isFPImmLegal()
16955 case MVT::f64: in isFPImmLegal()
16961 case MVT::ppcf128: in isFPImmLegal()
17008 N0.getOperand(0).getValueType() != MVT::i32 || CN1 == nullptr || in combineSHL()
17009 N->getValueType(0) != MVT::i64) in combineSHL()
17023 if (ShiftBy.getValueType() == MVT::i64) in combineSHL()
17024 ShiftBy = DCI.DAG.getConstant(CN1->getZExtValue(), DL, MVT::i32); in combineSHL()
17026 return DCI.DAG.getNode(PPCISD::EXTSWSLI, DL, MVT::i64, N0->getOperand(0), in combineSHL()
17058 Op.getValueType() != MVT::i64) in combineADDToADDZE()
17063 Cmp.getOperand(0).getValueType() != MVT::i64) in combineADDToADDZE()
17086 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Glue); in combineADDToADDZE()
17101 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Z, in combineADDToADDZE()
17102 DAG.getConstant(NegConstant, DL, MVT::i64)); in combineADDToADDZE()
17104 SDValue Addc = DAG.getNode(ISD::ADDC, DL, DAG.getVTList(MVT::i64, MVT::Glue), in combineADDToADDZE()
17105 AddOrZ, DAG.getConstant(-1ULL, DL, MVT::i64)); in combineADDToADDZE()
17106 return DAG.getNode(ISD::ADDE, DL, VTs, LHS, DAG.getConstant(0, DL, MVT::i64), in combineADDToADDZE()
17116 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Z, in combineADDToADDZE()
17117 DAG.getConstant(NegConstant, DL, MVT::i64)); in combineADDToADDZE()
17119 SDValue Subc = DAG.getNode(ISD::SUBC, DL, DAG.getVTList(MVT::i64, MVT::Glue), in combineADDToADDZE()
17120 DAG.getConstant(0, DL, MVT::i64), AddOrZ); in combineADDToADDZE()
17121 return DAG.getNode(ISD::ADDE, DL, VTs, LHS, DAG.getConstant(0, DL, MVT::i64), in combineADDToADDZE()
17209 if (VT != MVT::v4i32 && VT != MVT::v8i16 && VT != MVT::v16i8) in combineTRUNCATE()
17219 DCI.DAG.getTargetConstant(0, dl, MVT::i32)); in combineTRUNCATE()
17225 if (Op0.getValueType() != MVT::i128 || N->getValueType(0) != MVT::i64) in combineTRUNCATE()
17245 Op0.getValueType() == MVT::i128 && in combineTRUNCATE()
17246 Op0.getOperand(0).getValueType() == MVT::f128) { in combineTRUNCATE()
17247 SDValue Bitcast = DCI.DAG.getBitcast(MVT::v2i64, Op0.getOperand(0)); in combineTRUNCATE()
17249 ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Bitcast, in combineTRUNCATE()
17250 DCI.DAG.getTargetConstant(EltToExtract, dl, MVT::i32)); in combineTRUNCATE()
17410 if (Subtarget.hasP9Vector() && VT == MVT::f128) in hasBitPreservingFPLogic()
17412 return VT == MVT::f32 || VT == MVT::f64 || in hasBitPreservingFPLogic()
17413 VT == MVT::v4f32 || VT == MVT::v2f64; in hasBitPreservingFPLogic()
17443 if (VT != MVT::v4i32 && VT != MVT::v8i16 && VT != MVT::v16i8) in combineABS()
17460 DAG.getTargetConstant(0, dl, MVT::i32)); in combineABS()
17464 if (N->getOperand(0).getValueType() == MVT::v4i32 && in combineABS()
17469 DAG.getTargetConstant(1, dl, MVT::i32)); in combineABS()
17499 if (VT != MVT::v4i32 && VT != MVT::v8i16 && VT != MVT::v16i8) in combineVSelect()
17533 DAG.getTargetConstant(0, dl, MVT::i32)); in combineVSelect()
17727 else if (MemVT == MVT::f128 || MemVT.isVector()) in computeMOFlags()
17811 unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts()
17817 if (PartVT == MVT::f64 && in splitValueIntoRegisterParts()
17818 (ValVT == MVT::i32 || ValVT == MVT::i16 || ValVT == MVT::i8)) { in splitValueIntoRegisterParts()
17819 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val); in splitValueIntoRegisterParts()
17820 Val = DAG.getNode(ISD::BITCAST, DL, MVT::f64, Val); in splitValueIntoRegisterParts()
17869 if (Op.getValueType() == MVT::f32) in lowerLibCallBasedOnType()
17872 if (Op.getValueType() == MVT::f64) in lowerLibCallBasedOnType()
18028 if ((CNType == MVT::i32 || isInt<32>(CNImm)) && in SelectOptimalAddrMode()
18032 Disp = DAG.getTargetConstant((int16_t)Addr, DL, MVT::i32); in SelectOptimalAddrMode()
18034 DAG.getTargetConstant((Addr - (int16_t)Addr) >> 16, DL, MVT::i32); in SelectOptimalAddrMode()
18035 uint32_t LIS = CNType == MVT::i32 ? PPC::LIS : PPC::LIS8; in SelectOptimalAddrMode()