Lines Matching refs:MVT
140 static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT, in CC_SkipOdd()
177 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32); in CreateCopyOfByValArgument()
260 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps); in LowerReturn()
368 if (RVLocs[i].getValVT() == MVT::i1) { in LowerCallResult()
376 MVT::i32, Glue); in LowerCallResult()
385 RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1); in LowerCallResult()
423 Callee = DAG.getTargetGlobalAddress(GAN->getGlobal(), dl, MVT::i32); in LowerCall()
500 MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr); in LowerCall()
533 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall()
583 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); in LowerCall()
637 bool IsLegalType = VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 || in getPostIndexedAddressParts()
638 VT == MVT::i64 || VT == MVT::f32 || VT == MVT::f64 || in getPostIndexedAddressParts()
639 VT == MVT::v2i16 || VT == MVT::v2i32 || VT == MVT::v4i8 || in getPostIndexedAddressParts()
640 VT == MVT::v4i16 || VT == MVT::v8i8 || in getPostIndexedAddressParts()
669 if (Op.getOperand(NumOps-1).getValueType() == MVT::Glue) in LowerINLINEASM()
713 SDValue Zero = DAG.getConstant(0, DL, MVT::i32); in LowerPREFETCH()
714 return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero); in LowerPREFETCH()
725 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other); in LowerREADCYCLECOUNTER()
737 SDValue Zero = DAG.getConstant(0, DL, MVT::i32); in LowerINTRINSIC_VOID()
738 return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero); in LowerINTRINSIC_VOID()
766 SDValue AC = DAG.getConstant(A, dl, MVT::i32); in LowerDYNAMIC_STACKALLOC()
767 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other); in LowerDYNAMIC_STACKALLOC()
839 MVT RegVT = VA.getLocVT(); in LowerFormalArguments()
850 if (VA.getValVT() == MVT::i1) { in LowerFormalArguments()
854 Copy = DAG.getSetCC(dl, MVT::i1, T, DAG.getConstant(0, dl, RegVT), in LowerFormalArguments()
878 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); in LowerFormalArguments()
950 SDValue Addr = DAG.getFrameIndex(QFI->getVarArgsFrameIndex(), MVT::i32); in LowerVASTART()
972 DAG.getFrameIndex(FuncInfo.getRegSavedAreaStartFrameIndex(), MVT::i32); in LowerVASTART()
980 MVT::i32), in LowerVASTART()
1008 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps); in LowerVASTART()
1034 MVT ResTy = ty(Op); in LowerSETCC()
1035 MVT OpTy = ty(LHS); in LowerSETCC()
1037 if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) { in LowerSETCC()
1038 MVT ElemTy = OpTy.getVectorElementType(); in LowerSETCC()
1040 MVT WideTy = MVT::getVectorVT(MVT::getIntegerVT(2*ElemTy.getSizeInBits()), in LowerSETCC()
1076 if (OpTy == MVT::i8 || OpTy == MVT::i16) { in LowerSETCC()
1081 DAG.getSExtOrTrunc(LHS, SDLoc(LHS), MVT::i32), in LowerSETCC()
1082 DAG.getSExtOrTrunc(RHS, SDLoc(RHS), MVT::i32), CC); in LowerSETCC()
1092 MVT OpTy = ty(Op1); in LowerVSELECT()
1095 if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) { in LowerVSELECT()
1096 MVT ElemTy = OpTy.getVectorElementType(); in LowerVSELECT()
1098 MVT WideTy = MVT::getVectorVT(MVT::getIntegerVT(2*ElemTy.getSizeInBits()), in LowerVSELECT()
1182 SDValue Offset = DAG.getConstant(4, dl, MVT::i32); in LowerRETURNADDR()
1189 Register Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32)); in LowerRETURNADDR()
1213 return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0)); in LowerATOMIC_FENCE()
1245 SDValue Off = DAG.getConstant(Offset, dl, MVT::i32); in LowerGLOBALADDRESS()
1281 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); in GetDynamicTLSAddr()
1466 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass); in HexagonTargetLowering()
1467 addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa in HexagonTargetLowering()
1468 addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa in HexagonTargetLowering()
1469 addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba in HexagonTargetLowering()
1470 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass); in HexagonTargetLowering()
1471 addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass); in HexagonTargetLowering()
1472 addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass); in HexagonTargetLowering()
1473 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
1474 addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
1475 addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
1476 addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
1478 addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass); in HexagonTargetLowering()
1479 addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
1493 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); in HexagonTargetLowering()
1494 setOperationAction(ISD::ConstantFP, MVT::f64, Legal); in HexagonTargetLowering()
1495 setOperationAction(ISD::TRAP, MVT::Other, Legal); in HexagonTargetLowering()
1496 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); in HexagonTargetLowering()
1497 setOperationAction(ISD::JumpTable, MVT::i32, Custom); in HexagonTargetLowering()
1498 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); in HexagonTargetLowering()
1499 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in HexagonTargetLowering()
1500 setOperationAction(ISD::INLINEASM, MVT::Other, Custom); in HexagonTargetLowering()
1501 setOperationAction(ISD::INLINEASM_BR, MVT::Other, Custom); in HexagonTargetLowering()
1502 setOperationAction(ISD::PREFETCH, MVT::Other, Custom); in HexagonTargetLowering()
1503 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom); in HexagonTargetLowering()
1504 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); in HexagonTargetLowering()
1505 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); in HexagonTargetLowering()
1506 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom); in HexagonTargetLowering()
1507 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); in HexagonTargetLowering()
1508 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); in HexagonTargetLowering()
1511 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); in HexagonTargetLowering()
1512 setOperationAction(ISD::GlobalAddress, MVT::i8, Custom); in HexagonTargetLowering()
1513 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); in HexagonTargetLowering()
1516 setOperationAction(ISD::SETCC, MVT::i8, Custom); in HexagonTargetLowering()
1517 setOperationAction(ISD::SETCC, MVT::i16, Custom); in HexagonTargetLowering()
1518 setOperationAction(ISD::SETCC, MVT::v4i8, Custom); in HexagonTargetLowering()
1519 setOperationAction(ISD::SETCC, MVT::v2i16, Custom); in HexagonTargetLowering()
1522 setOperationAction(ISD::VASTART, MVT::Other, Custom); in HexagonTargetLowering()
1523 setOperationAction(ISD::VAEND, MVT::Other, Expand); in HexagonTargetLowering()
1524 setOperationAction(ISD::VAARG, MVT::Other, Expand); in HexagonTargetLowering()
1526 setOperationAction(ISD::VACOPY, MVT::Other, Custom); in HexagonTargetLowering()
1528 setOperationAction(ISD::VACOPY, MVT::Other, Expand); in HexagonTargetLowering()
1530 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); in HexagonTargetLowering()
1531 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); in HexagonTargetLowering()
1532 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); in HexagonTargetLowering()
1538 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in HexagonTargetLowering()
1542 setOperationAction(LegalIntOp, MVT::i32, Legal); in HexagonTargetLowering()
1543 setOperationAction(LegalIntOp, MVT::i64, Legal); in HexagonTargetLowering()
1548 for (MVT VT : MVT::integer_valuetypes()) { in HexagonTargetLowering()
1556 setOperationAction(ISD::ADDCARRY, MVT::i64, Custom); in HexagonTargetLowering()
1557 setOperationAction(ISD::SUBCARRY, MVT::i64, Custom); in HexagonTargetLowering()
1559 setOperationAction(ISD::CTLZ, MVT::i8, Promote); in HexagonTargetLowering()
1560 setOperationAction(ISD::CTLZ, MVT::i16, Promote); in HexagonTargetLowering()
1561 setOperationAction(ISD::CTTZ, MVT::i8, Promote); in HexagonTargetLowering()
1562 setOperationAction(ISD::CTTZ, MVT::i16, Promote); in HexagonTargetLowering()
1565 setOperationAction(ISD::CTPOP, MVT::i8, Promote); in HexagonTargetLowering()
1566 setOperationAction(ISD::CTPOP, MVT::i16, Promote); in HexagonTargetLowering()
1567 setOperationAction(ISD::CTPOP, MVT::i32, Promote); in HexagonTargetLowering()
1568 setOperationAction(ISD::CTPOP, MVT::i64, Legal); in HexagonTargetLowering()
1570 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); in HexagonTargetLowering()
1571 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal); in HexagonTargetLowering()
1572 setOperationAction(ISD::BSWAP, MVT::i32, Legal); in HexagonTargetLowering()
1573 setOperationAction(ISD::BSWAP, MVT::i64, Legal); in HexagonTargetLowering()
1575 setOperationAction(ISD::FSHL, MVT::i32, Legal); in HexagonTargetLowering()
1576 setOperationAction(ISD::FSHL, MVT::i64, Legal); in HexagonTargetLowering()
1577 setOperationAction(ISD::FSHR, MVT::i32, Legal); in HexagonTargetLowering()
1578 setOperationAction(ISD::FSHR, MVT::i64, Legal); in HexagonTargetLowering()
1585 for (MVT VT : MVT::integer_valuetypes()) in HexagonTargetLowering()
1592 for (MVT VT : MVT::fp_valuetypes()) in HexagonTargetLowering()
1597 for (MVT VT : MVT::integer_valuetypes()) { in HexagonTargetLowering()
1598 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand); in HexagonTargetLowering()
1599 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand); in HexagonTargetLowering()
1600 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand); in HexagonTargetLowering()
1603 setTruncStoreAction(MVT::f64, MVT::f32, Expand); in HexagonTargetLowering()
1605 for (MVT VT : MVT::fp_valuetypes()) in HexagonTargetLowering()
1606 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in HexagonTargetLowering()
1609 for (MVT VT : MVT::integer_valuetypes()) { in HexagonTargetLowering()
1613 for (MVT VT : MVT::fp_valuetypes()) { in HexagonTargetLowering()
1617 setOperationAction(ISD::BR_CC, MVT::Other, Expand); in HexagonTargetLowering()
1650 for (MVT VT : MVT::fixedlen_vector_valuetypes()) { in HexagonTargetLowering()
1655 for (MVT TargetVT : MVT::fixedlen_vector_valuetypes()) { in HexagonTargetLowering()
1665 if (VT.getVectorElementType() != MVT::i32) { in HexagonTargetLowering()
1666 MVT VT32 = MVT::getVectorVT(MVT::i32, VT.getSizeInBits()/32); in HexagonTargetLowering()
1677 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, MVT::v2i8, Legal); in HexagonTargetLowering()
1678 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, MVT::v2i8, Legal); in HexagonTargetLowering()
1679 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, MVT::v2i8, Legal); in HexagonTargetLowering()
1680 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, MVT::v4i8, Legal); in HexagonTargetLowering()
1681 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, MVT::v4i8, Legal); in HexagonTargetLowering()
1682 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, MVT::v4i8, Legal); in HexagonTargetLowering()
1684 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Legal); in HexagonTargetLowering()
1685 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal); in HexagonTargetLowering()
1686 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal); in HexagonTargetLowering()
1689 for (MVT NativeVT : {MVT::v8i1, MVT::v4i1, MVT::v2i1, MVT::v4i8, in HexagonTargetLowering()
1690 MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v2i32}) { in HexagonTargetLowering()
1705 if (NativeVT.getVectorElementType() != MVT::i1) in HexagonTargetLowering()
1709 for (MVT VT : {MVT::v8i8, MVT::v4i16, MVT::v2i32}) { in HexagonTargetLowering()
1720 for (MVT VT : {MVT::i16, MVT::i32, MVT::v4i8, MVT::i64, MVT::v8i8, in HexagonTargetLowering()
1721 MVT::v2i16, MVT::v4i16, MVT::v2i32}) { in HexagonTargetLowering()
1727 for (MVT VT : {MVT::v2i1, MVT::v4i1, MVT::v8i1}) { in HexagonTargetLowering()
1732 for (MVT VT : {MVT::v2i16, MVT::v4i8, MVT::v8i8, MVT::v2i32, MVT::v4i16, in HexagonTargetLowering()
1733 MVT::v2i32}) { in HexagonTargetLowering()
1744 setOperationAction(ISD::BITCAST, MVT::i8, Custom); in HexagonTargetLowering()
1745 setOperationAction(ISD::SETCC, MVT::v2i16, Custom); in HexagonTargetLowering()
1746 setOperationAction(ISD::VSELECT, MVT::v4i8, Custom); in HexagonTargetLowering()
1747 setOperationAction(ISD::VSELECT, MVT::v2i16, Custom); in HexagonTargetLowering()
1748 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i8, Custom); in HexagonTargetLowering()
1749 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); in HexagonTargetLowering()
1750 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); in HexagonTargetLowering()
1753 setOperationAction(ISD::FMA, MVT::f64, Expand); in HexagonTargetLowering()
1754 setOperationAction(ISD::FADD, MVT::f64, Expand); in HexagonTargetLowering()
1755 setOperationAction(ISD::FSUB, MVT::f64, Expand); in HexagonTargetLowering()
1756 setOperationAction(ISD::FMUL, MVT::f64, Expand); in HexagonTargetLowering()
1758 setOperationAction(ISD::FMINNUM, MVT::f32, Legal); in HexagonTargetLowering()
1759 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in HexagonTargetLowering()
1761 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote); in HexagonTargetLowering()
1762 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote); in HexagonTargetLowering()
1763 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote); in HexagonTargetLowering()
1764 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote); in HexagonTargetLowering()
1765 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote); in HexagonTargetLowering()
1766 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote); in HexagonTargetLowering()
1767 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote); in HexagonTargetLowering()
1768 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote); in HexagonTargetLowering()
1769 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote); in HexagonTargetLowering()
1770 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); in HexagonTargetLowering()
1771 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote); in HexagonTargetLowering()
1772 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); in HexagonTargetLowering()
1776 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); in HexagonTargetLowering()
1777 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); in HexagonTargetLowering()
1778 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); in HexagonTargetLowering()
1779 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); in HexagonTargetLowering()
1781 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand); in HexagonTargetLowering()
1782 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand); in HexagonTargetLowering()
1783 setTruncStoreAction(MVT::f32, MVT::f16, Expand); in HexagonTargetLowering()
1784 setTruncStoreAction(MVT::f64, MVT::f16, Expand); in HexagonTargetLowering()
1788 for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64, MVT::f32, MVT::f64, in HexagonTargetLowering()
1789 MVT::v2i16, MVT::v2i32, MVT::v4i8, MVT::v4i16, MVT::v8i8}) { in HexagonTargetLowering()
1797 setOperationAction(ISD::ROTL, MVT::i32, Legal); in HexagonTargetLowering()
1798 setOperationAction(ISD::ROTL, MVT::i64, Legal); in HexagonTargetLowering()
1799 setOperationAction(ISD::ROTR, MVT::i32, Legal); in HexagonTargetLowering()
1800 setOperationAction(ISD::ROTR, MVT::i64, Legal); in HexagonTargetLowering()
1803 setOperationAction(ISD::FADD, MVT::f64, Legal); in HexagonTargetLowering()
1804 setOperationAction(ISD::FSUB, MVT::f64, Legal); in HexagonTargetLowering()
1807 setOperationAction(ISD::FMINNUM, MVT::f64, Legal); in HexagonTargetLowering()
1808 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in HexagonTargetLowering()
1809 setOperationAction(ISD::FMUL, MVT::f64, Legal); in HexagonTargetLowering()
1975 SDValue Trap = DAG.getNode(ISD::TRAP, dl, MVT::Other, Chain); in replaceMemWithUndef()
2078 Info.memVT = MVT::getVT(ElTy); in getTgtMemIntrinsic()
2103 Info.memVT = MVT::getVT(VecTy); in getTgtMemIntrinsic()
2130 return VT1.getSimpleVT() == MVT::i64 && VT2.getSimpleVT() == MVT::i32; in isTruncateFree()
2150 HexagonTargetLowering::getPreferredVectorAction(MVT VT) const { in getPreferredVectorAction()
2152 MVT ElemTy = VT.getVectorElementType(); in getPreferredVectorAction()
2164 if (ElemTy == MVT::i1) in getPreferredVectorAction()
2195 MVT VecTy = ty(Op); in LowerVECTOR_SHUFFLE()
2256 SDValue T0 = DAG.getBitcast(MVT::i32, Op0); in LowerVECTOR_SHUFFLE()
2257 SDValue T1 = DAG.getNode(ISD::BSWAP, dl, MVT::i32, T0); in LowerVECTOR_SHUFFLE()
2283 SDValue T0 = DAG.getBitcast(MVT::i64, Op0); in LowerVECTOR_SHUFFLE()
2284 SDValue T1 = DAG.getNode(ISD::BSWAP, dl, MVT::i64, T0); in LowerVECTOR_SHUFFLE()
2360 MVT ResTy = ty(Op); in LowerBITCAST()
2362 MVT InpTy = ty(InpV); in LowerBITCAST()
2367 if (InpTy == MVT::i8) { in LowerBITCAST()
2368 if (ResTy == MVT::v8i1) { in LowerBITCAST()
2370 SDValue Ext = DAG.getZExtOrTrunc(Sc, dl, MVT::i32); in LowerBITCAST()
2381 MVT VecTy, SelectionDAG &DAG, in getBuildVectorConstInts()
2383 MVT ElemTy = VecTy.getVectorElementType(); in getBuildVectorConstInts()
2411 MVT VecTy, SelectionDAG &DAG) const { in buildVector32()
2412 MVT ElemTy = VecTy.getVectorElementType(); in buildVector32()
2430 if (ElemTy == MVT::i16 || ElemTy == MVT::f16) { in buildVector32()
2437 return DAG.getBitcast(VecTy, DAG.getConstant(V, dl, MVT::i32)); in buildVector32()
2440 if (ElemTy == MVT::f16) { in buildVector32()
2441 E0 = DAG.getZExtOrTrunc(DAG.getBitcast(MVT::i16, Elem[0]), dl, MVT::i32); in buildVector32()
2442 E1 = DAG.getZExtOrTrunc(DAG.getBitcast(MVT::i16, Elem[1]), dl, MVT::i32); in buildVector32()
2447 SDValue N = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32, {E1, E0}, DAG); in buildVector32()
2451 if (ElemTy == MVT::i8) { in buildVector32()
2458 return DAG.getBitcast(MVT::v4i8, DAG.getConstant(V, dl, MVT::i32)); in buildVector32()
2471 SDValue Ext = DAG.getZExtOrTrunc(Elem[First], dl, MVT::i32); in buildVector32()
2481 Vs[i] = DAG.getZExtOrTrunc(Elem[i], dl, MVT::i32); in buildVector32()
2482 Vs[i] = DAG.getZeroExtendInReg(Vs[i], dl, MVT::i8); in buildVector32()
2484 SDValue S8 = DAG.getConstant(8, dl, MVT::i32); in buildVector32()
2485 SDValue T0 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[1], S8}); in buildVector32()
2486 SDValue T1 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[3], S8}); in buildVector32()
2487 SDValue B0 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[0], T0}); in buildVector32()
2488 SDValue B1 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[2], T1}); in buildVector32()
2490 SDValue R = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32, {B1, B0}, DAG); in buildVector32()
2491 return DAG.getBitcast(MVT::v4i8, R); in buildVector32()
2502 MVT VecTy, SelectionDAG &DAG) const { in buildVector64()
2503 MVT ElemTy = VecTy.getVectorElementType(); in buildVector64()
2522 if (ElemTy == MVT::i16 || ElemTy == MVT::f16) { in buildVector64()
2532 SDValue S = ElemTy == MVT::f16 ? DAG.getBitcast(MVT::i16, Elem[First]) in buildVector64()
2534 SDValue Ext = DAG.getZExtOrTrunc(S, dl, MVT::i32); in buildVector64()
2546 SDValue V0 = DAG.getConstant(Val, dl, MVT::i64); in buildVector64()
2551 MVT HalfTy = MVT::getVectorVT(ElemTy, Num/2); in buildVector64()
2552 SDValue L = (ElemTy == MVT::i32) in buildVector64()
2555 SDValue H = (ElemTy == MVT::i32) in buildVector64()
2563 const SDLoc &dl, MVT ValTy, MVT ResTy, in extractVector()
2565 MVT VecTy = ty(VecV); in extractVector()
2586 return DAG.getNode(HexagonISD::TYPECAST, dl, MVT::i1, VecV); in extractVector()
2591 SDValue A0 = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, {VecV}, DAG); in extractVector()
2592 SDValue M0 = DAG.getConstant(8 / VecWidth, dl, MVT::i32); in extractVector()
2593 SDValue I0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, M0); in extractVector()
2594 return DAG.getNode(HexagonISD::TSTBIT, dl, MVT::i1, A0, I0); in extractVector()
2605 assert(ty(IdxV) == MVT::i32); in extractVector()
2607 SDValue S0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, in extractVector()
2608 DAG.getConstant(8*VecRep, dl, MVT::i32)); in extractVector()
2609 SDValue T0 = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, VecV); in extractVector()
2610 SDValue T1 = DAG.getNode(ISD::SRL, dl, MVT::i64, T0, S0); in extractVector()
2614 T1 = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, T1); in extractVector()
2625 MVT ScalarTy = tyScalar(VecTy); in extractVector()
2628 SDValue WidthV = DAG.getConstant(ValWidth, dl, MVT::i32); in extractVector()
2636 ExtV = DAG.getTargetExtractSubreg(SubIdx, dl, MVT::i32, VecV); in extractVector()
2640 SDValue OffV = DAG.getConstant(Off, dl, MVT::i32); in extractVector()
2647 if (ty(IdxV) != MVT::i32) in extractVector()
2648 IdxV = DAG.getZExtOrTrunc(IdxV, dl, MVT::i32); in extractVector()
2649 SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, in extractVector()
2650 DAG.getConstant(ElemWidth, dl, MVT::i32)); in extractVector()
2663 const SDLoc &dl, MVT ValTy, in insertVector()
2665 MVT VecTy = ty(VecV); in insertVector()
2666 if (VecTy.getVectorElementType() == MVT::i1) { in insertVector()
2667 MVT ValTy = ty(ValV); in insertVector()
2668 assert(ValTy.getVectorElementType() == MVT::i1); in insertVector()
2669 SDValue ValR = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, ValV); in insertVector()
2676 ValR = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64, in insertVector()
2677 DAG.getUNDEF(MVT::i32), ValR); in insertVector()
2681 ValR = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, ValR); in insertVector()
2684 SDValue Width = DAG.getConstant(ValBytes*8, dl, MVT::i32); in insertVector()
2685 SDValue Idx = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, in insertVector()
2686 DAG.getConstant(8, dl, MVT::i32)); in insertVector()
2687 SDValue VecR = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, VecV); in insertVector()
2688 SDValue Ins = DAG.getNode(HexagonISD::INSERT, dl, MVT::i32, in insertVector()
2699 MVT ScalarTy = MVT::getIntegerVT(VecWidth); in insertVector()
2703 ValV = DAG.getBitcast(MVT::getIntegerVT(VW), ValV); in insertVector()
2708 SDValue WidthV = DAG.getConstant(ValWidth, dl, MVT::i32); in insertVector()
2713 SDValue OffV = DAG.getConstant(W, dl, MVT::i32); in insertVector()
2717 if (ty(IdxV) != MVT::i32) in insertVector()
2718 IdxV = DAG.getZExtOrTrunc(IdxV, dl, MVT::i32); in insertVector()
2719 SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, WidthV); in insertVector()
2732 return DAG.getUNDEF(MVT::i64); in expandPredicate()
2733 return getInstr(Hexagon::S2_vsxtbh, dl, MVT::i64, {Vec32}, DAG); in expandPredicate()
2741 return DAG.getUNDEF(MVT::i32); in contractPredicate()
2742 return getInstr(Hexagon::S2_vtrunehb, dl, MVT::i32, {Vec64}, DAG); in contractPredicate()
2746 HexagonTargetLowering::getZero(const SDLoc &dl, MVT Ty, SelectionDAG &DAG) in getZero()
2751 return DAG.getBitcast(Ty, DAG.getConstant(0, dl, MVT::getIntegerVT(W))); in getZero()
2752 return DAG.getNode(ISD::SPLAT_VECTOR, dl, Ty, getZero(dl, MVT::i32, DAG)); in getZero()
2763 HexagonTargetLowering::appendUndef(SDValue Val, MVT ResTy, SelectionDAG &DAG) in appendUndef()
2765 MVT ValTy = ty(Val); in appendUndef()
2786 MVT VecTy = ty(Op); in LowerBUILD_VECTOR()
2798 if (VecTy == MVT::v8i1 || VecTy == MVT::v4i1 || VecTy == MVT::v2i1) { in LowerBUILD_VECTOR()
2820 SDValue Z = getZero(dl, MVT::i32, DAG); in LowerBUILD_VECTOR()
2824 SDValue S = DAG.getConstant(1ull << i, dl, MVT::i32); in LowerBUILD_VECTOR()
2825 Rs[i] = DAG.getSelect(dl, MVT::i32, Ops[i/Rep], S, Z); in LowerBUILD_VECTOR()
2829 Rs[i] = DAG.getNode(ISD::OR, dl, MVT::i32, Rs[2*i], Rs[2*i+1]); in LowerBUILD_VECTOR()
2841 MVT VecTy = ty(Op); in LowerCONCAT_VECTORS()
2849 MVT ElemTy = VecTy.getVectorElementType(); in LowerCONCAT_VECTORS()
2850 if (ElemTy == MVT::i1) { in LowerCONCAT_VECTORS()
2851 assert(VecTy == MVT::v2i1 || VecTy == MVT::v4i1 || VecTy == MVT::v8i1); in LowerCONCAT_VECTORS()
2852 MVT OpTy = ty(Op.getOperand(0)); in LowerCONCAT_VECTORS()
2866 SDValue W = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, P); in LowerCONCAT_VECTORS()
2869 W = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64, in LowerCONCAT_VECTORS()
2870 DAG.getUNDEF(MVT::i32), W); in LowerCONCAT_VECTORS()
2872 W = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, W); in LowerCONCAT_VECTORS()
2877 SDValue WidthV = DAG.getConstant(64 / Scale, dl, MVT::i32); in LowerCONCAT_VECTORS()
2883 SDValue T = DAG.getNode(HexagonISD::INSERT, dl, MVT::i32, in LowerCONCAT_VECTORS()
2894 SDValue WW = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64, in LowerCONCAT_VECTORS()
2906 MVT ElemTy = ty(Vec).getVectorElementType(); in LowerEXTRACT_VECTOR_ELT()
2947 MVT Ty = ty(Op); in LowerLoad()
2952 bool DoCast = (Ty == MVT::v2i1 || Ty == MVT::v4i1 || Ty == MVT::v8i1); in LowerLoad()
2955 LN->getAddressingMode(), LN->getExtensionType(), MVT::i1, dl, in LowerLoad()
2957 /*MemoryVT*/ MVT::i1, LN->getAlign(), LN->getMemOperand()->getFlags(), in LowerLoad()
2982 MVT Ty = ty(Val); in LowerStore()
2984 bool DoCast = (Ty == MVT::v2i1 || Ty == MVT::v4i1 || Ty == MVT::v8i1); in LowerStore()
2986 SDValue TC = DAG.getNode(HexagonISD::TYPECAST, dl, MVT::i1, Val); in LowerStore()
3000 MVT StoreTy = SN->getMemoryVT().getSimpleVT(); in LowerStore()
3011 MVT LoadTy = ty(Op); in LowerUnalignedLoad()
3036 MVT PartTy = HaveAlign <= 8 ? MVT::getIntegerVT(8 * HaveAlign) in LowerUnalignedLoad()
3037 : MVT::getVectorVT(MVT::i8, HaveAlign); in LowerUnalignedLoad()
3062 BO.first = DAG.getNode(ISD::ADD, dl, MVT::i32, BO.first, in LowerUnalignedLoad()
3063 DAG.getConstant(BO.second % LoadLen, dl, MVT::i32)); in LowerUnalignedLoad()
3067 ? DAG.getNode(HexagonISD::VALIGNADDR, dl, MVT::i32, BO.first, in LowerUnalignedLoad()
3068 DAG.getConstant(NeedAlign, dl, MVT::i32)) in LowerUnalignedLoad()
3089 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, in LowerUnalignedLoad()
3105 assert(VTs.VTs[1] == MVT::i1); in LowerUAddSubO()
3117 SDValue Ov = DAG.getSetCC(dl, MVT::i1, Op, getZero(dl, ty(Op), DAG), in LowerUAddSubO()
3123 SDValue Ov = DAG.getSetCC(dl, MVT::i1, Op, in LowerUAddSubO()
3174 return DAG.getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain); in LowerEH_RETURN()
3279 if (N->getValueType(0) == MVT::i8) { in ReplaceNodeResults()
3280 if (N->getOperand(0).getValueType() == MVT::v8i1) { in ReplaceNodeResults()
3281 SDValue P = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, in ReplaceNodeResults()
3283 SDValue T = DAG.getAnyExtOrTrunc(P, dl, MVT::i8); in ReplaceNodeResults()
3369 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const { in getRegForInlineAsmConstraint()
3377 case MVT::i1: in getRegForInlineAsmConstraint()
3378 case MVT::i8: in getRegForInlineAsmConstraint()
3379 case MVT::i16: in getRegForInlineAsmConstraint()
3380 case MVT::i32: in getRegForInlineAsmConstraint()
3381 case MVT::f32: in getRegForInlineAsmConstraint()
3383 case MVT::i64: in getRegForInlineAsmConstraint()
3384 case MVT::f64: in getRegForInlineAsmConstraint()
3389 if (VT != MVT::i32) in getRegForInlineAsmConstraint()
3552 return MVT::i64; in getOptimalMemOpType()
3554 return MVT::i32; in getOptimalMemOpType()
3556 return MVT::i16; in getOptimalMemOpType()
3557 return MVT::Other; in getOptimalMemOpType()
3563 MVT SVT = VT.getSimpleVT(); in allowsMemoryAccess()
3573 MVT SVT = VT.getSimpleVT(); in allowsMisalignedMemoryAccesses()
3583 MVT VT) const { in findRepresentativeClass()
3588 if (VT.getVectorElementType() == MVT::i1) in findRepresentativeClass()