Lines Matching refs:MVT
41 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_SRet()
42 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_SRet()
54 static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_Split_64()
55 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_Split_64()
80 static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_Ret_Split_64()
81 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_Ret_Split_64()
104 static bool Analyze_CC_Sparc64_Full(bool IsReturn, unsigned &ValNo, MVT &ValVT, in Analyze_CC_Sparc64_Full()
105 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in Analyze_CC_Sparc64_Full()
107 assert((LocVT == MVT::f32 || LocVT == MVT::f128 in Analyze_CC_Sparc64_Full()
112 unsigned size = (LocVT == MVT::f128) ? 16 : 8; in Analyze_CC_Sparc64_Full()
113 Align alignment = (LocVT == MVT::f128) ? Align(16) : Align(8); in Analyze_CC_Sparc64_Full()
117 if (LocVT == MVT::i64 && Offset < 6*8) in Analyze_CC_Sparc64_Full()
120 else if (LocVT == MVT::f64 && Offset < 16*8) in Analyze_CC_Sparc64_Full()
123 else if (LocVT == MVT::f32 && Offset < 16*8) in Analyze_CC_Sparc64_Full()
126 else if (LocVT == MVT::f128 && Offset < 16*8) in Analyze_CC_Sparc64_Full()
144 if (LocVT == MVT::f32) in Analyze_CC_Sparc64_Full()
154 static bool Analyze_CC_Sparc64_Half(bool IsReturn, unsigned &ValNo, MVT &ValVT, in Analyze_CC_Sparc64_Half()
155 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in Analyze_CC_Sparc64_Half()
160 if (LocVT == MVT::f32 && Offset < 16*8) { in Analyze_CC_Sparc64_Half()
167 if (LocVT == MVT::i32 && Offset < 6*8) { in Analyze_CC_Sparc64_Half()
170 LocVT = MVT::i64; in Analyze_CC_Sparc64_Half()
191 static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT, in CC_Sparc64_Full()
198 static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT, in CC_Sparc64_Half()
205 static bool RetCC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT, in RetCC_Sparc64_Full()
212 static bool RetCC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT, in RetCC_Sparc64_Half()
285 assert(VA.getLocVT() == MVT::v2i32); in LowerReturn_32()
289 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
292 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
326 RetOps[1] = DAG.getConstant(RetAddrOffset, DL, MVT::i32); in LowerReturn_32()
332 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps); in LowerReturn_32()
358 RetOps.push_back(DAG.getConstant(8, DL, MVT::i32)); in LowerReturn_64()
384 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { in LowerReturn_64()
385 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal, in LowerReturn_64()
386 DAG.getConstant(32, DL, MVT::i32)); in LowerReturn_64()
391 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]); in LowerReturn_64()
392 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV); in LowerReturn_64()
411 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps); in LowerReturn_64()
454 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); in LowerFormalArguments_32()
456 DAG.getLoad(MVT::i32, dl, Chain, FIPtr, MachinePointerInfo()); in LowerFormalArguments_32()
463 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32); in LowerFormalArguments_32()
467 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32); in LowerFormalArguments_32()
476 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); in LowerFormalArguments_32()
477 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, MachinePointerInfo()); in LowerFormalArguments_32()
481 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32); in LowerFormalArguments_32()
488 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); in LowerFormalArguments_32()
495 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); in LowerFormalArguments_32()
496 if (VA.getLocVT() == MVT::f32) in LowerFormalArguments_32()
497 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg); in LowerFormalArguments_32()
498 else if (VA.getLocVT() != MVT::i32) { in LowerFormalArguments_32()
499 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg, in LowerFormalArguments_32()
513 assert(VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::v2i32); in LowerFormalArguments_32()
531 DAG.getLoad(MVT::i32, dl, Chain, FIPtr, MachinePointerInfo()); in LowerFormalArguments_32()
538 DAG.getLoad(MVT::i32, dl, Chain, FIPtr2, MachinePointerInfo()); in LowerFormalArguments_32()
544 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); in LowerFormalArguments_32()
555 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) { in LowerFormalArguments_32()
557 } else if (VA.getValVT() == MVT::f128) { in LowerFormalArguments_32()
576 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); in LowerFormalArguments_32()
602 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32); in LowerFormalArguments_32()
606 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); in LowerFormalArguments_32()
615 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); in LowerFormalArguments_32()
650 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) in LowerFormalArguments_64()
652 DAG.getConstant(32, DL, MVT::i32)); in LowerFormalArguments_64()
717 SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64); in LowerFormalArguments_64()
726 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); in LowerFormalArguments_64()
836 SDValue SizeNode = DAG.getConstant(Size, dl, MVT::i32); in LowerCall_32()
904 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
906 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
918 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32); in LowerCall_32()
924 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
926 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
933 if (VA.getLocVT() == MVT::f64) { in LowerCall_32()
939 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, Arg); in LowerCall_32()
942 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, in LowerCall_32()
945 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, in LowerCall_32()
958 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
960 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
967 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
969 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
974 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
984 if (VA.getLocVT() != MVT::f32) { in LowerCall_32()
988 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); in LowerCall_32()
996 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
999 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
1007 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall_32()
1030 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32, 0, TF); in LowerCall_32()
1032 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32, TF); in LowerCall_32()
1035 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); in LowerCall_32()
1040 Ops.push_back(DAG.getTargetConstant(SRetArgSize, dl, MVT::i32)); in LowerCall_32()
1062 return DAG.getNode(SPISD::TAIL_CALL, dl, MVT::Other, Ops); in LowerCall_32()
1082 if (RVLocs[i].getLocVT() == MVT::v2i32) { in LowerCall_32()
1083 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2i32); in LowerCall_32()
1085 Chain, dl, toCallerWindow(RVLocs[i++].getLocReg()), MVT::i32, InFlag); in LowerCall_32()
1088 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Lo, in LowerCall_32()
1089 DAG.getConstant(0, dl, MVT::i32)); in LowerCall_32()
1091 Chain, dl, toCallerWindow(RVLocs[i].getLocReg()), MVT::i32, InFlag); in LowerCall_32()
1094 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Hi, in LowerCall_32()
1095 DAG.getConstant(1, dl, MVT::i32)); in LowerCall_32()
1143 MVT ValTy = VA.getLocVT(); in fixupVariableFloatArgs()
1146 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128)) in fixupVariableFloatArgs()
1156 Register firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0; in fixupVariableFloatArgs()
1157 unsigned argSize = (ValTy == MVT::f64) ? 8 : 16; in fixupVariableFloatArgs()
1164 if (ValTy == MVT::f64) in fixupVariableFloatArgs()
1167 IReg, MVT::i64, CCValAssign::BCvt); in fixupVariableFloatArgs()
1169 assert(ValTy == MVT::f128 && "Unexpected type!"); in fixupVariableFloatArgs()
1173 IReg, MVT::i128, CCValAssign::BCvt); in fixupVariableFloatArgs()
1252 if (!VA.needsCustom() || VA.getValVT() != MVT::f128 in LowerCall_64()
1253 || VA.getLocVT() != MVT::i128) in LowerCall_64()
1259 if (VA.needsCustom() && VA.getValVT() == MVT::f128 in LowerCall_64()
1260 && VA.getLocVT() == MVT::i128) { in LowerCall_64()
1275 DAG.getLoad(MVT::i64, DL, Store, HiPtrOff, MachinePointerInfo()); in LowerCall_64()
1277 DAG.getLoad(MVT::i64, DL, Store, LoPtrOff, MachinePointerInfo()); in LowerCall_64()
1287 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { in LowerCall_64()
1288 Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg, in LowerCall_64()
1289 DAG.getConstant(32, DL, MVT::i32)); in LowerCall_64()
1295 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, in LowerCall_64()
1297 Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV); in LowerCall_64()
1322 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); in LowerCall_64()
1370 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); in LowerCall_64()
1389 if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && !CLI.CB) in LowerCall_64()
1416 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) in LowerCall_64()
1418 DAG.getConstant(32, DL, MVT::i32)); in LowerCall_64()
1506 MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0)); in SparcTargetLowering()
1517 addRegisterClass(MVT::i32, &SP::IntRegsRegClass); in SparcTargetLowering()
1519 addRegisterClass(MVT::f32, &SP::FPRegsRegClass); in SparcTargetLowering()
1520 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass); in SparcTargetLowering()
1521 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass); in SparcTargetLowering()
1524 addRegisterClass(MVT::i64, &SP::I64RegsRegClass); in SparcTargetLowering()
1528 addRegisterClass(MVT::v2i32, &SP::IntPairRegClass); in SparcTargetLowering()
1533 setOperationAction(Op, MVT::v2i32, Expand); in SparcTargetLowering()
1536 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) { in SparcTargetLowering()
1537 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Expand); in SparcTargetLowering()
1538 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i32, Expand); in SparcTargetLowering()
1539 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Expand); in SparcTargetLowering()
1541 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, VT, Expand); in SparcTargetLowering()
1542 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, VT, Expand); in SparcTargetLowering()
1543 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, VT, Expand); in SparcTargetLowering()
1545 setTruncStoreAction(VT, MVT::v2i32, Expand); in SparcTargetLowering()
1546 setTruncStoreAction(MVT::v2i32, VT, Expand); in SparcTargetLowering()
1549 setOperationAction(ISD::LOAD, MVT::v2i32, Legal); in SparcTargetLowering()
1550 setOperationAction(ISD::STORE, MVT::v2i32, Legal); in SparcTargetLowering()
1551 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Legal); in SparcTargetLowering()
1552 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Legal); in SparcTargetLowering()
1555 setOperationAction(ISD::LOAD, MVT::i64, Custom); in SparcTargetLowering()
1556 setOperationAction(ISD::STORE, MVT::i64, Custom); in SparcTargetLowering()
1564 for (MVT VT : MVT::fp_valuetypes()) { in SparcTargetLowering()
1565 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); in SparcTargetLowering()
1566 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in SparcTargetLowering()
1567 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand); in SparcTargetLowering()
1571 for (MVT VT : MVT::integer_valuetypes()) in SparcTargetLowering()
1572 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in SparcTargetLowering()
1575 setTruncStoreAction(MVT::f32, MVT::f16, Expand); in SparcTargetLowering()
1576 setTruncStoreAction(MVT::f64, MVT::f16, Expand); in SparcTargetLowering()
1577 setTruncStoreAction(MVT::f64, MVT::f32, Expand); in SparcTargetLowering()
1578 setTruncStoreAction(MVT::f128, MVT::f16, Expand); in SparcTargetLowering()
1579 setTruncStoreAction(MVT::f128, MVT::f32, Expand); in SparcTargetLowering()
1580 setTruncStoreAction(MVT::f128, MVT::f64, Expand); in SparcTargetLowering()
1589 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in SparcTargetLowering()
1590 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); in SparcTargetLowering()
1591 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); in SparcTargetLowering()
1594 setOperationAction(ISD::UREM, MVT::i32, Expand); in SparcTargetLowering()
1595 setOperationAction(ISD::SREM, MVT::i32, Expand); in SparcTargetLowering()
1596 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in SparcTargetLowering()
1597 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in SparcTargetLowering()
1601 setOperationAction(ISD::UREM, MVT::i64, Expand); in SparcTargetLowering()
1602 setOperationAction(ISD::SREM, MVT::i64, Expand); in SparcTargetLowering()
1603 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in SparcTargetLowering()
1604 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in SparcTargetLowering()
1608 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in SparcTargetLowering()
1609 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1610 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in SparcTargetLowering()
1611 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in SparcTargetLowering()
1614 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in SparcTargetLowering()
1615 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1616 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); in SparcTargetLowering()
1617 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in SparcTargetLowering()
1620 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); in SparcTargetLowering()
1621 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); in SparcTargetLowering()
1622 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); in SparcTargetLowering()
1623 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); in SparcTargetLowering()
1624 setOperationAction(ISD::FP16_TO_FP, MVT::f128, Expand); in SparcTargetLowering()
1625 setOperationAction(ISD::FP_TO_FP16, MVT::f128, Expand); in SparcTargetLowering()
1627 setOperationAction(ISD::BITCAST, MVT::f32, Expand); in SparcTargetLowering()
1628 setOperationAction(ISD::BITCAST, MVT::i32, Expand); in SparcTargetLowering()
1631 setOperationAction(ISD::SELECT, MVT::i32, Expand); in SparcTargetLowering()
1632 setOperationAction(ISD::SELECT, MVT::f32, Expand); in SparcTargetLowering()
1633 setOperationAction(ISD::SELECT, MVT::f64, Expand); in SparcTargetLowering()
1634 setOperationAction(ISD::SELECT, MVT::f128, Expand); in SparcTargetLowering()
1636 setOperationAction(ISD::SETCC, MVT::i32, Expand); in SparcTargetLowering()
1637 setOperationAction(ISD::SETCC, MVT::f32, Expand); in SparcTargetLowering()
1638 setOperationAction(ISD::SETCC, MVT::f64, Expand); in SparcTargetLowering()
1639 setOperationAction(ISD::SETCC, MVT::f128, Expand); in SparcTargetLowering()
1642 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in SparcTargetLowering()
1643 setOperationAction(ISD::BRIND, MVT::Other, Expand); in SparcTargetLowering()
1644 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in SparcTargetLowering()
1645 setOperationAction(ISD::BR_CC, MVT::i32, Custom); in SparcTargetLowering()
1646 setOperationAction(ISD::BR_CC, MVT::f32, Custom); in SparcTargetLowering()
1647 setOperationAction(ISD::BR_CC, MVT::f64, Custom); in SparcTargetLowering()
1648 setOperationAction(ISD::BR_CC, MVT::f128, Custom); in SparcTargetLowering()
1650 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in SparcTargetLowering()
1651 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in SparcTargetLowering()
1652 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in SparcTargetLowering()
1653 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); in SparcTargetLowering()
1655 setOperationAction(ISD::ADDC, MVT::i32, Custom); in SparcTargetLowering()
1656 setOperationAction(ISD::ADDE, MVT::i32, Custom); in SparcTargetLowering()
1657 setOperationAction(ISD::SUBC, MVT::i32, Custom); in SparcTargetLowering()
1658 setOperationAction(ISD::SUBE, MVT::i32, Custom); in SparcTargetLowering()
1661 setOperationAction(ISD::ADDC, MVT::i64, Custom); in SparcTargetLowering()
1662 setOperationAction(ISD::ADDE, MVT::i64, Custom); in SparcTargetLowering()
1663 setOperationAction(ISD::SUBC, MVT::i64, Custom); in SparcTargetLowering()
1664 setOperationAction(ISD::SUBE, MVT::i64, Custom); in SparcTargetLowering()
1665 setOperationAction(ISD::BITCAST, MVT::f64, Expand); in SparcTargetLowering()
1666 setOperationAction(ISD::BITCAST, MVT::i64, Expand); in SparcTargetLowering()
1667 setOperationAction(ISD::SELECT, MVT::i64, Expand); in SparcTargetLowering()
1668 setOperationAction(ISD::SETCC, MVT::i64, Expand); in SparcTargetLowering()
1669 setOperationAction(ISD::BR_CC, MVT::i64, Custom); in SparcTargetLowering()
1670 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); in SparcTargetLowering()
1672 setOperationAction(ISD::CTPOP, MVT::i64, in SparcTargetLowering()
1674 setOperationAction(ISD::CTTZ , MVT::i64, Expand); in SparcTargetLowering()
1675 setOperationAction(ISD::CTLZ , MVT::i64, Expand); in SparcTargetLowering()
1676 setOperationAction(ISD::BSWAP, MVT::i64, Expand); in SparcTargetLowering()
1677 setOperationAction(ISD::ROTL , MVT::i64, Expand); in SparcTargetLowering()
1678 setOperationAction(ISD::ROTR , MVT::i64, Expand); in SparcTargetLowering()
1679 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom); in SparcTargetLowering()
1695 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Legal); in SparcTargetLowering()
1697 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Legal); in SparcTargetLowering()
1700 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom); in SparcTargetLowering()
1701 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom); in SparcTargetLowering()
1704 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Legal); in SparcTargetLowering()
1705 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Legal); in SparcTargetLowering()
1706 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); in SparcTargetLowering()
1707 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Custom); in SparcTargetLowering()
1722 setOperationAction(ISD::FNEG, MVT::f64, Custom); in SparcTargetLowering()
1723 setOperationAction(ISD::FABS, MVT::f64, Custom); in SparcTargetLowering()
1726 setOperationAction(ISD::FSIN , MVT::f128, Expand); in SparcTargetLowering()
1727 setOperationAction(ISD::FCOS , MVT::f128, Expand); in SparcTargetLowering()
1728 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); in SparcTargetLowering()
1729 setOperationAction(ISD::FREM , MVT::f128, Expand); in SparcTargetLowering()
1730 setOperationAction(ISD::FMA , MVT::f128, Expand); in SparcTargetLowering()
1731 setOperationAction(ISD::FSIN , MVT::f64, Expand); in SparcTargetLowering()
1732 setOperationAction(ISD::FCOS , MVT::f64, Expand); in SparcTargetLowering()
1733 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in SparcTargetLowering()
1734 setOperationAction(ISD::FREM , MVT::f64, Expand); in SparcTargetLowering()
1735 setOperationAction(ISD::FMA , MVT::f64, Expand); in SparcTargetLowering()
1736 setOperationAction(ISD::FSIN , MVT::f32, Expand); in SparcTargetLowering()
1737 setOperationAction(ISD::FCOS , MVT::f32, Expand); in SparcTargetLowering()
1738 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in SparcTargetLowering()
1739 setOperationAction(ISD::FREM , MVT::f32, Expand); in SparcTargetLowering()
1740 setOperationAction(ISD::FMA , MVT::f32, Expand); in SparcTargetLowering()
1741 setOperationAction(ISD::CTTZ , MVT::i32, Expand); in SparcTargetLowering()
1742 setOperationAction(ISD::CTLZ , MVT::i32, Expand); in SparcTargetLowering()
1743 setOperationAction(ISD::ROTL , MVT::i32, Expand); in SparcTargetLowering()
1744 setOperationAction(ISD::ROTR , MVT::i32, Expand); in SparcTargetLowering()
1745 setOperationAction(ISD::BSWAP, MVT::i32, Expand); in SparcTargetLowering()
1746 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); in SparcTargetLowering()
1747 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in SparcTargetLowering()
1748 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); in SparcTargetLowering()
1749 setOperationAction(ISD::FPOW , MVT::f128, Expand); in SparcTargetLowering()
1750 setOperationAction(ISD::FPOW , MVT::f64, Expand); in SparcTargetLowering()
1751 setOperationAction(ISD::FPOW , MVT::f32, Expand); in SparcTargetLowering()
1753 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); in SparcTargetLowering()
1754 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); in SparcTargetLowering()
1755 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); in SparcTargetLowering()
1758 setOperationAction(ISD::MULHU, MVT::i32, Expand); in SparcTargetLowering()
1759 setOperationAction(ISD::MULHS, MVT::i32, Expand); in SparcTargetLowering()
1760 setOperationAction(ISD::MUL, MVT::i32, Expand); in SparcTargetLowering()
1764 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); in SparcTargetLowering()
1765 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); in SparcTargetLowering()
1768 setOperationAction(ISD::SDIV, MVT::i32, Expand); in SparcTargetLowering()
1771 setOperationAction(ISD::UDIV, MVT::i32, Expand); in SparcTargetLowering()
1779 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); in SparcTargetLowering()
1780 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); in SparcTargetLowering()
1781 setOperationAction(ISD::MULHU, MVT::i64, Expand); in SparcTargetLowering()
1782 setOperationAction(ISD::MULHS, MVT::i64, Expand); in SparcTargetLowering()
1784 setOperationAction(ISD::UMULO, MVT::i64, Custom); in SparcTargetLowering()
1785 setOperationAction(ISD::SMULO, MVT::i64, Custom); in SparcTargetLowering()
1787 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand); in SparcTargetLowering()
1788 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand); in SparcTargetLowering()
1789 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand); in SparcTargetLowering()
1793 setOperationAction(ISD::VASTART , MVT::Other, Custom); in SparcTargetLowering()
1795 setOperationAction(ISD::VAARG , MVT::Other, Custom); in SparcTargetLowering()
1797 setOperationAction(ISD::TRAP , MVT::Other, Legal); in SparcTargetLowering()
1798 setOperationAction(ISD::DEBUGTRAP , MVT::Other, Legal); in SparcTargetLowering()
1801 setOperationAction(ISD::VACOPY , MVT::Other, Expand); in SparcTargetLowering()
1802 setOperationAction(ISD::VAEND , MVT::Other, Expand); in SparcTargetLowering()
1803 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); in SparcTargetLowering()
1804 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); in SparcTargetLowering()
1805 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); in SparcTargetLowering()
1809 setOperationAction(ISD::CTPOP, MVT::i32, in SparcTargetLowering()
1813 setOperationAction(ISD::LOAD, MVT::f128, Legal); in SparcTargetLowering()
1814 setOperationAction(ISD::STORE, MVT::f128, Legal); in SparcTargetLowering()
1816 setOperationAction(ISD::LOAD, MVT::f128, Custom); in SparcTargetLowering()
1817 setOperationAction(ISD::STORE, MVT::f128, Custom); in SparcTargetLowering()
1821 setOperationAction(ISD::FADD, MVT::f128, Legal); in SparcTargetLowering()
1822 setOperationAction(ISD::FSUB, MVT::f128, Legal); in SparcTargetLowering()
1823 setOperationAction(ISD::FMUL, MVT::f128, Legal); in SparcTargetLowering()
1824 setOperationAction(ISD::FDIV, MVT::f128, Legal); in SparcTargetLowering()
1825 setOperationAction(ISD::FSQRT, MVT::f128, Legal); in SparcTargetLowering()
1826 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal); in SparcTargetLowering()
1827 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); in SparcTargetLowering()
1829 setOperationAction(ISD::FNEG, MVT::f128, Legal); in SparcTargetLowering()
1830 setOperationAction(ISD::FABS, MVT::f128, Legal); in SparcTargetLowering()
1832 setOperationAction(ISD::FNEG, MVT::f128, Custom); in SparcTargetLowering()
1833 setOperationAction(ISD::FABS, MVT::f128, Custom); in SparcTargetLowering()
1846 setOperationAction(ISD::FADD, MVT::f128, Custom); in SparcTargetLowering()
1847 setOperationAction(ISD::FSUB, MVT::f128, Custom); in SparcTargetLowering()
1848 setOperationAction(ISD::FMUL, MVT::f128, Custom); in SparcTargetLowering()
1849 setOperationAction(ISD::FDIV, MVT::f128, Custom); in SparcTargetLowering()
1850 setOperationAction(ISD::FSQRT, MVT::f128, Custom); in SparcTargetLowering()
1851 setOperationAction(ISD::FNEG, MVT::f128, Custom); in SparcTargetLowering()
1852 setOperationAction(ISD::FABS, MVT::f128, Custom); in SparcTargetLowering()
1854 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); in SparcTargetLowering()
1855 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in SparcTargetLowering()
1856 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in SparcTargetLowering()
1901 setOperationAction(ISD::FDIV, MVT::f32, Promote); in SparcTargetLowering()
1902 setOperationAction(ISD::FSQRT, MVT::f32, Promote); in SparcTargetLowering()
1906 setOperationAction(ISD::FMUL, MVT::f32, Promote); in SparcTargetLowering()
1914 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom); in SparcTargetLowering()
1916 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in SparcTargetLowering()
1960 return MVT::i32; in getSetCCResultType()
2092 H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, DL, MVT::i32)); in makeAddress()
2101 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, DL, MVT::i32)); in makeAddress()
2165 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); in LowerGlobalTLSAddress()
2195 unsigned ldTF = ((PtrVT == MVT::i64)? SparcMCExpr::VK_Sparc_TLS_IE_LDX in LowerGlobalTLSAddress()
2355 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); in LowerF128Compare()
2362 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); in LowerF128Compare()
2367 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); in LowerF128Compare()
2372 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); in LowerF128Compare()
2377 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); in LowerF128Compare()
2383 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); in LowerF128Compare()
2388 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); in LowerF128Compare()
2395 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); in LowerF128Compare()
2402 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); in LowerF128Compare()
2411 if (Op.getOperand(0).getValueType() == MVT::f64) in LowerF128_FPEXTEND()
2415 if (Op.getOperand(0).getValueType() == MVT::f32) in LowerF128_FPEXTEND()
2427 if (Op.getOperand(0).getValueType() != MVT::f128) in LowerF128_FPROUND()
2430 if (Op.getValueType() == MVT::f64) in LowerF128_FPROUND()
2433 if (Op.getValueType() == MVT::f32) in LowerF128_FPROUND()
2446 assert(VT == MVT::i32 || VT == MVT::i64); in LowerFP_TO_SINT()
2449 if (Op.getOperand(0).getValueType() == MVT::f128 in LowerFP_TO_SINT()
2451 const char *libName = TLI.getLibcallName(VT == MVT::i32 in LowerFP_TO_SINT()
2462 if (VT == MVT::i32) in LowerFP_TO_SINT()
2463 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0)); in LowerFP_TO_SINT()
2465 Op = DAG.getNode(SPISD::FTOX, dl, MVT::f64, Op.getOperand(0)); in LowerFP_TO_SINT()
2475 assert(OpVT == MVT::i32 || (OpVT == MVT::i64)); in LowerSINT_TO_FP()
2477 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64; in LowerSINT_TO_FP()
2480 if (Op.getValueType() == MVT::f128 in LowerSINT_TO_FP()
2482 const char *libName = TLI.getLibcallName(OpVT == MVT::i32 in LowerSINT_TO_FP()
2494 unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF; in LowerSINT_TO_FP()
2506 if (Op.getOperand(0).getValueType() != MVT::f128 || in LowerFP_TO_UINT()
2510 assert(VT == MVT::i32 || VT == MVT::i64); in LowerFP_TO_UINT()
2513 TLI.getLibcallName(VT == MVT::i32 in LowerFP_TO_UINT()
2524 assert(OpVT == MVT::i32 || OpVT == MVT::i64); in LowerUINT_TO_FP()
2528 if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(OpVT))) in LowerUINT_TO_FP()
2532 TLI.getLibcallName(OpVT == MVT::i32 in LowerUINT_TO_FP()
2556 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS); in LowerBR_CC()
2559 Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC; in LowerBR_CC()
2561 if (!hasHardQuad && LHS.getValueType() == MVT::f128) { in LowerBR_CC()
2566 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS); in LowerBR_CC()
2571 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest, in LowerBR_CC()
2572 DAG.getConstant(SPCC, dl, MVT::i32), CompareFlag); in LowerBR_CC()
2592 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS); in LowerSELECT_CC()
2593 Opc = LHS.getValueType() == MVT::i32 ? in LowerSELECT_CC()
2597 if (!hasHardQuad && LHS.getValueType() == MVT::f128) { in LowerSELECT_CC()
2602 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS); in LowerSELECT_CC()
2608 DAG.getConstant(SPCC, dl, MVT::i32), CompareFlag); in LowerSELECT_CC()
2723 dl, MVT::Other, DAG.getEntryNode()); in getFLUSHW()
2806 assert(SrcReg64.getValueType() == MVT::f64 && "LowerF64Op called on non-double!"); in LowerF64Op()
2818 SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32, in LowerF64Op()
2820 SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32, in LowerF64Op()
2824 Lo32 = DAG.getNode(opcode, dl, MVT::f32, Lo32); in LowerF64Op()
2826 Hi32 = DAG.getNode(opcode, dl, MVT::f32, Hi32); in LowerF64Op()
2829 dl, MVT::f64), 0); in LowerF64Op()
2830 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64, in LowerF64Op()
2832 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64, in LowerF64Op()
2847 DAG.getLoad(MVT::f64, dl, LdNode->getChain(), LdNode->getBasePtr(), in LowerF128Load()
2853 SDValue Lo64 = DAG.getLoad(MVT::f64, dl, LdNode->getChain(), LoPtr, in LowerF128Load()
2857 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32); in LowerF128Load()
2858 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32); in LowerF128Load()
2861 dl, MVT::f128); in LowerF128Load()
2863 MVT::f128, in LowerF128Load()
2868 MVT::f128, in LowerF128Load()
2874 SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); in LowerF128Load()
2884 if (MemVT == MVT::f128) in LowerLOAD()
2896 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32); in LowerF128Store()
2897 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32); in LowerF128Store()
2901 MVT::f64, in LowerF128Store()
2906 MVT::f64, in LowerF128Store()
2924 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); in LowerF128Store()
2933 if (MemVT == MVT::f128) in LowerSTORE()
2936 if (MemVT == MVT::i64) { in LowerSTORE()
2939 SDValue Val = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, St->getValue()); in LowerSTORE()
2956 if (Op.getValueType() == MVT::f64) in LowerFNEGorFABS()
2958 if (Op.getValueType() != MVT::f128) in LowerFNEGorFABS()
2967 SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64, in LowerFNEGorFABS()
2969 SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64, in LowerFNEGorFABS()
2974 Lo64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Lo64); in LowerFNEGorFABS()
2979 Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64); in LowerFNEGorFABS()
2985 dl, MVT::f128), 0); in LowerFNEGorFABS()
2986 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128, in LowerFNEGorFABS()
2988 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128, in LowerFNEGorFABS()
2995 if (Op.getValueType() != MVT::i64) in LowerADDC_ADDE_SUBC_SUBE()
3000 SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1); in LowerADDC_ADDE_SUBC_SUBE()
3001 SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1, in LowerADDC_ADDE_SUBC_SUBE()
3002 DAG.getConstant(32, dl, MVT::i64)); in LowerADDC_ADDE_SUBC_SUBE()
3003 Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi); in LowerADDC_ADDE_SUBC_SUBE()
3006 SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2); in LowerADDC_ADDE_SUBC_SUBE()
3007 SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2, in LowerADDC_ADDE_SUBC_SUBE()
3008 DAG.getConstant(32, dl, MVT::i64)); in LowerADDC_ADDE_SUBC_SUBE()
3009 Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi); in LowerADDC_ADDE_SUBC_SUBE()
3022 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Glue); in LowerADDC_ADDE_SUBC_SUBE()
3032 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo); in LowerADDC_ADDE_SUBC_SUBE()
3033 Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi); in LowerADDC_ADDE_SUBC_SUBE()
3034 Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi, in LowerADDC_ADDE_SUBC_SUBE()
3035 DAG.getConstant(32, dl, MVT::i64)); in LowerADDC_ADDE_SUBC_SUBE()
3037 SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo); in LowerADDC_ADDE_SUBC_SUBE()
3051 EVT VT = MVT::i64; in LowerUMULO_SMULO()
3052 EVT WideVT = MVT::i128; in LowerUMULO_SMULO()
3065 HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt); in LowerUMULO_SMULO()
3068 HiRHS = DAG.getConstant(0, dl, MVT::i64); in LowerUMULO_SMULO()
3084 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE); in LowerUMULO_SMULO()
3086 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, DAG.getConstant(0, dl, VT), in LowerUMULO_SMULO()
3188 SDValue Lo = DAG.getConstant(V.zextOrTrunc(32), DL, MVT::i32); in bitcastConstantFPToInt()
3189 SDValue Hi = DAG.getConstant(V.lshr(32).zextOrTrunc(32), DL, MVT::i32); in bitcastConstantFPToInt()
3192 return DAG.getBuildVector(MVT::v2i32, DL, {Hi, Lo}); in bitcastConstantFPToInt()
3200 if (isa<ConstantFPSDNode>(Src) && N->getSimpleValueType(0) == MVT::v2i32 && in PerformBITCASTCombine()
3201 Src.getSimpleValueType() == MVT::f64) in PerformBITCASTCombine()
3382 MVT VT) const { in getRegForInlineAsmConstraint()
3389 if (VT == MVT::v2i32) in getRegForInlineAsmConstraint()
3396 if (VT == MVT::f32 || VT == MVT::i32) in getRegForInlineAsmConstraint()
3398 else if (VT == MVT::f64 || VT == MVT::i64) in getRegForInlineAsmConstraint()
3400 else if (VT == MVT::f128) in getRegForInlineAsmConstraint()
3405 if (VT == MVT::f32 || VT == MVT::i32) in getRegForInlineAsmConstraint()
3407 else if (VT == MVT::f64 || VT == MVT::i64 ) in getRegForInlineAsmConstraint()
3409 else if (VT == MVT::f128) in getRegForInlineAsmConstraint()
3442 if (VT != MVT::f32 && VT != MVT::Other && RegName[0] == 'f' && in getRegForInlineAsmConstraint()
3444 if (VT == MVT::f64 && (RegNo % 2 == 0)) { in getRegForInlineAsmConstraint()
3447 } else if (VT == MVT::f128 && (RegNo % 4 == 0)) { in getRegForInlineAsmConstraint()
3461 if (Subtarget->is64Bit() && VT == MVT::i64) { in getRegForInlineAsmConstraint()
3491 if (N->getOperand(0).getValueType() != MVT::f128 in ReplaceNodeResults()
3492 || N->getValueType(0) != MVT::i64) in ReplaceNodeResults()
3505 SDValue Lo = DAG.getCopyFromReg(N->getOperand(0), dl, SP::ASR23, MVT::i32); in ReplaceNodeResults()
3506 SDValue Hi = DAG.getCopyFromReg(Lo, dl, SP::G0, MVT::i32); in ReplaceNodeResults()
3508 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops); in ReplaceNodeResults()
3516 if (N->getValueType(0) != MVT::f128 in ReplaceNodeResults()
3517 || N->getOperand(0).getValueType() != MVT::i64) in ReplaceNodeResults()
3533 if (Ld->getValueType(0) != MVT::i64 || Ld->getMemoryVT() != MVT::i64) in ReplaceNodeResults()
3538 Ld->getExtensionType(), dl, MVT::v2i32, Ld->getChain(), in ReplaceNodeResults()
3539 Ld->getBasePtr(), Ld->getPointerInfo(), MVT::v2i32, in ReplaceNodeResults()
3543 SDValue Res = DAG.getNode(ISD::BITCAST, dl, MVT::i64, LoadRes); in ReplaceNodeResults()