Lines Matching refs:MVT
183 bool isTypeLegal(Type *Ty, MVT &VT);
184 bool isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed = false);
188 bool simplifyAddress(Address &Addr, MVT VT);
197 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
202 unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
205 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
208 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
211 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
215 unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
223 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
224 bool emitICmp_ri(MVT RetVT, unsigned LHSReg, uint64_t Imm);
225 bool emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS);
226 unsigned emitLoad(MVT VT, MVT ResultVT, Address Addr, bool WantZExt = true,
228 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
230 bool emitStoreRelease(MVT VT, unsigned SrcReg, unsigned AddrReg,
232 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
233 unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
234 unsigned emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,
237 unsigned emitAdd_ri_(MVT VT, unsigned Op0, int64_t Imm);
238 unsigned emitSub(MVT RetVT, const Value *LHS, const Value *RHS,
241 unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, unsigned RHSReg,
243 unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, unsigned RHSReg,
246 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
248 unsigned emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
250 unsigned emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
252 unsigned emitAnd_ri(MVT RetVT, unsigned LHSReg, uint64_t Imm);
253 unsigned emitMul_rr(MVT RetVT, unsigned Op0, unsigned Op1);
254 unsigned emitSMULL_rr(MVT RetVT, unsigned Op0, unsigned Op1);
255 unsigned emitUMULL_rr(MVT RetVT, unsigned Op0, unsigned Op1);
256 unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, unsigned Op1Reg);
257 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
259 unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, unsigned Op1Reg);
260 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
262 unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, unsigned Op1Reg);
263 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
266 unsigned materializeInt(const ConstantInt *CI, MVT VT);
267 unsigned materializeFP(const ConstantFP *CFP, MVT VT);
273 bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
275 bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
318 static unsigned getImplicitScaleFactor(MVT VT) { in getImplicitScaleFactor()
322 case MVT::i1: // fall-through in getImplicitScaleFactor()
323 case MVT::i8: in getImplicitScaleFactor()
325 case MVT::i16: in getImplicitScaleFactor()
327 case MVT::i32: // fall-through in getImplicitScaleFactor()
328 case MVT::f32: in getImplicitScaleFactor()
330 case MVT::i64: // fall-through in getImplicitScaleFactor()
331 case MVT::f64: in getImplicitScaleFactor()
347 assert(TLI.getValueType(DL, AI->getType(), true) == MVT::i64 && in fastMaterializeAlloca()
370 unsigned AArch64FastISel::materializeInt(const ConstantInt *CI, MVT VT) { in materializeInt()
371 if (VT > MVT::i64) in materializeInt()
378 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass in materializeInt()
380 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in materializeInt()
387 unsigned AArch64FastISel::materializeFP(const ConstantFP *CFP, MVT VT) { in materializeFP()
393 if (VT != MVT::f32 && VT != MVT::f64) in materializeFP()
397 bool Is64Bit = (VT == MVT::f64); in materializeFP()
516 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant()
520 assert(VT == MVT::i64 && "Expected 64-bit pointers"); in fastMaterializeConstant()
537 MVT VT; in fastMaterializeFloatZero()
541 if (VT != MVT::f32 && VT != MVT::f64) in fastMaterializeFloatZero()
544 bool Is64Bit = (VT == MVT::f64); in fastMaterializeFloatZero()
757 Reg = fastEmitInst_extractsubreg(MVT::i32, Reg, AArch64::sub_32); in computeAddress()
853 Reg = fastEmitInst_extractsubreg(MVT::i32, Reg, AArch64::sub_32); in computeAddress()
958 bool AArch64FastISel::isTypeLegal(Type *Ty, MVT &VT) { in isTypeLegal()
965 if (evt == MVT::Other || !evt.isSimple()) in isTypeLegal()
970 if (VT == MVT::f128) in isTypeLegal()
982 bool AArch64FastISel::isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed) { in isTypeSupported()
991 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16) in isTypeSupported()
1005 bool AArch64FastISel::simplifyAddress(Address &Addr, MVT VT) { in simplifyAddress()
1052 ResultReg = emitAddSub_rx(/*UseAdd=*/true, MVT::i64, Addr.getReg(), in simplifyAddress()
1056 ResultReg = emitAddSub_rs(/*UseAdd=*/true, MVT::i64, Addr.getReg(), in simplifyAddress()
1061 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(), in simplifyAddress()
1064 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(), in simplifyAddress()
1067 ResultReg = emitLSL_ri(MVT::i64, MVT::i64, Addr.getOffsetReg(), in simplifyAddress()
1085 ResultReg = emitAdd_ri_(MVT::i64, Addr.getReg(), Offset); in simplifyAddress()
1087 ResultReg = fastEmit_i(MVT::i64, MVT::i64, ISD::Constant, Offset); in simplifyAddress()
1137 unsigned AArch64FastISel::emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS, in emitAddSub()
1145 case MVT::i1: in emitAddSub()
1148 case MVT::i8: in emitAddSub()
1152 case MVT::i16: in emitAddSub()
1156 case MVT::i32: // fall-through in emitAddSub()
1157 case MVT::i64: in emitAddSub()
1160 MVT SrcVT = RetVT; in emitAddSub()
1161 RetVT.SimpleTy = std::max(RetVT.SimpleTy, MVT::i32); in emitAddSub()
1280 unsigned AArch64FastISel::emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_rr()
1289 if (RetVT != MVT::i32 && RetVT != MVT::i64) in emitAddSub_rr()
1298 bool Is64Bit = RetVT == MVT::i64; in emitAddSub_rr()
1317 unsigned AArch64FastISel::emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_ri()
1322 if (RetVT != MVT::i32 && RetVT != MVT::i64) in emitAddSub_ri()
1340 bool Is64Bit = RetVT == MVT::i64; in emitAddSub_ri()
1362 unsigned AArch64FastISel::emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_rs()
1371 if (RetVT != MVT::i32 && RetVT != MVT::i64) in emitAddSub_rs()
1384 bool Is64Bit = RetVT == MVT::i64; in emitAddSub_rs()
1404 unsigned AArch64FastISel::emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_rx()
1413 if (RetVT != MVT::i32 && RetVT != MVT::i64) in emitAddSub_rx()
1425 bool Is64Bit = RetVT == MVT::i64; in emitAddSub_rx()
1453 MVT VT = EVT.getSimpleVT(); in emitCmp()
1458 case MVT::i1: in emitCmp()
1459 case MVT::i8: in emitCmp()
1460 case MVT::i16: in emitCmp()
1461 case MVT::i32: in emitCmp()
1462 case MVT::i64: in emitCmp()
1464 case MVT::f32: in emitCmp()
1465 case MVT::f64: in emitCmp()
1470 bool AArch64FastISel::emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, in emitICmp()
1476 bool AArch64FastISel::emitICmp_ri(MVT RetVT, unsigned LHSReg, uint64_t Imm) { in emitICmp_ri()
1481 bool AArch64FastISel::emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS) { in emitFCmp()
1482 if (RetVT != MVT::f32 && RetVT != MVT::f64) in emitFCmp()
1497 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDri : AArch64::FCMPSri; in emitFCmp()
1507 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDrr : AArch64::FCMPSrr; in emitFCmp()
1514 unsigned AArch64FastISel::emitAdd(MVT RetVT, const Value *LHS, const Value *RHS, in emitAdd()
1525 unsigned AArch64FastISel::emitAdd_ri_(MVT VT, unsigned Op0, int64_t Imm) { in emitAdd_ri_()
1543 unsigned AArch64FastISel::emitSub(MVT RetVT, const Value *LHS, const Value *RHS, in emitSub()
1549 unsigned AArch64FastISel::emitSubs_rr(MVT RetVT, unsigned LHSReg, in emitSubs_rr()
1555 unsigned AArch64FastISel::emitSubs_rs(MVT RetVT, unsigned LHSReg, in emitSubs_rs()
1563 unsigned AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT, in emitLogicalOp()
1632 MVT VT = std::max(MVT::i32, RetVT.SimpleTy); in emitLogicalOp()
1634 if (RetVT >= MVT::i8 && RetVT <= MVT::i16) { in emitLogicalOp()
1635 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff; in emitLogicalOp()
1636 ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask); in emitLogicalOp()
1641 unsigned AArch64FastISel::emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, in emitLogicalOp_ri()
1656 case MVT::i1: in emitLogicalOp_ri()
1657 case MVT::i8: in emitLogicalOp_ri()
1658 case MVT::i16: in emitLogicalOp_ri()
1659 case MVT::i32: { in emitLogicalOp_ri()
1666 case MVT::i64: in emitLogicalOp_ri()
1679 if (RetVT >= MVT::i8 && RetVT <= MVT::i16 && ISDOpc != ISD::AND) { in emitLogicalOp_ri()
1680 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff; in emitLogicalOp_ri()
1681 ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask); in emitLogicalOp_ri()
1686 unsigned AArch64FastISel::emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, in emitLogicalOp_rs()
1706 case MVT::i1: in emitLogicalOp_rs()
1707 case MVT::i8: in emitLogicalOp_rs()
1708 case MVT::i16: in emitLogicalOp_rs()
1709 case MVT::i32: in emitLogicalOp_rs()
1713 case MVT::i64: in emitLogicalOp_rs()
1721 if (RetVT >= MVT::i8 && RetVT <= MVT::i16) { in emitLogicalOp_rs()
1722 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff; in emitLogicalOp_rs()
1723 ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask); in emitLogicalOp_rs()
1728 unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg, in emitAnd_ri()
1733 unsigned AArch64FastISel::emitLoad(MVT VT, MVT RetVT, Address Addr, in emitLoad()
1809 bool IsRet64Bit = RetVT == MVT::i64; in emitLoad()
1813 case MVT::i1: // Intentional fall-through. in emitLoad()
1814 case MVT::i8: in emitLoad()
1819 case MVT::i16: in emitLoad()
1824 case MVT::i32: in emitLoad()
1829 case MVT::i64: in emitLoad()
1833 case MVT::f32: in emitLoad()
1837 case MVT::f64: in emitLoad()
1850 if (VT == MVT::i1) { in emitLoad()
1851 unsigned ANDReg = emitAnd_ri(MVT::i32, ResultReg, 1); in emitLoad()
1858 if (WantZExt && RetVT == MVT::i64 && VT <= MVT::i32) { in emitLoad()
1871 MVT VT; in selectAddSub()
1897 MVT VT; in selectLogicalOp()
1926 MVT VT; in selectLoad()
1956 MVT RetVT = VT; in selectLoad()
1997 if (RetVT == MVT::i64 && VT <= MVT::i32) { in selectLoad()
2004 ResultReg = fastEmitInst_extractsubreg(MVT::i32, ResultReg, in selectLoad()
2036 bool AArch64FastISel::emitStoreRelease(MVT VT, unsigned SrcReg, in emitStoreRelease()
2042 case MVT::i8: Opc = AArch64::STLRB; break; in emitStoreRelease()
2043 case MVT::i16: Opc = AArch64::STLRH; break; in emitStoreRelease()
2044 case MVT::i32: Opc = AArch64::STLRW; break; in emitStoreRelease()
2045 case MVT::i64: Opc = AArch64::STLRX; break; in emitStoreRelease()
2058 bool AArch64FastISel::emitStore(MVT VT, unsigned SrcReg, Address Addr, in emitStore()
2101 case MVT::i1: VTIsi1 = true; LLVM_FALLTHROUGH; in emitStore()
2102 case MVT::i8: Opc = OpcTable[Idx][0]; break; in emitStore()
2103 case MVT::i16: Opc = OpcTable[Idx][1]; break; in emitStore()
2104 case MVT::i32: Opc = OpcTable[Idx][2]; break; in emitStore()
2105 case MVT::i64: Opc = OpcTable[Idx][3]; break; in emitStore()
2106 case MVT::f32: Opc = OpcTable[Idx][4]; break; in emitStore()
2107 case MVT::f64: Opc = OpcTable[Idx][5]; break; in emitStore()
2112 unsigned ANDReg = emitAnd_ri(MVT::i32, SrcReg, 1); in emitStore()
2127 MVT VT; in selectStore()
2155 SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in selectStore()
2158 VT = MVT::getIntegerVT(VT.getSizeInBits()); in selectStore()
2159 SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in selectStore()
2255 MVT VT; in emitCompareAndBranch()
2301 if (VT == MVT::i1) in emitCompareAndBranch()
2347 SrcReg = fastEmitInst_extractsubreg(MVT::i32, SrcReg, AArch64::sub_32); in emitCompareAndBranch()
2350 SrcReg = emitIntExt(VT, SrcReg, MVT::i32, /*isZExt=*/true); in emitCompareAndBranch()
2532 ResultReg = fastEmit_i(MVT::i32, MVT::i32, ISD::Constant, 1); in selectCmp()
2642 Src1Reg = emitLogicalOp_ri(ISD::XOR, MVT::i32, Src1Reg, 1); in optimizeSelect()
2652 MVT VT; in selectSelect()
2661 case MVT::i1: in selectSelect()
2662 case MVT::i8: in selectSelect()
2663 case MVT::i16: in selectSelect()
2664 case MVT::i32: in selectSelect()
2668 case MVT::i64: in selectSelect()
2672 case MVT::f32: in selectSelect()
2676 case MVT::f64: in selectSelect()
2804 MVT DestVT; in selectFPToInt()
2813 if (SrcVT == MVT::f128 || SrcVT == MVT::f16) in selectFPToInt()
2817 if (SrcVT == MVT::f64) { in selectFPToInt()
2819 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr; in selectFPToInt()
2821 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr; in selectFPToInt()
2824 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr; in selectFPToInt()
2826 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr; in selectFPToInt()
2829 DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass); in selectFPToInt()
2837 MVT DestVT; in selectIntToFP()
2841 if (DestVT == MVT::f16) in selectIntToFP()
2844 assert((DestVT == MVT::f32 || DestVT == MVT::f64) && in selectIntToFP()
2854 if (SrcVT == MVT::i16 || SrcVT == MVT::i8 || SrcVT == MVT::i1) { in selectIntToFP()
2856 emitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed); in selectIntToFP()
2862 if (SrcVT == MVT::i64) { in selectIntToFP()
2864 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUXSri : AArch64::SCVTFUXDri; in selectIntToFP()
2866 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUXSri : AArch64::UCVTFUXDri; in selectIntToFP()
2869 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUWSri : AArch64::SCVTFUWDri; in selectIntToFP()
2871 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUWSri : AArch64::UCVTFUWDri; in selectIntToFP()
2915 MVT VT = ArgVT.getSimpleVT().SimpleTy; in fastLowerArguments()
2923 if (VT >= MVT::i1 && VT <= MVT::i64) in fastLowerArguments()
2925 else if ((VT >= MVT::f16 && VT <= MVT::f64) || VT.is64BitVector() || in fastLowerArguments()
2953 MVT VT = TLI.getSimpleValueType(DL, Arg.getType()); in fastLowerArguments()
2956 if (VT >= MVT::i1 && VT <= MVT::i32) { in fastLowerArguments()
2959 VT = MVT::i32; in fastLowerArguments()
2960 } else if (VT == MVT::i64) { in fastLowerArguments()
2963 } else if (VT == MVT::f16) { in fastLowerArguments()
2966 } else if (VT == MVT::f32) { in fastLowerArguments()
2969 } else if ((VT == MVT::f64) || VT.is64BitVector()) { in fastLowerArguments()
2992 SmallVectorImpl<MVT> &OutVTs, in processCallArgs()
3010 MVT ArgVT = OutVTs[VA.getValNo()]; in processCallArgs()
3021 MVT DestVT = VA.getLocVT(); in processCallArgs()
3022 MVT SrcVT = ArgVT; in processCallArgs()
3031 MVT DestVT = VA.getLocVT(); in processCallArgs()
3032 MVT SrcVT = ArgVT; in processCallArgs()
3081 bool AArch64FastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT, in finishCall()
3091 if (RetVT != MVT::isVoid) { in finishCall()
3101 MVT CopyVT = RVLocs[0].getValVT(); in finishCall()
3160 MVT RetVT; in fastLowerCall()
3162 RetVT = MVT::isVoid; in fastLowerCall()
3172 SmallVector<MVT, 16> OutVTs; in fastLowerCall()
3176 MVT VT; in fastLowerCall()
3178 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)) in fastLowerCall()
3282 MVT VT; in tryEmitSmallMemCpy()
3285 VT = MVT::i64; in tryEmitSmallMemCpy()
3287 VT = MVT::i32; in tryEmitSmallMemCpy()
3289 VT = MVT::i16; in tryEmitSmallMemCpy()
3291 VT = MVT::i8; in tryEmitSmallMemCpy()
3296 VT = MVT::i32; in tryEmitSmallMemCpy()
3298 VT = MVT::i16; in tryEmitSmallMemCpy()
3300 VT = MVT::i8; in tryEmitSmallMemCpy()
3336 MVT RetVT; in foldXALUIntrinsic()
3343 if (RetVT != MVT::i32 && RetVT != MVT::i64) in foldXALUIntrinsic()
3514 MVT RetVT; in fastLowerIntrinsicCall()
3518 if (RetVT != MVT::f32 && RetVT != MVT::f64) in fastLowerIntrinsicCall()
3527 bool Is64Bit = RetVT == MVT::f64; in fastLowerIntrinsicCall()
3563 MVT VT; in fastLowerIntrinsicCall()
3571 case MVT::f32: in fastLowerIntrinsicCall()
3574 case MVT::f64: in fastLowerIntrinsicCall()
3599 MVT VT; in fastLowerIntrinsicCall()
3625 MVT VT; in fastLowerIntrinsicCall()
3629 if (VT != MVT::i32 && VT != MVT::i64) in fastLowerIntrinsicCall()
3689 if (VT == MVT::i32) { in fastLowerIntrinsicCall()
3690 MulReg = emitSMULL_rr(MVT::i64, LHSReg, RHSReg); in fastLowerIntrinsicCall()
3694 emitAddSub_rx(/*UseAdd=*/false, MVT::i64, MulReg, MulSubReg, in fastLowerIntrinsicCall()
3699 assert(VT == MVT::i64 && "Unexpected value type."); in fastLowerIntrinsicCall()
3719 if (VT == MVT::i32) { in fastLowerIntrinsicCall()
3720 MulReg = emitUMULL_rr(MVT::i64, LHSReg, RHSReg); in fastLowerIntrinsicCall()
3728 assert(VT == MVT::i64 && "Unexpected value type."); in fastLowerIntrinsicCall()
3828 MVT RVVT = RVEVT.getSimpleVT(); in selectRet()
3829 if (RVVT == MVT::f128) in selectRet()
3832 MVT DestVT = VA.getValVT(); in selectRet()
3835 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16) in selectRet()
3850 SrcReg = emitAnd_ri(MVT::i64, SrcReg, 0xffffffff); in selectRet()
3879 MVT SrcVT = SrcEVT.getSimpleVT(); in selectTrunc()
3880 MVT DestVT = DestEVT.getSimpleVT(); in selectTrunc()
3882 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 && in selectTrunc()
3883 SrcVT != MVT::i8) in selectTrunc()
3885 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8 && in selectTrunc()
3886 DestVT != MVT::i1) in selectTrunc()
3899 if (SrcVT == MVT::i64) { in selectTrunc()
3905 case MVT::i1: in selectTrunc()
3908 case MVT::i8: in selectTrunc()
3911 case MVT::i16: in selectTrunc()
3916 Register Reg32 = fastEmitInst_extractsubreg(MVT::i32, SrcReg, in selectTrunc()
3919 ResultReg = emitAnd_ri(MVT::i32, Reg32, Mask); in selectTrunc()
3932 unsigned AArch64FastISel::emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) { in emiti1Ext()
3933 assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 || in emiti1Ext()
3934 DestVT == MVT::i64) && in emiti1Ext()
3937 if (DestVT == MVT::i8 || DestVT == MVT::i16) in emiti1Ext()
3938 DestVT = MVT::i32; in emiti1Ext()
3941 unsigned ResultReg = emitAnd_ri(MVT::i32, SrcReg, 1); in emiti1Ext()
3943 if (DestVT == MVT::i64) { in emiti1Ext()
3956 if (DestVT == MVT::i64) { in emiti1Ext()
3965 unsigned AArch64FastISel::emitMul_rr(MVT RetVT, unsigned Op0, unsigned Op1) { in emitMul_rr()
3969 case MVT::i8: in emitMul_rr()
3970 case MVT::i16: in emitMul_rr()
3971 case MVT::i32: in emitMul_rr()
3972 RetVT = MVT::i32; in emitMul_rr()
3974 case MVT::i64: in emitMul_rr()
3979 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitMul_rr()
3983 unsigned AArch64FastISel::emitSMULL_rr(MVT RetVT, unsigned Op0, unsigned Op1) { in emitSMULL_rr()
3984 if (RetVT != MVT::i64) in emitSMULL_rr()
3991 unsigned AArch64FastISel::emitUMULL_rr(MVT RetVT, unsigned Op0, unsigned Op1) { in emitUMULL_rr()
3992 if (RetVT != MVT::i64) in emitUMULL_rr()
3999 unsigned AArch64FastISel::emitLSL_rr(MVT RetVT, unsigned Op0Reg, in emitLSL_rr()
4006 case MVT::i8: Opc = AArch64::LSLVWr; NeedTrunc = true; Mask = 0xff; break; in emitLSL_rr()
4007 case MVT::i16: Opc = AArch64::LSLVWr; NeedTrunc = true; Mask = 0xffff; break; in emitLSL_rr()
4008 case MVT::i32: Opc = AArch64::LSLVWr; break; in emitLSL_rr()
4009 case MVT::i64: Opc = AArch64::LSLVXr; break; in emitLSL_rr()
4013 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitLSL_rr()
4015 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Mask); in emitLSL_rr()
4019 ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask); in emitLSL_rr()
4023 unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0, in emitLSL_ri()
4027 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 || in emitLSL_ri()
4028 SrcVT == MVT::i32 || SrcVT == MVT::i64) && in emitLSL_ri()
4030 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 || in emitLSL_ri()
4031 RetVT == MVT::i64) && "Unexpected return value type."); in emitLSL_ri()
4033 bool Is64Bit = (RetVT == MVT::i64); in emitLSL_ri()
4089 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) { in emitLSL_ri()
4101 unsigned AArch64FastISel::emitLSR_rr(MVT RetVT, unsigned Op0Reg, in emitLSR_rr()
4108 case MVT::i8: Opc = AArch64::LSRVWr; NeedTrunc = true; Mask = 0xff; break; in emitLSR_rr()
4109 case MVT::i16: Opc = AArch64::LSRVWr; NeedTrunc = true; Mask = 0xffff; break; in emitLSR_rr()
4110 case MVT::i32: Opc = AArch64::LSRVWr; break; in emitLSR_rr()
4111 case MVT::i64: Opc = AArch64::LSRVXr; break; in emitLSR_rr()
4115 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitLSR_rr()
4117 Op0Reg = emitAnd_ri(MVT::i32, Op0Reg, Mask); in emitLSR_rr()
4118 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Mask); in emitLSR_rr()
4122 ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask); in emitLSR_rr()
4126 unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, in emitLSR_ri()
4130 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 || in emitLSR_ri()
4131 SrcVT == MVT::i32 || SrcVT == MVT::i64) && in emitLSR_ri()
4133 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 || in emitLSR_ri()
4134 RetVT == MVT::i64) && "Unexpected return value type."); in emitLSR_ri()
4136 bool Is64Bit = (RetVT == MVT::i64); in emitLSR_ri()
4205 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) { in emitLSR_ri()
4217 unsigned AArch64FastISel::emitASR_rr(MVT RetVT, unsigned Op0Reg, in emitASR_rr()
4224 case MVT::i8: Opc = AArch64::ASRVWr; NeedTrunc = true; Mask = 0xff; break; in emitASR_rr()
4225 case MVT::i16: Opc = AArch64::ASRVWr; NeedTrunc = true; Mask = 0xffff; break; in emitASR_rr()
4226 case MVT::i32: Opc = AArch64::ASRVWr; break; in emitASR_rr()
4227 case MVT::i64: Opc = AArch64::ASRVXr; break; in emitASR_rr()
4231 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitASR_rr()
4233 Op0Reg = emitIntExt(RetVT, Op0Reg, MVT::i32, /*isZExt=*/false); in emitASR_rr()
4234 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Mask); in emitASR_rr()
4238 ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask); in emitASR_rr()
4242 unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, in emitASR_ri()
4246 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 || in emitASR_ri()
4247 SrcVT == MVT::i32 || SrcVT == MVT::i64) && in emitASR_ri()
4249 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 || in emitASR_ri()
4250 RetVT == MVT::i64) && "Unexpected return value type."); in emitASR_ri()
4252 bool Is64Bit = (RetVT == MVT::i64); in emitASR_ri()
4310 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) { in emitASR_ri()
4322 unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntExt()
4324 assert(DestVT != MVT::i1 && "ZeroExt/SignExt an i1?"); in emitIntExt()
4330 if (((DestVT != MVT::i8) && (DestVT != MVT::i16) && in emitIntExt()
4331 (DestVT != MVT::i32) && (DestVT != MVT::i64)) || in emitIntExt()
4332 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && in emitIntExt()
4333 (SrcVT != MVT::i16) && (SrcVT != MVT::i32))) in emitIntExt()
4342 case MVT::i1: in emitIntExt()
4344 case MVT::i8: in emitIntExt()
4345 if (DestVT == MVT::i64) in emitIntExt()
4351 case MVT::i16: in emitIntExt()
4352 if (DestVT == MVT::i64) in emitIntExt()
4358 case MVT::i32: in emitIntExt()
4359 assert(DestVT == MVT::i64 && "IntExt i32 to i32?!?"); in emitIntExt()
4366 if (DestVT == MVT::i8 || DestVT == MVT::i16) in emitIntExt()
4367 DestVT = MVT::i32; in emitIntExt()
4368 else if (DestVT == MVT::i64) { in emitIntExt()
4379 (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitIntExt()
4431 bool AArch64FastISel::optimizeIntExtLoad(const Instruction *I, MVT RetVT, in optimizeIntExtLoad()
4432 MVT SrcVT) { in optimizeIntExtLoad()
4460 if (RetVT != MVT::i64 || SrcVT > MVT::i32) { in optimizeIntExtLoad()
4488 MVT RetVT; in selectIntExt()
4489 MVT SrcVT; in selectIntExt()
4508 if (RetVT == MVT::i64 && SrcVT != MVT::i64) { in selectIntExt()
4536 MVT DestVT = DestEVT.getSimpleVT(); in selectRem()
4537 if (DestVT != MVT::i64 && DestVT != MVT::i32) in selectRem()
4541 bool Is64bit = (DestVT == MVT::i64); in selectRem()
4562 (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in selectRem()
4573 MVT VT; in selectMul()
4590 MVT SrcVT = VT; in selectMul()
4594 MVT VT; in selectMul()
4603 MVT VT; in selectMul()
4643 MVT RetVT; in selectShift()
4653 MVT SrcVT = RetVT; in selectShift()
4658 MVT TmpVT; in selectShift()
4667 MVT TmpVT; in selectShift()
4729 MVT RetVT, SrcVT; in selectBitCast()
4737 if (RetVT == MVT::f32 && SrcVT == MVT::i32) in selectBitCast()
4739 else if (RetVT == MVT::f64 && SrcVT == MVT::i64) in selectBitCast()
4741 else if (RetVT == MVT::i32 && SrcVT == MVT::f32) in selectBitCast()
4743 else if (RetVT == MVT::i64 && SrcVT == MVT::f64) in selectBitCast()
4751 case MVT::i32: RC = &AArch64::GPR32RegClass; break; in selectBitCast()
4752 case MVT::i64: RC = &AArch64::GPR64RegClass; break; in selectBitCast()
4753 case MVT::f32: RC = &AArch64::FPR32RegClass; break; in selectBitCast()
4754 case MVT::f64: RC = &AArch64::FPR64RegClass; break; in selectBitCast()
4769 MVT RetVT; in selectFRem()
4777 case MVT::f32: in selectFRem()
4780 case MVT::f64: in selectFRem()
4807 MVT VT; in selectSDiv()
4815 if ((VT != MVT::i32 && VT != MVT::i64) || !C || in selectSDiv()
4843 if (VT == MVT::i64) { in selectSDiv()
4857 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in selectSDiv()
4882 MVT PtrVT = TLI.getPointerTy(DL); in getRegForGEPIndex()
4906 MVT VT = TLI.getPointerTy(DL); in selectGetElementPtr()
4971 MVT VT; in selectAtomicCmpXchg()
4979 if (VT == MVT::i32) { in selectAtomicCmpXchg()
4983 } else if (VT == MVT::i64) { in selectAtomicCmpXchg()
5013 .addDef(VT == MVT::i32 ? AArch64::WZR : AArch64::XZR) in selectAtomicCmpXchg()