Lines Matching refs:MVT
48 auto MVTPtr = Subtarget->hasAddr64() ? MVT::i64 : MVT::i32; in WebAssemblyTargetLowering()
60 addRegisterClass(MVT::i32, &WebAssembly::I32RegClass); in WebAssemblyTargetLowering()
61 addRegisterClass(MVT::i64, &WebAssembly::I64RegClass); in WebAssemblyTargetLowering()
62 addRegisterClass(MVT::f32, &WebAssembly::F32RegClass); in WebAssemblyTargetLowering()
63 addRegisterClass(MVT::f64, &WebAssembly::F64RegClass); in WebAssemblyTargetLowering()
65 addRegisterClass(MVT::v16i8, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
66 addRegisterClass(MVT::v8i16, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
67 addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
68 addRegisterClass(MVT::v4f32, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
69 addRegisterClass(MVT::v2i64, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
70 addRegisterClass(MVT::v2f64, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
73 addRegisterClass(MVT::externref, &WebAssembly::EXTERNREFRegClass); in WebAssemblyTargetLowering()
74 addRegisterClass(MVT::funcref, &WebAssembly::FUNCREFRegClass); in WebAssemblyTargetLowering()
81 for (auto T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64}) { in WebAssemblyTargetLowering()
86 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, in WebAssemblyTargetLowering()
87 MVT::v2f64}) { in WebAssemblyTargetLowering()
95 for (auto T : {MVT::externref, MVT::funcref, MVT::Other}) { in WebAssemblyTargetLowering()
106 setOperationAction(ISD::BRIND, MVT::Other, Custom); in WebAssemblyTargetLowering()
110 setOperationAction(ISD::VASTART, MVT::Other, Custom); in WebAssemblyTargetLowering()
111 setOperationAction(ISD::VAARG, MVT::Other, Expand); in WebAssemblyTargetLowering()
112 setOperationAction(ISD::VACOPY, MVT::Other, Expand); in WebAssemblyTargetLowering()
113 setOperationAction(ISD::VAEND, MVT::Other, Expand); in WebAssemblyTargetLowering()
115 for (auto T : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) { in WebAssemblyTargetLowering()
137 setLoadExtAction(ISD::EXTLOAD, T, MVT::f16, Expand); in WebAssemblyTargetLowering()
138 setTruncStoreAction(T, MVT::f16, Expand); in WebAssemblyTargetLowering()
146 for (auto T : {MVT::i32, MVT::i64}) in WebAssemblyTargetLowering()
149 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) in WebAssemblyTargetLowering()
155 for (auto T : {MVT::i32, MVT::i64}) in WebAssemblyTargetLowering()
180 for (auto T : {MVT::v16i8, MVT::v8i16}) in WebAssemblyTargetLowering()
184 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) in WebAssemblyTargetLowering()
188 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, in WebAssemblyTargetLowering()
189 MVT::v2f64}) in WebAssemblyTargetLowering()
193 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, in WebAssemblyTargetLowering()
194 MVT::v2f64}) in WebAssemblyTargetLowering()
199 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) in WebAssemblyTargetLowering()
204 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, in WebAssemblyTargetLowering()
205 MVT::v2f64}) in WebAssemblyTargetLowering()
209 setOperationAction(ISD::MUL, MVT::v16i8, Expand); in WebAssemblyTargetLowering()
212 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, in WebAssemblyTargetLowering()
213 MVT::v2f64}) in WebAssemblyTargetLowering()
219 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) in WebAssemblyTargetLowering()
224 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32}) in WebAssemblyTargetLowering()
228 setOperationAction(ISD::CTPOP, MVT::v16i8, Legal); in WebAssemblyTargetLowering()
229 setOperationAction(ISD::CTLZ, MVT::v16i8, Expand); in WebAssemblyTargetLowering()
230 setOperationAction(ISD::CTTZ, MVT::v16i8, Expand); in WebAssemblyTargetLowering()
234 for (auto T : {MVT::v8i16, MVT::v4i32, MVT::v2i64}) in WebAssemblyTargetLowering()
240 for (auto T : {MVT::v4f32, MVT::v2f64}) in WebAssemblyTargetLowering()
245 setCondCodeAction(CC, MVT::v2i64, Custom); in WebAssemblyTargetLowering()
250 for (auto T : {MVT::v2i64, MVT::v2f64}) in WebAssemblyTargetLowering()
255 setOperationAction(Op, MVT::v4i32, Custom); in WebAssemblyTargetLowering()
260 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in WebAssemblyTargetLowering()
264 for (auto T : {MVT::i8, MVT::i16, MVT::i32}) in WebAssemblyTargetLowering()
267 for (auto T : MVT::integer_fixedlen_vector_valuetypes()) in WebAssemblyTargetLowering()
271 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); in WebAssemblyTargetLowering()
272 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); in WebAssemblyTargetLowering()
275 setOperationAction(ISD::FrameIndex, MVT::i32, Custom); in WebAssemblyTargetLowering()
276 setOperationAction(ISD::FrameIndex, MVT::i64, Custom); in WebAssemblyTargetLowering()
277 setOperationAction(ISD::CopyToReg, MVT::Other, Custom); in WebAssemblyTargetLowering()
280 for (auto T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64}) in WebAssemblyTargetLowering()
285 setOperationAction(ISD::BR_JT, MVT::Other, Custom); in WebAssemblyTargetLowering()
292 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand); in WebAssemblyTargetLowering()
293 setTruncStoreAction(MVT::f64, MVT::f32, Expand); in WebAssemblyTargetLowering()
294 for (auto T : MVT::integer_valuetypes()) in WebAssemblyTargetLowering()
296 setLoadExtAction(Ext, T, MVT::i1, Promote); in WebAssemblyTargetLowering()
298 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, in WebAssemblyTargetLowering()
299 MVT::v2f64}) { in WebAssemblyTargetLowering()
300 for (auto MemT : MVT::fixedlen_vector_valuetypes()) { in WebAssemblyTargetLowering()
301 if (MVT(T) != MemT) { in WebAssemblyTargetLowering()
310 setLoadExtAction(Ext, MVT::v8i16, MVT::v8i8, Legal); in WebAssemblyTargetLowering()
311 setLoadExtAction(Ext, MVT::v4i32, MVT::v4i16, Legal); in WebAssemblyTargetLowering()
312 setLoadExtAction(Ext, MVT::v2i64, MVT::v2i32, Legal); in WebAssemblyTargetLowering()
314 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Legal); in WebAssemblyTargetLowering()
318 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); in WebAssemblyTargetLowering()
321 setOperationAction(ISD::TRAP, MVT::Other, Legal); in WebAssemblyTargetLowering()
322 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal); in WebAssemblyTargetLowering()
325 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in WebAssemblyTargetLowering()
326 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom); in WebAssemblyTargetLowering()
327 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); in WebAssemblyTargetLowering()
347 MVT WebAssemblyTargetLowering::getPointerTy(const DataLayout &DL, in getPointerTy()
350 return MVT::externref; in getPointerTy()
352 return MVT::funcref; in getPointerTy()
356 MVT WebAssemblyTargetLowering::getPointerMemTy(const DataLayout &DL, in getPointerMemTy()
359 return MVT::externref; in getPointerMemTy()
361 return MVT::funcref; in getPointerMemTy()
407 MVT WebAssemblyTargetLowering::getScalarShiftAmountTy(const DataLayout & /*DL*/, in getScalarShiftAmountTy()
421 MVT Result = MVT::getIntegerVT(BitWidth); in getScalarShiftAmountTy()
422 assert(Result != MVT::INVALID_SIMPLE_VALUE_TYPE && in getScalarShiftAmountTy()
718 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const { in getRegForInlineAsmConstraint()
724 assert(VT != MVT::iPTR && "Pointer MVT not expected here"); in getRegForInlineAsmConstraint()
806 return (ExtT == MVT::v8i16 && MemT == MVT::v8i8) || in isVectorLoadExtDesirable()
807 (ExtT == MVT::v4i32 && MemT == MVT::v4i16) || in isVectorLoadExtDesirable()
808 (ExtT == MVT::v2i64 && MemT == MVT::v2i32); in isVectorLoadExtDesirable()
838 Info.memVT = MVT::i32; in getTgtMemIntrinsic()
852 Info.memVT = MVT::i32; in getTgtMemIntrinsic()
860 Info.memVT = MVT::i64; in getTgtMemIntrinsic()
896 WebAssemblyTargetLowering::getPreferredVectorAction(MVT VT) const { in getPreferredVectorAction()
898 MVT EltVT = VT.getVectorElementType(); in getPreferredVectorAction()
902 if (EltVT == MVT::i8 || EltVT == MVT::i16 || EltVT == MVT::i32 || in getPreferredVectorAction()
903 EltVT == MVT::i64 || EltVT == MVT::f32 || EltVT == MVT::f64) in getPreferredVectorAction()
999 SmallVector<MVT, 4> CallerRetTys; in LowerCall()
1000 SmallVector<MVT, 4> CalleeRetTys; in LowerCall()
1067 DAG.getConstant(Out.Flags.getByValSize(), DL, MVT::i32); in LowerCall()
1116 assert(VT != MVT::iPTR && "Legalized args should be concrete"); in LowerCall()
1151 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains); in LowerCall()
1212 SDValue TableSlot = DAG.getConstant(0, DL, MVT::i32); in LowerCall()
1215 WebAssemblyISD::TABLE_SET, DL, DAG.getVTList(MVT::Other), TableSetOps, in LowerCall()
1216 MVT::funcref, in LowerCall()
1228 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); in LowerCall()
1232 InTys.push_back(MVT::Other); in LowerCall()
1263 Chain = DAG.getNode(WebAssemblyISD::RETURN, DL, MVT::Other, RetOps); in LowerReturn()
1312 DL, MVT::i32)) in LowerFormalArguments()
1335 MVT PtrVT = getPointerTy(MF.getDataLayout()); in LowerFormalArguments()
1342 DAG.getTargetConstant(Ins.size(), DL, MVT::i32))); in LowerFormalArguments()
1347 SmallVector<MVT, 4> Params; in LowerFormalArguments()
1348 SmallVector<MVT, 4> Results; in LowerFormalArguments()
1351 for (MVT VT : Results) in LowerFormalArguments()
1477 return (Op->getOperand(1).getSimpleValueType() == MVT::i32 && in IsWebAssemblyTableWithOffset()
1479 (Op->getOperand(0).getSimpleValueType() == MVT::i32 && in IsWebAssemblyTableWithOffset()
1510 Idx = DAG.getConstant(0, DL, MVT::i32); in MatchTableForLowering()
1525 SDValue IdxV = DAG.getNode(ISD::ADD, DL, MVT::i32, Base->getOperand(1), in MatchTableForLowering()
1554 SDVTList Tys = DAG.getVTList(MVT::Other); in LowerStore()
1567 SDVTList Tys = DAG.getVTList(MVT::Other); in LowerStore()
1578 SDValue Idx = DAG.getTargetConstant(*Local, Base, MVT::i32); in LowerStore()
1579 SDVTList Tys = DAG.getVTList(MVT::Other); // The chain. in LowerStore()
1606 SDVTList Tys = DAG.getVTList(LN->getValueType(0), MVT::Other); in LowerLoad()
1619 SDVTList Tys = DAG.getVTList(LN->getValueType(0), MVT::Other); in LowerLoad()
1630 SDValue Idx = DAG.getTargetConstant(*Local, Base, MVT::i32); in LowerLoad()
1655 SDValue Copy(DAG.getMachineNode(VT == MVT::i32 ? WebAssembly::COPY_I32 in LowerCopyToReg()
1691 {DAG.getConstant(Depth, DL, MVT::i32)}, CallOptions, DL) in LowerRETURNADDR()
1740 MVT PtrVT = getPointerTy(DAG.getDataLayout()); in LowerGlobalTLSAddress()
1741 auto GlobalGet = PtrVT == MVT::i64 ? WebAssembly::GLOBAL_GET_I64 in LowerGlobalTLSAddress()
1782 MVT PtrVT = getPointerTy(MF.getDataLayout()); in LowerGlobalAddress()
1855 return DAG.getNode(WebAssemblyISD::BR_TABLE, DL, MVT::Other, Ops); in LowerBR_JT()
1922 Ops[OpIdx++] = DAG.getConstant(0, DL, MVT::i32); in LowerIntrinsic()
1948 MVT VecT = Extract.getOperand(0).getSimpleValueType(); in LowerSIGN_EXTEND_INREG()
1951 MVT ExtractedLaneT = in LowerSIGN_EXTEND_INREG()
1953 MVT ExtractedVecT = in LowerSIGN_EXTEND_INREG()
1954 MVT::getVectorVT(ExtractedLaneT, 128 / ExtractedLaneT.getSizeInBits()); in LowerSIGN_EXTEND_INREG()
1977 if (Op.getValueType() != MVT::v2f64) in LowerConvertLow()
2017 MVT ExpectedSrcVT; in LowerConvertLow()
2021 ExpectedSrcVT = MVT::v4i32; in LowerConvertLow()
2024 ExpectedSrcVT = MVT::v4f32; in LowerConvertLow()
2037 return DAG.getNode(LHSOpcode, DL, MVT::v2f64, Src); in LowerConvertLow()
2049 bool CanSwizzle = VecT == MVT::v16i8; in LowerBUILD_VECTOR()
2082 if (SwizzleSrc.getValueType() != MVT::v16i8 || in LowerBUILD_VECTOR()
2083 SwizzleIndices.getValueType() != MVT::v16i8 || in LowerBUILD_VECTOR()
2291 DAG.getConstant(I, DL, MVT::i32)); in LowerBUILD_VECTOR()
2302 MVT VecType = Op.getOperand(0).getSimpleValueType(); in LowerVECTOR_SHUFFLE()
2317 Ops[OpIdx++] = DAG.getConstant(ByteIndex, DL, MVT::i32); in LowerVECTOR_SHUFFLE()
2329 assert(Op->getOperand(0)->getSimpleValueType(0) == MVT::v2i64); in LowerSETCC()
2335 return DAG.getNode(ISD::SELECT_CC, DL, MVT::i64, LHS[I], RHS[I], in LowerSETCC()
2336 DAG.getConstant(uint64_t(-1), DL, MVT::i64), in LowerSETCC()
2337 DAG.getConstant(uint64_t(0), DL, MVT::i64), CC); in LowerSETCC()
2358 if (LaneT.bitsGE(MVT::i32)) in unrollVectorShift()
2363 SDValue Mask = DAG.getConstant(LaneT.getSizeInBits() - 1, DL, MVT::i32); in unrollVectorShift()
2366 DAG.ExtractVectorElements(Op.getOperand(0), ShiftedElements, 0, 0, MVT::i32); in unrollVectorShift()
2368 DAG.ExtractVectorElements(Op.getOperand(1), ShiftElements, 0, 0, MVT::i32); in unrollVectorShift()
2372 DAG.getNode(ISD::AND, DL, MVT::i32, ShiftElements[i], Mask); in unrollVectorShift()
2375 ShiftedValue = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, in unrollVectorShift()
2378 DAG.getNode(ShiftOpcode, DL, MVT::i32, ShiftedValue, MaskedShiftValue)); in unrollVectorShift()
2395 ShiftVal = DAG.getAnyExtOrTrunc(ShiftVal, DL, MVT::i32); in LowerShift()
2421 if ((ResT == MVT::i32 || ResT == MVT::i64) && in LowerFP_TO_INT_SAT()
2422 (SatVT == MVT::i32 || SatVT == MVT::i64)) in LowerFP_TO_INT_SAT()
2425 if (ResT == MVT::v4i32 && SatVT == MVT::i32) in LowerFP_TO_INT_SAT()
2449 MVT SrcType = CastOp.getSimpleValueType(); in performVECTOR_SHUFFLECombine()
2450 MVT DstType = Bitcast.getSimpleValueType(); in performVECTOR_SHUFFLECombine()
2479 if (ResVT == MVT::v8i16) { in performVectorExtendCombine()
2480 if (Extract.getValueType() != MVT::v8i8 || in performVectorExtendCombine()
2481 Source.getValueType() != MVT::v16i8 || (Index != 0 && Index != 8)) in performVectorExtendCombine()
2483 } else if (ResVT == MVT::v4i32) { in performVectorExtendCombine()
2484 if (Extract.getValueType() != MVT::v4i16 || in performVectorExtendCombine()
2485 Source.getValueType() != MVT::v8i16 || (Index != 0 && Index != 4)) in performVectorExtendCombine()
2487 } else if (ResVT == MVT::v2i64) { in performVectorExtendCombine()
2488 if (Extract.getValueType() != MVT::v2i32 || in performVectorExtendCombine()
2489 Source.getValueType() != MVT::v4i32 || (Index != 0 && Index != 2)) in performVectorExtendCombine()
2552 ResVT = MVT::v4i32; in performVectorTruncZeroCombine()
2553 ExpectedConversionType = MVT::v2i32; in performVectorTruncZeroCombine()
2556 ResVT = MVT::v4f32; in performVectorTruncZeroCombine()
2557 ExpectedConversionType = MVT::v2f32; in performVectorTruncZeroCombine()
2570 if (Source.getValueType() != MVT::v2f64) in performVectorTruncZeroCombine()
2597 ResVT = MVT::v4i32; in performVectorTruncZeroCombine()
2600 ResVT = MVT::v4f32; in performVectorTruncZeroCombine()
2610 if (Concat.getValueType() != MVT::v4f64) in performVectorTruncZeroCombine()
2614 if (Source.getValueType() != MVT::v2f64) in performVectorTruncZeroCombine()
2618 Concat.getOperand(1).getValueType() != MVT::v2f64) in performVectorTruncZeroCombine()
2675 EVT InVT = MVT::i16, OutVT = MVT::i8; in truncateVectorWithNARROW()
2677 InVT = MVT::i32; in truncateVectorWithNARROW()
2678 OutVT = MVT::i16; in truncateVectorWithNARROW()
2722 if (!((InSVT == MVT::i16 || InSVT == MVT::i32 || InSVT == MVT::i64) && in performTruncateCombine()
2723 (OutSVT == MVT::i8 || OutSVT == MVT::i16) && OutVT.is128BitVector())) in performTruncateCombine()