| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 2145 if (VT != MVT::i32 && VT != MVT::i64) in tryBitfieldInsertOpFromOrAndImm()
2234 if (VT != MVT::i32 && VT != MVT::i64) in tryBitfieldInsertOpFromOr()
2416 if (VT != MVT::i32 && VT != MVT::i64) in tryBitfieldInsertInZeroOp()
3807 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 || in Select()
3811 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 || in Select()
3815 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 || in Select()
3826 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 || in Select()
3830 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 || in Select()
3834 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 || in Select()
3845 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 || in Select()
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| H A D | AArch64ISelLowering.cpp | 718 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32) { in AArch64TargetLowering()
764 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) { in addTypeForNEON()
814 if (!VT.isFloatingPoint() && VT != MVT::v2i64 && VT != MVT::v1i64) in addTypeForNEON()
4543 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) { in LowerFCOPYSIGN()
5174 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) { in LowerVAARG()
5469 (VT == MVT::f64 || VT == MVT::v1f64 || VT == MVT::v2f64 || in getEstimate()
7505 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 && in LowerINSERT_VECTOR_ELT()
7506 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16) in LowerINSERT_VECTOR_ELT()
7539 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 && in LowerEXTRACT_VECTOR_ELT()
7540 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16) in LowerEXTRACT_VECTOR_ELT()
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| H A D | AArch64FastISel.cpp | 404 if (VT != MVT::f32 && VT != MVT::f64) in materializeFP()
525 MVT VT; in fastMaterializeFloatZero() local
529 if (VT != MVT::f32 && VT != MVT::f64) in fastMaterializeFloatZero()
980 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16) in isTypeSupported()
1890 MVT VT; in selectAddSub() local
2961 if (VT >= MVT::i1 && VT <= MVT::i64) in fastLowerArguments()
2963 else if ((VT >= MVT::f16 && VT <= MVT::f64) || VT.is64BitVector() || in fastLowerArguments()
2994 if (VT >= MVT::i1 && VT <= MVT::i32) { in fastLowerArguments()
3204 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)) in fastLowerCall()
3322 unsigned ResultReg = emitLoad(VT, VT, Src); in tryEmitSmallMemCpy()
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 493 return isTypeLegal(VT) ? VT : MVT::INVALID_SIMPLE_VALUE_TYPE; in hasFastEqualityCompare()
709 return VT; in getTypeToExpandTo()
711 VT = getTypeToTransformTo(Context, VT); in getTypeToExpandTo()
884 return (VT == MVT::Other || isTypeLegal(VT)) && in isOperationLegalOrCustom()
893 return (VT == MVT::Other || isTypeLegal(VT)) && in isOperationLegalOrPromote()
902 return (VT == MVT::Other || isTypeLegal(VT)) && in isOperationLegalOrCustomOrPromote()
986 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand); in isOperationExpand()
991 return (VT == MVT::Other || isTypeLegal(VT)) && in isOperationLegal()
1123 assert((VT.isInteger() || VT.isFloatingPoint()) && in getTypeToPromoteTo()
1126 MVT NVT = VT; in getTypeToPromoteTo()
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| H A D | SelectionDAG.h | 102 FastID(ID), VTs(VT), NumVTs(Num) {
546 SDVTList getVTList(EVT VT);
609 return getConstantFP(Val, DL, VT, true);
612 return getConstantFP(Val, DL, VT, true);
629 return getFrameIndex(FI, VT, true);
755 (VT.isInteger() &&
807 EVT VT = Op.getValueType();
812 EVT VT = Op.getValueType();
852 SDValue getUNDEF(EVT VT) {
857 SDValue getGLOBAL_OFFSET_TABLE(EVT VT) {
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| H A D | ValueTypes.h | 44 bool operator==(EVT VT) const {
45 return !(*this != VT);
47 bool operator!=(EVT VT) const {
48 if (V.SimpleTy != VT.V.SimpleTy)
51 return LLVMTy != VT.LLVMTy;
86 MVT M = MVT::getVectorVT(VT.V, EC); in getVectorVT()
223 bool bitsEq(EVT VT) const { in bitsEq()
229 bool bitsGT(EVT VT) const { in bitsGT()
235 bool bitsGE(EVT VT) const { in bitsGE()
241 bool bitsLT(EVT VT) const { in bitsLT()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 1162 if (VT.isVector() || !VT.isInteger()) in PromoteIntBinOp()
1227 if (VT.isVector() || !VT.isInteger()) in PromoteIntShiftOp()
1277 if (VT.isVector() || !VT.isInteger()) in PromoteExtend()
1308 if (VT.isVector() || !VT.isInteger()) in PromoteLoad()
3108 if (VT.isVector() || !VT.isInteger()) in useDivRem()
3570 if (VT.isSimple() && !VT.isVector()) { in visitMULHS()
3627 if (VT.isSimple() && !VT.isVector()) { in visitMULHU()
3703 if (VT.isSimple() && !VT.isVector()) { in visitSMUL_LOHI()
4834 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16) in MatchBSwapHWordLow()
5908 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64) in MatchLoadCombine()
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| H A D | TargetLowering.cpp | 161 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128) in softenSetCCOperands()
2029 if (VT == MVT::i1) in isExtendedTrueVal()
2519 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { in SimplifySetCC()
2728 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) && in SimplifySetCC()
4221 if (VT.isVector() && (!isOperationLegalOrCustom(ISD::SHL, VT) || in expandFunnelShift()
4286 if (VT.isVector() && (!isOperationLegalOrCustom(ISD::SHL, VT) || in expandROT()
4564 if (VT.isVector() && (!isOperationLegalOrCustom(ISD::ADD, VT) || in expandCTPOP()
4703 ISD::AND, dl, VT, DAG.getNOT(dl, Op, VT), in expandCTTZ()
4704 DAG.getNode(ISD::SUB, dl, VT, Op, DAG.getConstant(1, dl, VT))); in expandCTTZ()
4726 if (VT.isVector() && (!isOperationLegalOrCustom(ISD::SRA, VT) || in expandABS()
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| H A D | SelectionDAG.cpp | 796 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && in VerifySDNode()
1148 SDValue TrueValue = getBoolConstant(true, DL, VT, VT); in getLogicalNOT()
1485 if (VT.isSimple() && (unsigned)VT.getSimpleVT().SimpleTy >= in getValueType()
1550 assert(VT == N1.getValueType() && VT == N2.getValueType() && in getVectorShuffle()
4386 assert(VT.isInteger() && VT == Operand.getValueType() && in getNode()
4392 assert(VT.isInteger() && VT == Operand.getValueType() && in getNode()
4400 assert(VT.isInteger() && VT == Operand.getValueType() && in getNode()
4869 assert((!VT.isVector() || VT == N2.getValueType()) && in getNode()
5446 if (VT != Value.getValueType() && !VT.isInteger()) in getMemsetValue()
5464 else if (VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128) in getMemsetStringVal()
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| H A D | LegalizeVectorOps.cpp | 524 (VT.isVector() && VT.getVectorElementType().isFloatingPoint() && in Promote()
820 EVT VT = Op.getValueType(); in ExpandSELECT() local
872 EVT VT = Op.getValueType(); in ExpandSEXTINREG() local
895 EVT VT = Op.getValueType(); in ExpandANY_EXTEND_VECTOR_INREG() local
912 ISD::BITCAST, DL, VT, in ExpandANY_EXTEND_VECTOR_INREG()
918 EVT VT = Op.getValueType(); in ExpandSIGN_EXTEND_VECTOR_INREG() local
942 EVT VT = Op.getValueType(); in ExpandZERO_EXTEND_VECTOR_INREG() local
975 EVT VT = Op.getValueType(); in ExpandBSWAP() local
993 EVT VT = Op.getValueType(); in ExpandBITREVERSE() local
1073 APInt::getAllOnesValue(VT.getScalarSizeInBits()), DL, VT); in ExpandVSELECT()
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| H A D | LegalizeDAG.cpp | 287 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion"); in ExpandConstantFP()
293 EVT OrigVT = VT; in ExpandConstantFP()
294 EVT SVT = VT; in ExpandConstantFP()
308 VT = SVT; in ExpandConstantFP()
2958 VT = NewVT; in ExpandNode()
3078 SDVTList VTs = DAG.getVTList(VT, VT); in ExpandNode()
3148 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, dl, VT)); in ExpandNode()
3161 SDVTList VTs = DAG.getVTList(VT, VT); in ExpandNode()
3179 SDVTList VTs = DAG.getVTList(VT, VT); in ExpandNode()
3191 SDVTList VTs = DAG.getVTList(VT, VT); in ExpandNode()
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| H A D | ResourcePriorityQueue.cpp | 93 MVT VT = ScegN->getSimpleValueType(i); in numberRCValPredInSU() local
94 if (TLI->isTypeLegal(VT) in numberRCValPredInSU()
131 if (TLI->isTypeLegal(VT) in numberRCValSuccInSU()
326 MVT VT = SU->getNode()->getSimpleValueType(i); in rawRegPressureDelta() local
327 if (TLI->isTypeLegal(VT) in rawRegPressureDelta()
328 && TLI->getRegClassFor(VT) in rawRegPressureDelta()
329 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
339 if (TLI->isTypeLegal(VT) && TLI->getRegClassFor(VT) in rawRegPressureDelta()
473 MVT VT = ScegN->getSimpleValueType(i); in scheduledNode() local
475 if (TLI->isTypeLegal(VT)) { in scheduledNode()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 651 if (VT.isVector()) { in initActions()
716 assert(isTypeLegal(VT)); in canOpTrap()
737 if (VT.isSimple()) { in getTypeConversion()
738 MVT SVT = VT.getSimpleVT(); in getTypeConversion()
757 if (!VT.isVector()) { in getTypeConversion()
857 if (!VT.isPow2VectorType()) { in getTypeConversion()
1171 if (isTypeLegal(VT)) in computeRegisterProperties()
1228 if (NVT == VT) { in computeRegisterProperties()
1361 EVT VT = ValueVTs[j]; in GetReturnInfo() local
1375 if (VT.bitsLT(MinVT)) in GetReturnInfo()
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| H A D | CallingConvLower.cpp | 92 MVT ArgVT = Ins[i].VT; in AnalyzeFormalArguments()
110 MVT VT = Outs[i].VT; in CheckReturn() local
112 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) in CheckReturn()
124 MVT VT = Outs[i].VT; in AnalyzeReturn() local
126 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) { in AnalyzeReturn()
177 MVT VT = Ins[i].VT; in AnalyzeCallResult() local
179 if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this)) { in AnalyzeCallResult()
191 if (Fn(0, VT, VT, CCValAssign::Full, ISD::ArgFlagsTy(), *this)) { in AnalyzeCallResult()
201 if (VT.isVector()) in isValueTypeInRegForCC()
203 if (!VT.isInteger()) in isValueTypeInRegForCC()
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 8430 if (VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 || in LowerToHorizontalOp()
8528 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32) in materializeVectorConstant()
17275 assert((VT == MVT::i16 || VT == MVT::i32 || VT == MVT::i64) && in LowerFunnelShift()
18609 assert((VT == MVT::f64 || VT == MVT::f32 || VT == MVT::f128 || in LowerFABSorFNEG()
18669 assert((VT == MVT::f64 || VT == MVT::f32 || VT == MVT::f128 || in LowerFCOPYSIGN()
23576 if (VT == MVT::i16 || VT == MVT::i32 || VT == MVT::i64) { in LowerABS()
27584 VT = VT.getScalarType(); in isFMAFasterThanFMulAndFAdd()
36728 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64) in combineOr()
37689 if ((VT == MVT::v2i1 || VT == MVT::v4i1) && VT == StVT && in combineStore()
37702 VT == MVT::v64i1) && VT == StVT && TLI.isTypeLegal(VT) && in combineStore()
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| H A D | X86InterleavedAccess.cpp | 223 static MVT scaleVectorType(MVT VT) { in scaleVectorType() argument
254 assert(VT.getSizeInBits() >= 256 && in genShuffleBland()
323 MVT VT = MVT::v8i16; in interleave8bitStride4VF8() local
364 MVT HalfVT = scaleVectorType(VT); in interleave8bitStride4()
413 if (VT == MVT::v16i8) { in interleave8bitStride4()
434 int VectorSize = VT.getSizeInBits(); in createShuffleStride()
435 int VF = VT.getVectorNumElements(); in createShuffleStride()
556 createShuffleStride(VT, 3, VPShuf); in deinterleave8bitStride3()
557 setGroupSize(VT, GroupSize); in deinterleave8bitStride3()
610 int VF = VT.getVectorNumElements(); in group2Shuffle()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 185 if (VT == MVT::i64) in AMDGPUTargetLowering()
759 return VT == MVT::f32 || VT == MVT::f64 || in isFAbsFree()
765 return VT == MVT::f32 || VT == MVT::f64 || in isFNegFree()
1243 if (VT == MVT::v4i16 || VT == MVT::v4f16) { in LowerCONCAT_VECTORS()
1503 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, DL, VT)); in LowerDIVREM24()
1762 REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT)); in LowerUDIVREM64()
2190 if (VT == MVT::f32 || VT == MVT::f16) in LowerFROUND()
2193 if (VT == MVT::f64) in LowerFROUND()
2244 SL, VT); in getLog2EVal()
2774 if (VT.getScalarType() == MVT::i32 || isTypeLegal(VT)) in shouldCombineMemoryType()
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| H A D | R600ISelLowering.cpp | 799 SDValue Width = DAG.getConstant(VT.getSizeInBits(), DL, VT); in LowerSHLParts()
800 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT); in LowerSHLParts()
822 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi); in LowerSHLParts()
837 SDValue Width = DAG.getConstant(VT.getSizeInBits(), DL, VT); in LowerSRXParts()
838 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT); in LowerSRXParts()
860 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi); in LowerSRXParts()
991 (CompareVT == VT || VT == MVT::i32)) { in LowerSELECT_CC()
1245 VT.isVector()) { in LowerSTORE()
1594 EVT VT = In.VT; in LowerFormalArguments() local
1672 if (!VT.isSimple() || VT == MVT::Other) in allowsMisalignedMemoryAccesses()
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| /freebsd-12.1/contrib/llvm/lib/Support/ |
| H A D | LowLevelType.cpp | 19 LLT::LLT(MVT VT) { in LLT() argument
20 if (VT.isVector()) { in LLT()
21 init(/*isPointer=*/false, VT.getVectorNumElements() > 1, in LLT()
22 VT.getVectorNumElements(), VT.getVectorElementType().getSizeInBits(), in LLT()
24 } else if (VT.isValid()) { in LLT()
27 assert(VT.getSizeInBits() != 0 && "invalid zero-sized type"); in LLT()
29 VT.getSizeInBits(), /*AddressSpace=*/0); in LLT()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 190 if (VT.isInteger() && VT != PromotedBitwiseVT) { in addTypeForNEON()
208 VT != MVT::v2i64 && VT != MVT::v1i64) in addTypeForNEON()
1467 if (VT == MVT::Glue || VT == MVT::Other) in getSchedulingPreference()
4825 if (VT != MVT::v4i16 && VT != MVT::v8i16) in LowerVectorFP_TO_INT()
5423 assert((VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 || in LowerCTPOP()
5424 VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && in LowerCTPOP()
6525 if (VT.is128BitVector() && VT != MVT::v2f64 && VT != MVT::v4f32) { in LowerBUILD_VECTOR()
6817 ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(M, VT))); in isShuffleMaskLegal()
7099 if ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(ShuffleMask, VT)) in LowerVECTOR_SHUFFLE()
13369 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { in getARMIndexedAddressParts()
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| H A D | ARMFastISel.cpp | 468 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1) in ARMMaterializeInt()
668 MVT VT; in fastMaterializeAlloca() local
709 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16) in isLoadTypeLegal()
1042 MVT VT; in SelectLoad() local
1173 MVT VT; in SelectStore() local
1627 MVT VT; in SelectSelect() local
1703 MVT VT; in SelectDiv() local
1732 MVT VT; in SelectRem() local
1820 bool is64bit = VT == MVT::f64 || VT == MVT::i64; in SelectBinaryFPOp()
2460 MVT VT; in ARMTryEmitSmallMemCpy() local
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| /freebsd-12.1/contrib/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 556 if (!VT.isVector()) in getSetCCResultType()
562 VT = VT.getScalarType(); in isFMAFasterThanFMulAndFAdd()
564 if (!VT.isSimple()) in isFMAFasterThanFMulAndFAdd()
2529 if (VT.isVector()) in lowerSETCC()
3067 if (is32Bit(VT)) in lowerSMUL_LOHI()
3115 if (is32Bit(VT)) in lowerUMUL_LOHI()
3139 if (is32Bit(VT)) in lowerSDIVREM()
4049 EVT VT; member
5108 return VT.isVector() && VT.getScalarSizeInBits() % 8 == 0 && VT.isSimple(); in canTreatAsByteVector()
5814 if (VT.isVector() && isTypeLegal(VT) && in combineIntDIVREM()
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| /freebsd-12.1/contrib/llvm/include/llvm/Support/ |
| H A D | MachineValueType.h | 772 bool bitsGT(MVT VT) const { in bitsGT() argument
777 bool bitsGE(MVT VT) const { in bitsGE() argument
782 bool bitsLT(MVT VT) const { in bitsLT() argument
787 bool bitsLE(MVT VT) const { in bitsLE() argument
828 switch (VT.SimpleTy) { in getVectorVT()
907 switch(VT.SimpleTy) { in getScalableVectorVT()
981 return getVectorVT(VT, EC.Min); in getVectorVT()
992 SimpleValueType VT; member
994 mvt_iterator(SimpleValueType VT) : VT(VT) {} in mvt_iterator()
997 bool operator!=(const mvt_iterator &LHS) const { return VT != LHS.VT; }
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| /freebsd-12.1/contrib/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 83 for (auto VT : { MVT::i32, MVT::i64 }) { in BPFTargetLowering()
84 if (VT == MVT::i32 && !STI.getHasAlu32()) in BPFTargetLowering()
89 setOperationAction(ISD::SREM, VT, Expand); in BPFTargetLowering()
90 setOperationAction(ISD::UREM, VT, Expand); in BPFTargetLowering()
91 setOperationAction(ISD::MULHU, VT, Expand); in BPFTargetLowering()
92 setOperationAction(ISD::MULHS, VT, Expand); in BPFTargetLowering()
95 setOperationAction(ISD::ROTR, VT, Expand); in BPFTargetLowering()
96 setOperationAction(ISD::ROTL, VT, Expand); in BPFTargetLowering()
100 setOperationAction(ISD::CTPOP, VT, Expand); in BPFTargetLowering()
102 setOperationAction(ISD::SETCC, VT, Expand); in BPFTargetLowering()
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| /freebsd-12.1/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 304 if (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) { in isLoadTypeLegal()
610 MVT VT; in SelectLoad() local
759 MVT VT; in SelectStore() local
2001 if (VT != MVT::f32 && VT != MVT::f64) in PPCMaterializeFP()
2217 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && in PPCMaterializeInt()
2218 VT != MVT::i1) in PPCMaterializeInt()
2276 MVT VT; in fastMaterializeAlloca() local
2303 MVT VT; in tryToFoldLoadIntoMI() local
2343 if (VT != MVT::i16 && VT != MVT::i8) in tryToFoldLoadIntoMI()
2351 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8) in tryToFoldLoadIntoMI()
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