Lines Matching refs:VT
57 static bool is32Bit(EVT VT) { in is32Bit() argument
58 switch (VT.getSimpleVT().SimpleTy) { in is32Bit()
132 MVT VT = MVT::SimpleValueType(I); in SystemZTargetLowering() local
133 if (isTypeLegal(VT)) { in SystemZTargetLowering()
135 setOperationAction(ISD::SETCC, VT, Custom); in SystemZTargetLowering()
138 setOperationAction(ISD::SELECT, VT, Expand); in SystemZTargetLowering()
141 setOperationAction(ISD::SELECT_CC, VT, Custom); in SystemZTargetLowering()
142 setOperationAction(ISD::BR_CC, VT, Custom); in SystemZTargetLowering()
157 MVT VT = MVT::SimpleValueType(I); in SystemZTargetLowering() local
158 if (isTypeLegal(VT)) { in SystemZTargetLowering()
160 setOperationAction(ISD::SDIV, VT, Expand); in SystemZTargetLowering()
161 setOperationAction(ISD::UDIV, VT, Expand); in SystemZTargetLowering()
162 setOperationAction(ISD::SREM, VT, Expand); in SystemZTargetLowering()
163 setOperationAction(ISD::UREM, VT, Expand); in SystemZTargetLowering()
164 setOperationAction(ISD::SDIVREM, VT, Custom); in SystemZTargetLowering()
165 setOperationAction(ISD::UDIVREM, VT, Custom); in SystemZTargetLowering()
168 setOperationAction(ISD::SADDO, VT, Custom); in SystemZTargetLowering()
169 setOperationAction(ISD::SSUBO, VT, Custom); in SystemZTargetLowering()
172 setOperationAction(ISD::UADDO, VT, Custom); in SystemZTargetLowering()
173 setOperationAction(ISD::USUBO, VT, Custom); in SystemZTargetLowering()
176 setOperationAction(ISD::ADDCARRY, VT, Custom); in SystemZTargetLowering()
177 setOperationAction(ISD::SUBCARRY, VT, Custom); in SystemZTargetLowering()
181 setOperationAction(ISD::ATOMIC_LOAD, VT, Custom); in SystemZTargetLowering()
182 setOperationAction(ISD::ATOMIC_STORE, VT, Custom); in SystemZTargetLowering()
186 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); in SystemZTargetLowering()
190 setOperationAction(ISD::CTPOP, VT, Custom); in SystemZTargetLowering()
192 setOperationAction(ISD::CTPOP, VT, Expand); in SystemZTargetLowering()
195 setOperationAction(ISD::CTTZ, VT, Expand); in SystemZTargetLowering()
196 setOperationAction(ISD::ROTR, VT, Expand); in SystemZTargetLowering()
199 setOperationAction(ISD::MULHS, VT, Expand); in SystemZTargetLowering()
200 setOperationAction(ISD::MULHU, VT, Expand); in SystemZTargetLowering()
201 setOperationAction(ISD::SMUL_LOHI, VT, Custom); in SystemZTargetLowering()
202 setOperationAction(ISD::UMUL_LOHI, VT, Custom); in SystemZTargetLowering()
209 setOperationAction(ISD::FP_TO_UINT, VT, Expand); in SystemZTargetLowering()
265 for (MVT VT : MVT::integer_valuetypes()) { in SystemZTargetLowering() local
266 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in SystemZTargetLowering()
267 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in SystemZTargetLowering()
268 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in SystemZTargetLowering()
291 for (MVT VT : MVT::vector_valuetypes()) { in SystemZTargetLowering() local
294 if (getOperationAction(Opcode, VT) == Legal) in SystemZTargetLowering()
295 setOperationAction(Opcode, VT, Expand); in SystemZTargetLowering()
299 setTruncStoreAction(VT, InnerVT, Expand); in SystemZTargetLowering()
300 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand); in SystemZTargetLowering()
301 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand); in SystemZTargetLowering()
302 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand); in SystemZTargetLowering()
305 if (isTypeLegal(VT)) { in SystemZTargetLowering()
310 setOperationAction(ISD::LOAD, VT, Legal); in SystemZTargetLowering()
311 setOperationAction(ISD::STORE, VT, Legal); in SystemZTargetLowering()
312 setOperationAction(ISD::VSELECT, VT, Legal); in SystemZTargetLowering()
313 setOperationAction(ISD::BITCAST, VT, Legal); in SystemZTargetLowering()
314 setOperationAction(ISD::UNDEF, VT, Legal); in SystemZTargetLowering()
318 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); in SystemZTargetLowering()
319 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in SystemZTargetLowering()
324 for (MVT VT : MVT::integer_vector_valuetypes()) { in SystemZTargetLowering() local
325 if (isTypeLegal(VT)) { in SystemZTargetLowering()
327 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Legal); in SystemZTargetLowering()
328 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Legal); in SystemZTargetLowering()
329 setOperationAction(ISD::ADD, VT, Legal); in SystemZTargetLowering()
330 setOperationAction(ISD::SUB, VT, Legal); in SystemZTargetLowering()
331 if (VT != MVT::v2i64) in SystemZTargetLowering()
332 setOperationAction(ISD::MUL, VT, Legal); in SystemZTargetLowering()
333 setOperationAction(ISD::AND, VT, Legal); in SystemZTargetLowering()
334 setOperationAction(ISD::OR, VT, Legal); in SystemZTargetLowering()
335 setOperationAction(ISD::XOR, VT, Legal); in SystemZTargetLowering()
337 setOperationAction(ISD::CTPOP, VT, Legal); in SystemZTargetLowering()
339 setOperationAction(ISD::CTPOP, VT, Custom); in SystemZTargetLowering()
340 setOperationAction(ISD::CTTZ, VT, Legal); in SystemZTargetLowering()
341 setOperationAction(ISD::CTLZ, VT, Legal); in SystemZTargetLowering()
344 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); in SystemZTargetLowering()
347 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom); in SystemZTargetLowering()
348 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom); in SystemZTargetLowering()
352 setOperationAction(ISD::SHL, VT, Custom); in SystemZTargetLowering()
353 setOperationAction(ISD::SRA, VT, Custom); in SystemZTargetLowering()
354 setOperationAction(ISD::SRL, VT, Custom); in SystemZTargetLowering()
358 setOperationAction(ISD::ROTL, VT, Expand); in SystemZTargetLowering()
359 setOperationAction(ISD::ROTR, VT, Expand); in SystemZTargetLowering()
363 setOperationAction(ISD::SETCC, VT, Custom); in SystemZTargetLowering()
384 MVT VT = MVT::SimpleValueType(I); in SystemZTargetLowering() local
385 if (isTypeLegal(VT)) { in SystemZTargetLowering()
387 setOperationAction(ISD::FRINT, VT, Legal); in SystemZTargetLowering()
391 setOperationAction(ISD::FNEARBYINT, VT, Legal); in SystemZTargetLowering()
392 setOperationAction(ISD::FFLOOR, VT, Legal); in SystemZTargetLowering()
393 setOperationAction(ISD::FCEIL, VT, Legal); in SystemZTargetLowering()
394 setOperationAction(ISD::FTRUNC, VT, Legal); in SystemZTargetLowering()
395 setOperationAction(ISD::FROUND, VT, Legal); in SystemZTargetLowering()
399 setOperationAction(ISD::FSIN, VT, Expand); in SystemZTargetLowering()
400 setOperationAction(ISD::FCOS, VT, Expand); in SystemZTargetLowering()
401 setOperationAction(ISD::FSINCOS, VT, Expand); in SystemZTargetLowering()
402 setOperationAction(ISD::FREM, VT, Expand); in SystemZTargetLowering()
403 setOperationAction(ISD::FPOW, VT, Expand); in SystemZTargetLowering()
495 for (MVT VT : MVT::fp_valuetypes()) in SystemZTargetLowering() local
496 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand); in SystemZTargetLowering()
555 LLVMContext &, EVT VT) const { in getSetCCResultType()
556 if (!VT.isVector()) in getSetCCResultType()
558 return VT.changeVectorElementTypeToInteger(); in getSetCCResultType()
561 bool SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const { in isFMAFasterThanFMulAndFAdd()
562 VT = VT.getScalarType(); in isFMAFasterThanFMulAndFAdd()
564 if (!VT.isSimple()) in isFMAFasterThanFMulAndFAdd()
567 switch (VT.getSimpleVT().SimpleTy) { in isFMAFasterThanFMulAndFAdd()
580 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { in isFPImmLegal()
595 bool SystemZTargetLowering::allowsMisalignedMemoryAccesses(EVT VT, in allowsMisalignedMemoryAccesses() argument
870 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const { in getRegForInlineAsmConstraint()
877 if (VT == MVT::i64) in getRegForInlineAsmConstraint()
879 else if (VT == MVT::i128) in getRegForInlineAsmConstraint()
884 if (VT == MVT::i64) in getRegForInlineAsmConstraint()
886 else if (VT == MVT::i128) in getRegForInlineAsmConstraint()
894 if (VT == MVT::f64) in getRegForInlineAsmConstraint()
896 else if (VT == MVT::f128) in getRegForInlineAsmConstraint()
902 if (VT == MVT::f32) in getRegForInlineAsmConstraint()
904 if (VT == MVT::f64) in getRegForInlineAsmConstraint()
917 if (VT == MVT::i32) in getRegForInlineAsmConstraint()
920 if (VT == MVT::i128) in getRegForInlineAsmConstraint()
927 if (VT == MVT::f32) in getRegForInlineAsmConstraint()
930 if (VT == MVT::f128) in getRegForInlineAsmConstraint()
937 if (VT == MVT::f32) in getRegForInlineAsmConstraint()
940 if (VT == MVT::f64) in getRegForInlineAsmConstraint()
947 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); in getRegForInlineAsmConstraint()
1021 static void VerifyVectorType(MVT VT, EVT ArgVT) { in VerifyVectorType() argument
1022 if (ArgVT.isVector() && !VT.isVector()) in VerifyVectorType()
1028 VerifyVectorType(Ins[i].VT, Ins[i].ArgVT); in VerifyVectorTypes()
1033 VerifyVectorType(Outs[i].VT, Outs[i].ArgVT); in VerifyVectorTypes()
2366 static void lowerGR128Binary(SelectionDAG &DAG, const SDLoc &DL, EVT VT, in lowerGR128Binary() argument
2370 bool Is32Bit = is32Bit(VT); in lowerGR128Binary()
2371 Even = DAG.getTargetExtractSubreg(SystemZ::even128(Is32Bit), DL, VT, Result); in lowerGR128Binary()
2372 Odd = DAG.getTargetExtractSubreg(SystemZ::odd128(Is32Bit), DL, VT, Result); in lowerGR128Binary()
2444 const SDLoc &DL, EVT VT, in getVectorCmp() argument
2458 return DAG.getNode(SystemZISD::PACK, DL, VT, HRes, LRes); in getVectorCmp()
2460 return DAG.getNode(Opcode, DL, VT, CmpOp0, CmpOp1); in getVectorCmp()
2466 const SDLoc &DL, EVT VT, in lowerVectorSETCC() argument
2480 SDValue LT = getVectorCmp(DAG, SystemZISD::VFCMPH, DL, VT, CmpOp1, CmpOp0); in lowerVectorSETCC()
2481 SDValue GE = getVectorCmp(DAG, SystemZISD::VFCMPHE, DL, VT, CmpOp0, CmpOp1); in lowerVectorSETCC()
2482 Cmp = DAG.getNode(ISD::OR, DL, VT, LT, GE); in lowerVectorSETCC()
2492 SDValue LT = getVectorCmp(DAG, SystemZISD::VFCMPH, DL, VT, CmpOp1, CmpOp0); in lowerVectorSETCC()
2493 SDValue GT = getVectorCmp(DAG, SystemZISD::VFCMPH, DL, VT, CmpOp0, CmpOp1); in lowerVectorSETCC()
2494 Cmp = DAG.getNode(ISD::OR, DL, VT, LT, GT); in lowerVectorSETCC()
2503 Cmp = getVectorCmp(DAG, Opcode, DL, VT, CmpOp0, CmpOp1); in lowerVectorSETCC()
2507 Cmp = getVectorCmp(DAG, Opcode, DL, VT, CmpOp1, CmpOp0); in lowerVectorSETCC()
2516 Mask = DAG.getNode(ISD::BITCAST, DL, VT, Mask); in lowerVectorSETCC()
2517 Cmp = DAG.getNode(ISD::XOR, DL, VT, Cmp, Mask); in lowerVectorSETCC()
2528 EVT VT = Op.getValueType(); in lowerSETCC() local
2529 if (VT.isVector()) in lowerSETCC()
2530 return lowerVectorSETCC(DAG, DL, VT, CC, CmpOp0, CmpOp1); in lowerSETCC()
3064 EVT VT = Op.getValueType(); in lowerSMUL_LOHI() local
3067 if (is32Bit(VT)) in lowerSMUL_LOHI()
3076 lowerGR128Binary(DAG, DL, VT, SystemZISD::SMUL_LOHI, in lowerSMUL_LOHI()
3095 SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63); in lowerSMUL_LOHI()
3096 SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63); in lowerSMUL_LOHI()
3100 lowerGR128Binary(DAG, DL, VT, SystemZISD::UMUL_LOHI, in lowerSMUL_LOHI()
3102 SDValue NegLLTimesRH = DAG.getNode(ISD::AND, DL, VT, LL, RH); in lowerSMUL_LOHI()
3103 SDValue NegLHTimesRL = DAG.getNode(ISD::AND, DL, VT, LH, RL); in lowerSMUL_LOHI()
3104 SDValue NegSum = DAG.getNode(ISD::ADD, DL, VT, NegLLTimesRH, NegLHTimesRL); in lowerSMUL_LOHI()
3105 Ops[1] = DAG.getNode(ISD::SUB, DL, VT, Ops[1], NegSum); in lowerSMUL_LOHI()
3112 EVT VT = Op.getValueType(); in lowerUMUL_LOHI() local
3115 if (is32Bit(VT)) in lowerUMUL_LOHI()
3124 lowerGR128Binary(DAG, DL, VT, SystemZISD::UMUL_LOHI, in lowerUMUL_LOHI()
3133 EVT VT = Op.getValueType(); in lowerSDIVREM() local
3139 if (is32Bit(VT)) in lowerSDIVREM()
3147 lowerGR128Binary(DAG, DL, VT, SystemZISD::SDIVREM, Op0, Op1, Ops[1], Ops[0]); in lowerSDIVREM()
3153 EVT VT = Op.getValueType(); in lowerUDIVREM() local
3159 lowerGR128Binary(DAG, DL, VT, SystemZISD::UDIVREM, in lowerUDIVREM()
3269 MVT VT = N->getSimpleValueType(0); in lowerADDSUBCARRY() local
3272 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) in lowerADDSUBCARRY()
3302 SDVTList VTs = DAG.getVTList(VT, MVT::i32); in lowerADDSUBCARRY()
3314 EVT VT = Op.getValueType(); in lowerCTPOP() local
3319 if (VT.isVector()) { in lowerCTPOP()
3322 switch (VT.getScalarSizeInBits()) { in lowerCTPOP()
3326 Op = DAG.getNode(ISD::BITCAST, DL, VT, Op); in lowerCTPOP()
3328 SDValue Tmp = DAG.getNode(SystemZISD::VSHL_BY_SCALAR, DL, VT, Op, Shift); in lowerCTPOP()
3329 Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp); in lowerCTPOP()
3330 Op = DAG.getNode(SystemZISD::VSRL_BY_SCALAR, DL, VT, Op, Shift); in lowerCTPOP()
3336 Op = DAG.getNode(SystemZISD::VSUM, DL, VT, Op, Tmp); in lowerCTPOP()
3343 Op = DAG.getNode(SystemZISD::VSUM, DL, VT, Op, Tmp); in lowerCTPOP()
3356 return DAG.getConstant(0, DL, VT); in lowerCTPOP()
3359 int64_t OrigBitSize = VT.getSizeInBits(); in lowerCTPOP()
3366 Op = DAG.getNode(ISD::TRUNCATE, DL, VT, Op); in lowerCTPOP()
3371 SDValue Tmp = DAG.getNode(ISD::SHL, DL, VT, Op, DAG.getConstant(I, DL, VT)); in lowerCTPOP()
3373 Tmp = DAG.getNode(ISD::AND, DL, VT, Tmp, in lowerCTPOP()
3374 DAG.getConstant(((uint64_t)1 << BitSize) - 1, DL, VT)); in lowerCTPOP()
3375 Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp); in lowerCTPOP()
3380 Op = DAG.getNode(ISD::SRL, DL, VT, Op, in lowerCTPOP()
3381 DAG.getConstant(BitSize - 8, DL, VT)); in lowerCTPOP()
3899 EVT VT = ShuffleOp.getValueType(); in getVPermMask() local
3900 unsigned NumElements = VT.getVectorNumElements(); in getVPermMask()
3901 unsigned BytesPerElement = VT.getVectorElementType().getStoreSize(); in getVPermMask()
4035 GeneralShuffle(EVT vt) : VT(vt) {} in GeneralShuffle()
4049 EVT VT; member
4055 unsigned BytesPerElement = VT.getVectorElementType().getStoreSize(); in addUndef()
4067 unsigned BytesPerElement = VT.getVectorElementType().getStoreSize(); in add()
4072 EVT FromVT = Op.getNode() ? Op.getValueType() : VT; in add()
4130 return DAG.getUNDEF(VT); in getNode()
4201 return DAG.getNode(ISD::BITCAST, DL, VT, Op); in getNode()
4214 static SDValue buildScalarToVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT, in buildScalarToVector() argument
4220 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Value); in buildScalarToVector()
4221 return DAG.getBuildVector(VT, DL, Ops); in buildScalarToVector()
4224 return DAG.getUNDEF(VT); in buildScalarToVector()
4225 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Value); in buildScalarToVector()
4230 static SDValue buildMergeScalars(SelectionDAG &DAG, const SDLoc &DL, EVT VT, in buildMergeScalars() argument
4234 return DAG.getUNDEF(VT); in buildMergeScalars()
4235 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op1); in buildMergeScalars()
4238 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op0); in buildMergeScalars()
4239 return DAG.getNode(SystemZISD::MERGE_HIGH, DL, VT, in buildMergeScalars()
4240 buildScalarToVector(DAG, DL, VT, Op0), in buildMergeScalars()
4241 buildScalarToVector(DAG, DL, VT, Op1)); in buildMergeScalars()
4299 const SDLoc &DL, EVT VT, uint64_t Value, in tryBuildVectorReplicate() argument
4311 return DAG.getNode(ISD::BITCAST, DL, VT, Op); in tryBuildVectorReplicate()
4330 return DAG.getNode(ISD::BITCAST, DL, VT, Op); in tryBuildVectorReplicate()
4341 EVT VT = BVN->getValueType(0); in tryBuildVectorShuffle() local
4342 unsigned NumElements = VT.getVectorNumElements(); in tryBuildVectorShuffle()
4348 GeneralShuffle GS(VT); in tryBuildVectorShuffle()
4380 Op = DAG.getBuildVector(VT, SDLoc(BVN), ResidueOps); in tryBuildVectorShuffle()
4389 static SDValue buildVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT, in buildVector() argument
4420 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Single); in buildVector()
4431 if (VT == MVT::v2i64 && !AllLoads) in buildVector()
4435 if (VT == MVT::v2f64 && !AllLoads) in buildVector()
4436 return buildMergeScalars(DAG, DL, VT, Elems[0], Elems[1]); in buildVector()
4445 if (VT == MVT::v4f32 && !AllLoads) { in buildVector()
4446 SDValue Op01 = buildMergeScalars(DAG, DL, VT, Elems[0], Elems[1]); in buildVector()
4447 SDValue Op23 = buildMergeScalars(DAG, DL, VT, Elems[2], Elems[3]); in buildVector()
4460 return DAG.getNode(ISD::BITCAST, DL, VT, Op); in buildVector()
4486 Result = DAG.getBuildVector(VT, DL, Constants); in buildVector()
4506 Result = DAG.getNode(SystemZISD::REPLICATE, DL, VT, ReplicatedVal); in buildVector()
4516 Result = DAG.getNode(ISD::BITCAST, DL, VT, in buildVector()
4521 Result = DAG.getUNDEF(VT); in buildVector()
4528 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Result, Elems[I], in buildVector()
4539 EVT VT = Op.getValueType(); in lowerBUILD_VECTOR() local
4550 return DAG.getNode(ISD::BITCAST, DL, VT, Op); in lowerBUILD_VECTOR()
4571 SDValue Op = tryBuildVectorReplicate(DAG, TII, DL, VT, Value, in lowerBUILD_VECTOR()
4581 Op = tryBuildVectorReplicate(DAG, TII, DL, VT, Value, SplatBitSize); in lowerBUILD_VECTOR()
4595 if (isOperationLegal(ISD::SCALAR_TO_VECTOR, VT) && isScalarToVector(Op)) in lowerBUILD_VECTOR()
4596 return buildScalarToVector(DAG, DL, VT, Op.getOperand(0)); in lowerBUILD_VECTOR()
4603 return buildVector(DAG, DL, VT, Ops); in lowerBUILD_VECTOR()
4610 EVT VT = Op.getValueType(); in lowerVECTOR_SHUFFLE() local
4611 unsigned NumElements = VT.getVectorNumElements(); in lowerVECTOR_SHUFFLE()
4616 assert(Index < VT.getVectorNumElements() && in lowerVECTOR_SHUFFLE()
4621 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op0.getOperand(Index)); in lowerVECTOR_SHUFFLE()
4623 return DAG.getNode(SystemZISD::SPLAT, DL, VT, Op.getOperand(0), in lowerVECTOR_SHUFFLE()
4627 GeneralShuffle GS(VT); in lowerVECTOR_SHUFFLE()
4655 EVT VT = Op.getValueType(); in lowerINSERT_VECTOR_ELT() local
4660 if (VT == MVT::v2f64 && in lowerINSERT_VECTOR_ELT()
4665 unsigned Mask = VT.getVectorNumElements() - 1; in lowerINSERT_VECTOR_ELT()
4671 MVT IntVT = MVT::getIntegerVT(VT.getScalarSizeInBits()); in lowerINSERT_VECTOR_ELT()
4672 MVT IntVecVT = MVT::getVectorVT(IntVT, VT.getVectorNumElements()); in lowerINSERT_VECTOR_ELT()
4676 return DAG.getNode(ISD::BITCAST, DL, VT, Res); in lowerINSERT_VECTOR_ELT()
4686 EVT VT = Op.getValueType(); in lowerEXTRACT_VECTOR_ELT() local
4698 MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits()); in lowerEXTRACT_VECTOR_ELT()
4702 return DAG.getNode(ISD::BITCAST, DL, VT, Res); in lowerEXTRACT_VECTOR_ELT()
4728 EVT VT = Op.getValueType(); in lowerShift() local
4729 unsigned ElemBitSize = VT.getScalarSizeInBits(); in lowerShift()
4743 return DAG.getNode(ByScalar, DL, VT, Op0, Shift); in lowerShift()
4752 return DAG.getNode(ByScalar, DL, VT, Op0, Shift); in lowerShift()
4762 assert(Index < VT.getVectorNumElements() && in lowerShift()
4770 return DAG.getNode(ByScalar, DL, VT, Op0, Shift); in lowerShift()
5104 bool SystemZTargetLowering::canTreatAsByteVector(EVT VT) const { in canTreatAsByteVector()
5108 return VT.isVector() && VT.getScalarSizeInBits() % 8 == 0 && VT.isSimple(); in canTreatAsByteVector()
5170 EVT VT = MVT::getIntegerVT(Op.getValueSizeInBits()); in combineExtract() local
5171 Op = DAG.getNode(ISD::BITCAST, DL, VT, Op); in combineExtract()
5174 EVT VT = MVT::getIntegerVT(ResVT.getSizeInBits()); in combineExtract() local
5175 Op = DAG.getNode(ISD::TRUNCATE, DL, VT, Op); in combineExtract()
5176 if (VT != ResVT) { in combineExtract()
5262 EVT VT = N->getValueType(0); in combineZERO_EXTEND() local
5268 SDValue Ops[] = { DAG.getConstant(TrueOp->getZExtValue(), DL, VT), in combineZERO_EXTEND()
5269 DAG.getConstant(FalseOp->getZExtValue(), DL, VT), in combineZERO_EXTEND()
5271 SDValue NewSelect = DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VT, Ops); in combineZERO_EXTEND()
5291 EVT VT = N->getValueType(0); in combineSIGN_EXTEND_INREG() local
5298 DAG.getConstant(-1, DL, VT), DAG.getConstant(0, DL, VT), in combineSIGN_EXTEND_INREG()
5300 return DAG.getNode(ISD::SELECT_CC, DL, VT, Ops); in combineSIGN_EXTEND_INREG()
5312 EVT VT = N->getValueType(0); in combineSIGN_EXTEND() local
5318 unsigned Extra = (VT.getSizeInBits() - N0.getValueSizeInBits()); in combineSIGN_EXTEND()
5322 SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SDLoc(Inner), VT, in combineSIGN_EXTEND()
5324 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(Inner), VT, Ext, in combineSIGN_EXTEND()
5327 return DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, in combineSIGN_EXTEND()
5350 EVT VT = Op1.getValueType(); in combineMERGE() local
5351 unsigned ElemBytes = VT.getVectorElementType().getStoreSize(); in combineMERGE()
5355 EVT InVT = VT.changeVectorElementTypeToInteger(); in combineMERGE()
5358 if (VT != InVT) { in combineMERGE()
5364 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op); in combineMERGE()
5806 EVT VT = N->getValueType(0); in combineIntDIVREM() local
5814 if (VT.isVector() && isTypeLegal(VT) && in combineIntDIVREM()
5852 EVT VT = Op.getValueType(); in getDemandedSrcElements() local
5853 unsigned NumElts = (VT.isVector() ? VT.getVectorNumElements() : 1); in getDemandedSrcElements()
5909 assert(VT == MVT::v16i8 && "Unexpected type."); in getDemandedSrcElements()
5975 EVT VT = Op.getValueType(); in computeKnownBitsForTargetNode() local
5976 if (Op.getResNo() != 0 || VT == MVT::Untyped) in computeKnownBitsForTargetNode()
5978 assert (Known.getBitWidth() == VT.getScalarSizeInBits() && in computeKnownBitsForTargetNode()
5980 assert ((!VT.isVector() || in computeKnownBitsForTargetNode()
5981 (DemandedElts.getBitWidth() == VT.getVectorNumElements())) && in computeKnownBitsForTargetNode()
6069 EVT VT = Op.getValueType(); in computeNumSignBitsBinOp() local
6070 unsigned VTBits = VT.getScalarSizeInBits(); in computeNumSignBitsBinOp()
6116 EVT VT = Op.getValueType(); in ComputeNumSignBitsForTargetNode() local
6117 unsigned VTBits = VT.getScalarSizeInBits(); in ComputeNumSignBitsForTargetNode()
7443 SystemZTargetLowering::getRepRegClassFor(MVT VT) const { in getRepRegClassFor()
7444 if (VT == MVT::Untyped) in getRepRegClassFor()
7446 return TargetLowering::getRepRegClassFor(VT); in getRepRegClassFor()