Lines Matching refs:VT
157 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT, in softenSetCCOperands() argument
161 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128) in softenSetCCOperands()
170 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : in softenSetCCOperands()
171 (VT == MVT::f64) ? RTLIB::OEQ_F64 : in softenSetCCOperands()
172 (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128; in softenSetCCOperands()
176 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : in softenSetCCOperands()
177 (VT == MVT::f64) ? RTLIB::UNE_F64 : in softenSetCCOperands()
178 (VT == MVT::f128) ? RTLIB::UNE_F128 : RTLIB::UNE_PPCF128; in softenSetCCOperands()
182 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : in softenSetCCOperands()
183 (VT == MVT::f64) ? RTLIB::OGE_F64 : in softenSetCCOperands()
184 (VT == MVT::f128) ? RTLIB::OGE_F128 : RTLIB::OGE_PPCF128; in softenSetCCOperands()
188 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : in softenSetCCOperands()
189 (VT == MVT::f64) ? RTLIB::OLT_F64 : in softenSetCCOperands()
190 (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128; in softenSetCCOperands()
194 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : in softenSetCCOperands()
195 (VT == MVT::f64) ? RTLIB::OLE_F64 : in softenSetCCOperands()
196 (VT == MVT::f128) ? RTLIB::OLE_F128 : RTLIB::OLE_PPCF128; in softenSetCCOperands()
200 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : in softenSetCCOperands()
201 (VT == MVT::f64) ? RTLIB::OGT_F64 : in softenSetCCOperands()
202 (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128; in softenSetCCOperands()
205 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : in softenSetCCOperands()
206 (VT == MVT::f64) ? RTLIB::UO_F64 : in softenSetCCOperands()
207 (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128; in softenSetCCOperands()
210 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : in softenSetCCOperands()
211 (VT == MVT::f64) ? RTLIB::O_F64 : in softenSetCCOperands()
212 (VT == MVT::f128) ? RTLIB::O_F128 : RTLIB::O_PPCF128; in softenSetCCOperands()
216 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : in softenSetCCOperands()
217 (VT == MVT::f64) ? RTLIB::OLT_F64 : in softenSetCCOperands()
218 (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128; in softenSetCCOperands()
219 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : in softenSetCCOperands()
220 (VT == MVT::f64) ? RTLIB::OGT_F64 : in softenSetCCOperands()
221 (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128; in softenSetCCOperands()
224 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : in softenSetCCOperands()
225 (VT == MVT::f64) ? RTLIB::UO_F64 : in softenSetCCOperands()
226 (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128; in softenSetCCOperands()
227 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : in softenSetCCOperands()
228 (VT == MVT::f64) ? RTLIB::OEQ_F64 : in softenSetCCOperands()
229 (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128; in softenSetCCOperands()
236 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : in softenSetCCOperands()
237 (VT == MVT::f64) ? RTLIB::OGE_F64 : in softenSetCCOperands()
238 (VT == MVT::f128) ? RTLIB::OGE_F128 : RTLIB::OGE_PPCF128; in softenSetCCOperands()
241 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : in softenSetCCOperands()
242 (VT == MVT::f64) ? RTLIB::OGT_F64 : in softenSetCCOperands()
243 (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128; in softenSetCCOperands()
246 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : in softenSetCCOperands()
247 (VT == MVT::f64) ? RTLIB::OLE_F64 : in softenSetCCOperands()
248 (VT == MVT::f128) ? RTLIB::OLE_F128 : RTLIB::OLE_PPCF128; in softenSetCCOperands()
251 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : in softenSetCCOperands()
252 (VT == MVT::f64) ? RTLIB::OLT_F64 : in softenSetCCOperands()
253 (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128; in softenSetCCOperands()
374 EVT VT = Op.getValueType(); in ShrinkDemandedConstant() local
375 SDValue NewC = DAG.getConstant(Demanded & C, DL, VT); in ShrinkDemandedConstant()
376 SDValue NewOp = DAG.getNode(Opcode, DL, VT, Op.getOperand(0), NewC); in ShrinkDemandedConstant()
454 EVT VT = Op.getValueType(); in SimplifyDemandedBits() local
455 APInt DemandedElts = VT.isVector() in SimplifyDemandedBits()
456 ? APInt::getAllOnesValue(VT.getVectorNumElements()) in SimplifyDemandedBits()
498 EVT VT = Op.getValueType(); in SimplifyDemandedBits() local
513 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT)); in SimplifyDemandedBits()
638 SDValue Xor = TLO.DAG.getNode(ISD::XOR, dl, VT, Op0.getOperand(0), Op1); in SimplifyDemandedBits()
659 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, dl, VT)); in SimplifyDemandedBits()
729 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, VT, Op0, Op1)); in SimplifyDemandedBits()
744 TLO.DAG.getConstant(~C->getAPIntValue() & DemandedBits, dl, VT); in SimplifyDemandedBits()
745 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, Op0, ANDC)); in SimplifyDemandedBits()
754 SDValue New = TLO.DAG.getNOT(dl, Op0, VT); in SimplifyDemandedBits()
811 getBooleanContents(VT) == in SimplifyDemandedBits()
859 Op, TLO.DAG.getNode(Opc, dl, VT, Op0.getOperand(0), NewSA)); in SimplifyDemandedBits()
884 Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, NarrowShl)); in SimplifyDemandedBits()
902 SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, in SimplifyDemandedBits()
905 Op, TLO.DAG.getNode(ISD::SHL, dl, VT, NewExt, NewSA)); in SimplifyDemandedBits()
953 Op, TLO.DAG.getNode(Opc, dl, VT, Op0.getOperand(0), NewSA)); in SimplifyDemandedBits()
979 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1)); in SimplifyDemandedBits()
1012 Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1, Flags)); in SimplifyDemandedBits()
1020 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, NewSA)); in SimplifyDemandedBits()
1043 EVT ShiftAmtTy = VT; in SimplifyDemandedBits()
1050 TLO.DAG.getNode(ISD::SHL, dl, VT, Op0, ShiftAmt)); in SimplifyDemandedBits()
1114 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, Src)); in SimplifyDemandedBits()
1130 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, Src)); in SimplifyDemandedBits()
1145 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Src)); in SimplifyDemandedBits()
1197 if (TLO.LegalTypes() && !isTypeDesirableForOp(ISD::SRL, VT)) in SimplifyDemandedBits()
1207 Shift = TLO.DAG.getConstant(ShVal, dl, getShiftAmountTy(VT, DL)); in SimplifyDemandedBits()
1220 TLO.DAG.getNode(ISD::TRUNCATE, dl, VT, Src.getOperand(0)); in SimplifyDemandedBits()
1222 Op, TLO.DAG.getNode(ISD::SRL, dl, VT, NewTrunc, Shift)); in SimplifyDemandedBits()
1279 if (!TLO.LegalOperations() && !VT.isVector() && !SrcVT.isVector() && in SimplifyDemandedBits()
1282 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, VT); in SimplifyDemandedBits()
1284 if ((OpVTLegal || i32Legal) && VT.isSimple() && SrcVT != MVT::f16 && in SimplifyDemandedBits()
1287 EVT Ty = OpVTLegal ? VT : MVT::i32; in SimplifyDemandedBits()
1293 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Sign); in SimplifyDemandedBits()
1295 SDValue ShAmt = TLO.DAG.getConstant(ShVal, dl, VT); in SimplifyDemandedBits()
1297 TLO.DAG.getNode(ISD::SHL, dl, VT, Sign, ShAmt)); in SimplifyDemandedBits()
1356 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1, in SimplifyDemandedBits()
1372 SDValue Neg1 = TLO.DAG.getAllOnesConstant(dl, VT); in SimplifyDemandedBits()
1379 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Neg1, Flags); in SimplifyDemandedBits()
1412 if (VT.isInteger()) in SimplifyDemandedBits()
1413 return TLO.CombineTo(Op, TLO.DAG.getConstant(Known.One, dl, VT)); in SimplifyDemandedBits()
1441 EVT VT = Op.getValueType(); in SimplifyDemandedVectorElts() local
1444 assert(VT.isVector() && "Expected vector op"); in SimplifyDemandedVectorElts()
1445 assert(VT.getVectorNumElements() == NumElts && in SimplifyDemandedVectorElts()
1463 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT)); in SimplifyDemandedVectorElts()
1471 unsigned EltSizeInBits = VT.getScalarSizeInBits(); in SimplifyDemandedVectorElts()
1477 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT)); in SimplifyDemandedVectorElts()
1583 return TLO.CombineTo(Op, TLO.DAG.getBuildVector(VT, DL, Ops)); in SimplifyDemandedVectorElts()
1765 isShuffleMaskLegal(NewMask, VT)) in SimplifyDemandedVectorElts()
1767 TLO.DAG.getVectorShuffle(VT, DL, Op.getOperand(0), in SimplifyDemandedVectorElts()
1804 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, SDLoc(Op), VT)); in SimplifyDemandedVectorElts()
1855 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, SDLoc(Op), VT)); in SimplifyDemandedVectorElts()
1879 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT)); in SimplifyDemandedVectorElts()
2027 bool TargetLowering::isExtendedTrueVal(const ConstantSDNode *N, EVT VT, in isExtendedTrueVal() argument
2029 if (VT == MVT::i1) in isExtendedTrueVal()
2032 TargetLowering::BooleanContent Cnt = getBooleanContents(VT); in isExtendedTrueVal()
2047 SDValue TargetLowering::simplifySetCCWithAnd(EVT VT, SDValue N0, SDValue N1, in simplifySetCCWithAnd() argument
2083 return DAG.getSetCC(DL, VT, N0, Zero, Cond); in simplifySetCCWithAnd()
2100 return DAG.getSetCC(DL, VT, NewAnd, Zero, Cond); in simplifySetCCWithAnd()
2205 SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, in SimplifySetCC() argument
2216 case ISD::SETFALSE2: return DAG.getBoolConstant(false, dl, VT, OpVT); in SimplifySetCC()
2218 case ISD::SETTRUE2: return DAG.getBoolConstant(true, dl, VT, OpVT); in SimplifySetCC()
2227 return DAG.getSetCC(dl, VT, N1, N0, SwappedCC); in SimplifySetCC()
2252 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), in SimplifySetCC()
2275 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, dl, CTVT), CC); in SimplifySetCC()
2331 return DAG.getSetCC(dl, VT, Trunc, DAG.getConstant(0, dl, MVT::i1), in SimplifySetCC()
2334 return DAG.getSetCC(dl, VT, Trunc, C, Cond); in SimplifySetCC()
2348 if (TopSetCC.getValueType() == MVT::i1 && VT == MVT::i1 && in SimplifySetCC()
2363 return DAG.getSetCC(dl, VT, TopSetCC.getOperand(0), in SimplifySetCC()
2421 return DAG.getSetCC(dl, VT, in SimplifySetCC()
2442 return DAG.getConstant(0, dl, VT); in SimplifySetCC()
2446 return DAG.getConstant(1, dl, VT); in SimplifySetCC()
2450 return DAG.getConstant(C1.isNegative(), dl, VT); in SimplifySetCC()
2454 return DAG.getConstant(C1.isNonNegative(), dl, VT); in SimplifySetCC()
2478 return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT, N0.getValueType()); in SimplifySetCC()
2495 return DAG.getConstant(Cond == ISD::SETNE, dl, VT); in SimplifySetCC()
2509 return DAG.getSetCC(dl, VT, ZextOp, in SimplifySetCC()
2519 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { in SimplifySetCC()
2522 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); in SimplifySetCC()
2529 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); in SimplifySetCC()
2557 return DAG.getSetCC(dl, VT, Val, N1, in SimplifySetCC()
2561 (VT == MVT::i1 || in SimplifySetCC()
2573 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), in SimplifySetCC()
2580 if (Op0.getValueType().bitsGT(VT)) in SimplifySetCC()
2581 Op0 = DAG.getNode(ISD::AND, dl, VT, in SimplifySetCC()
2582 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), in SimplifySetCC()
2583 DAG.getConstant(1, dl, VT)); in SimplifySetCC()
2584 else if (Op0.getValueType().bitsLT(VT)) in SimplifySetCC()
2585 Op0 = DAG.getNode(ISD::AND, dl, VT, in SimplifySetCC()
2586 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), in SimplifySetCC()
2587 DAG.getConstant(1, dl, VT)); in SimplifySetCC()
2589 return DAG.getSetCC(dl, VT, Op0, in SimplifySetCC()
2595 return DAG.getSetCC(dl, VT, Op0, in SimplifySetCC()
2602 optimizeSetCCOfSignedTruncationCheck(VT, N0, N1, Cond, DCI, dl)) in SimplifySetCC()
2625 return DAG.getBoolConstant(true, dl, VT, OpVT); in SimplifySetCC()
2627 if (!VT.isVector()) { // TODO: Support this for vectors. in SimplifySetCC()
2632 isCondCodeLegal(NewCC, VT.getSimpleVT())) && in SimplifySetCC()
2635 return DAG.getSetCC(dl, VT, N0, in SimplifySetCC()
2645 return DAG.getBoolConstant(true, dl, VT, OpVT); in SimplifySetCC()
2648 if (!VT.isVector()) { // TODO: Support this for vectors. in SimplifySetCC()
2652 isCondCodeLegal(NewCC, VT.getSimpleVT())) && in SimplifySetCC()
2655 return DAG.getSetCC(dl, VT, N0, in SimplifySetCC()
2664 return DAG.getBoolConstant(false, dl, VT, OpVT); // X < MIN --> false in SimplifySetCC()
2667 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { in SimplifySetCC()
2670 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); in SimplifySetCC()
2674 return DAG.getSetCC(dl, VT, N0, in SimplifySetCC()
2682 return DAG.getBoolConstant(false, dl, VT, OpVT); // X > MAX --> false in SimplifySetCC()
2685 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { in SimplifySetCC()
2688 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); in SimplifySetCC()
2692 return DAG.getSetCC(dl, VT, N0, in SimplifySetCC()
2701 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { in SimplifySetCC()
2705 return DAG.getSetCC(dl, VT, N0, in SimplifySetCC()
2715 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); in SimplifySetCC()
2727 (VT == N0.getValueType() || in SimplifySetCC()
2728 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) && in SimplifySetCC()
2737 return DAG.getNode(ISD::TRUNCATE, dl, VT, in SimplifySetCC()
2746 return DAG.getNode(ISD::TRUNCATE, dl, VT, in SimplifySetCC()
2772 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond); in SimplifySetCC()
2802 return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond); in SimplifySetCC()
2810 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); in SimplifySetCC()
2820 return DAG.getBoolConstant(false, dl, VT, OpVT); in SimplifySetCC()
2822 return DAG.getBoolConstant(true, dl, VT, OpVT); in SimplifySetCC()
2824 return DAG.getUNDEF(VT); in SimplifySetCC()
2833 return DAG.getSetCC(dl, VT, N0, N0, Cond); in SimplifySetCC()
2841 return DAG.getSetCC(dl, VT, N0.getOperand(0), NegN1, SwapCond); in SimplifySetCC()
2855 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); in SimplifySetCC()
2858 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); in SimplifySetCC()
2861 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); in SimplifySetCC()
2864 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); in SimplifySetCC()
2868 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); in SimplifySetCC()
2871 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); in SimplifySetCC()
2874 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); in SimplifySetCC()
2877 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); in SimplifySetCC()
2891 return DAG.getBoolConstant(EqTrue, dl, VT, OpVT); in SimplifySetCC()
2895 return DAG.getBoolConstant(EqTrue, dl, VT, OpVT); in SimplifySetCC()
2897 return DAG.getBoolConstant(EqTrue, dl, VT, OpVT); in SimplifySetCC()
2904 return DAG.getSetCC(dl, VT, N0, N1, NewCond); in SimplifySetCC()
2914 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); in SimplifySetCC()
2916 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); in SimplifySetCC()
2920 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), in SimplifySetCC()
2923 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), in SimplifySetCC()
2936 return DAG.getSetCC(dl, VT, N0.getOperand(0), in SimplifySetCC()
2948 DAG.getSetCC(dl, VT, N0.getOperand(0), in SimplifySetCC()
2959 DAG.getSetCC(dl, VT, N0.getOperand(1), in SimplifySetCC()
2978 return DAG.getSetCC(dl, VT, N0.getOperand(1), in SimplifySetCC()
2982 return DAG.getSetCC(dl, VT, N0.getOperand(0), in SimplifySetCC()
2996 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); in SimplifySetCC()
3006 return DAG.getSetCC(dl, VT, N1.getOperand(1), in SimplifySetCC()
3010 return DAG.getSetCC(dl, VT, N1.getOperand(0), in SimplifySetCC()
3022 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); in SimplifySetCC()
3027 if (SDValue V = simplifySetCCWithAnd(VT, N0, N1, Cond, DCI, dl)) in SimplifySetCC()
3073 if (VT.getScalarType() != MVT::i1) { in SimplifySetCC()
3078 N0 = DAG.getNode(ExtendCode, dl, VT, N0); in SimplifySetCC()
3253 MVT VT) const { in getRegForInlineAsmConstraint()
3280 if (RI->isTypeLegalForClass(*RC, VT)) in getRegForInlineAsmConstraint()
3697 EVT VT = N->getValueType(0); in BuildExactSDIV() local
3698 EVT SVT = VT.getScalarType(); in BuildExactSDIV()
3699 EVT ShVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout()); in BuildExactSDIV()
3729 if (VT.isVector()) { in BuildExactSDIV()
3731 Factor = DAG.getBuildVector(VT, dl, Factors); in BuildExactSDIV()
3744 Res = DAG.getNode(ISD::SRA, dl, VT, Res, Shift, Flags); in BuildExactSDIV()
3748 return DAG.getNode(ISD::MUL, dl, VT, Res, Factor); in BuildExactSDIV()
3769 EVT VT = N->getValueType(0); in BuildSDIV() local
3770 EVT SVT = VT.getScalarType(); in BuildSDIV()
3771 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout()); in BuildSDIV()
3773 unsigned EltBits = VT.getScalarSizeInBits(); in BuildSDIV()
3777 if (!isTypeLegal(VT)) in BuildSDIV()
3824 if (VT.isVector()) { in BuildSDIV()
3825 MagicFactor = DAG.getBuildVector(VT, dl, MagicFactors); in BuildSDIV()
3826 Factor = DAG.getBuildVector(VT, dl, Factors); in BuildSDIV()
3828 ShiftMask = DAG.getBuildVector(VT, dl, ShiftMasks); in BuildSDIV()
3839 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) in BuildSDIV()
3840 : isOperationLegalOrCustom(ISD::MULHS, VT)) in BuildSDIV()
3841 Q = DAG.getNode(ISD::MULHS, dl, VT, N0, MagicFactor); in BuildSDIV()
3842 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) in BuildSDIV()
3843 : isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) { in BuildSDIV()
3845 DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), N0, MagicFactor); in BuildSDIV()
3852 Factor = DAG.getNode(ISD::MUL, dl, VT, N0, Factor); in BuildSDIV()
3854 Q = DAG.getNode(ISD::ADD, dl, VT, Q, Factor); in BuildSDIV()
3858 Q = DAG.getNode(ISD::SRA, dl, VT, Q, Shift); in BuildSDIV()
3863 SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q, SignShift); in BuildSDIV()
3865 T = DAG.getNode(ISD::AND, dl, VT, T, ShiftMask); in BuildSDIV()
3867 return DAG.getNode(ISD::ADD, dl, VT, Q, T); in BuildSDIV()
3878 EVT VT = N->getValueType(0); in BuildUDIV() local
3879 EVT SVT = VT.getScalarType(); in BuildUDIV()
3880 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout()); in BuildUDIV()
3882 unsigned EltBits = VT.getScalarSizeInBits(); in BuildUDIV()
3886 if (!isTypeLegal(VT)) in BuildUDIV()
3942 if (VT.isVector()) { in BuildUDIV()
3944 MagicFactor = DAG.getBuildVector(VT, dl, MagicFactors); in BuildUDIV()
3945 NPQFactor = DAG.getBuildVector(VT, dl, NPQFactors); in BuildUDIV()
3954 Q = DAG.getNode(ISD::SRL, dl, VT, Q, PreShift); in BuildUDIV()
3959 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) in BuildUDIV()
3960 : isOperationLegalOrCustom(ISD::MULHU, VT)) in BuildUDIV()
3961 return DAG.getNode(ISD::MULHU, dl, VT, X, Y); in BuildUDIV()
3962 if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) in BuildUDIV()
3963 : isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) { in BuildUDIV()
3965 DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), X, Y); in BuildUDIV()
3979 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N0, Q); in BuildUDIV()
3984 if (VT.isVector()) in BuildUDIV()
3987 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, DAG.getConstant(1, dl, ShVT)); in BuildUDIV()
3991 Q = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); in BuildUDIV()
3995 Q = DAG.getNode(ISD::SRL, dl, VT, Q, PostShift); in BuildUDIV()
3998 SDValue One = DAG.getConstant(1, dl, VT); in BuildUDIV()
3999 SDValue IsOne = DAG.getSetCC(dl, VT, N1, One, ISD::SETEQ); in BuildUDIV()
4000 return DAG.getSelect(dl, VT, IsOne, N0, Q); in BuildUDIV()
4018 bool TargetLowering::expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, in expandMUL_LOHI() argument
4039 unsigned OuterBitSize = VT.getScalarSizeInBits(); in expandMUL_LOHI()
4091 if (!VT.isVector() && Opcode == ISD::MUL && LHSSB > InnerBitSize && in expandMUL_LOHI()
4103 EVT ShiftAmountTy = getShiftAmountTy(VT, DAG.getDataLayout()); in expandMUL_LOHI()
4113 isOperationLegalOrCustom(ISD::SRL, VT) && in expandMUL_LOHI()
4115 LH = DAG.getNode(ISD::SRL, dl, VT, LHS, Shift); in expandMUL_LOHI()
4117 RH = DAG.getNode(ISD::SRL, dl, VT, RHS, Shift); in expandMUL_LOHI()
4140 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo); in expandMUL_LOHI()
4141 Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Hi); in expandMUL_LOHI()
4142 Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift); in expandMUL_LOHI()
4143 return DAG.getNode(ISD::OR, dl, VT, Lo, Hi); in expandMUL_LOHI()
4146 SDValue Next = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Hi); in expandMUL_LOHI()
4152 Next = DAG.getNode(ISD::ADD, dl, VT, Next, Merge(Lo, Hi)); in expandMUL_LOHI()
4158 EVT BoolType = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); in expandMUL_LOHI()
4160 bool UseGlue = (isOperationLegalOrCustom(ISD::ADDC, VT) && in expandMUL_LOHI()
4161 isOperationLegalOrCustom(ISD::ADDE, VT)); in expandMUL_LOHI()
4163 Next = DAG.getNode(ISD::ADDC, dl, DAG.getVTList(VT, MVT::Glue), Next, in expandMUL_LOHI()
4166 Next = DAG.getNode(ISD::ADDCARRY, dl, DAG.getVTList(VT, BoolType), Next, in expandMUL_LOHI()
4171 Next = DAG.getNode(ISD::SRL, dl, VT, Next, Shift); in expandMUL_LOHI()
4183 Next = DAG.getNode(ISD::ADD, dl, VT, Next, Merge(Lo, Hi)); in expandMUL_LOHI()
4186 SDValue NextSub = DAG.getNode(ISD::SUB, dl, VT, Next, in expandMUL_LOHI()
4187 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, RL)); in expandMUL_LOHI()
4190 NextSub = DAG.getNode(ISD::SUB, dl, VT, Next, in expandMUL_LOHI()
4191 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, LL)); in expandMUL_LOHI()
4196 Next = DAG.getNode(ISD::SRL, dl, VT, Next, Shift); in expandMUL_LOHI()
4219 EVT VT = Node->getValueType(0); in expandFunnelShift() local
4221 if (VT.isVector() && (!isOperationLegalOrCustom(ISD::SHL, VT) || in expandFunnelShift()
4222 !isOperationLegalOrCustom(ISD::SRL, VT) || in expandFunnelShift()
4223 !isOperationLegalOrCustom(ISD::SUB, VT) || in expandFunnelShift()
4224 !isOperationLegalOrCustomOrPromote(ISD::OR, VT))) in expandFunnelShift()
4233 unsigned EltSizeInBits = VT.getScalarSizeInBits(); in expandFunnelShift()
4250 SDValue ShX = DAG.getNode(ISD::SHL, DL, VT, X, IsFSHL ? ShAmt : InvShAmt); in expandFunnelShift()
4251 SDValue ShY = DAG.getNode(ISD::SRL, DL, VT, Y, IsFSHL ? InvShAmt : ShAmt); in expandFunnelShift()
4252 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShX, ShY); in expandFunnelShift()
4261 Result = DAG.getSelect(DL, VT, IsZeroShift, IsFSHL ? X : Y, Or); in expandFunnelShift()
4268 EVT VT = Node->getValueType(0); in expandROT() local
4269 unsigned EltSizeInBits = VT.getScalarSizeInBits(); in expandROT()
4280 if (isOperationLegal(RevRot, VT)) { in expandROT()
4282 Result = DAG.getNode(RevRot, DL, VT, Op0, Sub); in expandROT()
4286 if (VT.isVector() && (!isOperationLegalOrCustom(ISD::SHL, VT) || in expandROT()
4287 !isOperationLegalOrCustom(ISD::SRL, VT) || in expandROT()
4288 !isOperationLegalOrCustom(ISD::SUB, VT) || in expandROT()
4289 !isOperationLegalOrCustomOrPromote(ISD::OR, VT) || in expandROT()
4290 !isOperationLegalOrCustomOrPromote(ISD::AND, VT))) in expandROT()
4305 Result = DAG.getNode(ISD::OR, DL, VT, DAG.getNode(ShOpc, DL, VT, Op0, And0), in expandROT()
4306 DAG.getNode(HsOpc, DL, VT, Op0, And1)); in expandROT()
4526 EVT VT = Node->getValueType(0); in expandFMINNUM_FMAXNUM() local
4527 if (isOperationLegalOrCustom(NewOp, VT)) { in expandFMINNUM_FMAXNUM()
4535 Quiet0 = DAG.getNode(ISD::FCANONICALIZE, dl, VT, Quiet0, in expandFMINNUM_FMAXNUM()
4539 Quiet1 = DAG.getNode(ISD::FCANONICALIZE, dl, VT, Quiet1, in expandFMINNUM_FMAXNUM()
4544 return DAG.getNode(NewOp, dl, VT, Quiet0, Quiet1, Node->getFlags()); in expandFMINNUM_FMAXNUM()
4553 EVT VT = Node->getValueType(0); in expandCTPOP() local
4554 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout()); in expandCTPOP()
4556 unsigned Len = VT.getScalarSizeInBits(); in expandCTPOP()
4557 assert(VT.isInteger() && "CTPOP not implemented for this type."); in expandCTPOP()
4564 if (VT.isVector() && (!isOperationLegalOrCustom(ISD::ADD, VT) || in expandCTPOP()
4565 !isOperationLegalOrCustom(ISD::SUB, VT) || in expandCTPOP()
4566 !isOperationLegalOrCustom(ISD::SRL, VT) || in expandCTPOP()
4567 (Len != 8 && !isOperationLegalOrCustom(ISD::MUL, VT)) || in expandCTPOP()
4568 !isOperationLegalOrCustomOrPromote(ISD::AND, VT))) in expandCTPOP()
4574 DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), dl, VT); in expandCTPOP()
4576 DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), dl, VT); in expandCTPOP()
4578 DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), dl, VT); in expandCTPOP()
4580 DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)), dl, VT); in expandCTPOP()
4583 Op = DAG.getNode(ISD::SUB, dl, VT, Op, in expandCTPOP()
4584 DAG.getNode(ISD::AND, dl, VT, in expandCTPOP()
4585 DAG.getNode(ISD::SRL, dl, VT, Op, in expandCTPOP()
4589 Op = DAG.getNode(ISD::ADD, dl, VT, DAG.getNode(ISD::AND, dl, VT, Op, Mask33), in expandCTPOP()
4590 DAG.getNode(ISD::AND, dl, VT, in expandCTPOP()
4591 DAG.getNode(ISD::SRL, dl, VT, Op, in expandCTPOP()
4595 Op = DAG.getNode(ISD::AND, dl, VT, in expandCTPOP()
4596 DAG.getNode(ISD::ADD, dl, VT, Op, in expandCTPOP()
4597 DAG.getNode(ISD::SRL, dl, VT, Op, in expandCTPOP()
4603 DAG.getNode(ISD::SRL, dl, VT, DAG.getNode(ISD::MUL, dl, VT, Op, Mask01), in expandCTPOP()
4613 EVT VT = Node->getValueType(0); in expandCTLZ() local
4614 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout()); in expandCTLZ()
4616 unsigned NumBitsPerElt = VT.getScalarSizeInBits(); in expandCTLZ()
4620 isOperationLegalOrCustom(ISD::CTLZ, VT)) { in expandCTLZ()
4621 Result = DAG.getNode(ISD::CTLZ, dl, VT, Op); in expandCTLZ()
4626 if (isOperationLegalOrCustom(ISD::CTLZ_ZERO_UNDEF, VT)) { in expandCTLZ()
4628 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); in expandCTLZ()
4629 SDValue CTLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, VT, Op); in expandCTLZ()
4630 SDValue Zero = DAG.getConstant(0, dl, VT); in expandCTLZ()
4632 Result = DAG.getNode(ISD::SELECT, dl, VT, SrcIsZero, in expandCTLZ()
4633 DAG.getConstant(NumBitsPerElt, dl, VT), CTLZ); in expandCTLZ()
4638 if (VT.isVector() && (!isPowerOf2_32(NumBitsPerElt) || in expandCTLZ()
4639 !isOperationLegalOrCustom(ISD::CTPOP, VT) || in expandCTLZ()
4640 !isOperationLegalOrCustom(ISD::SRL, VT) || in expandCTLZ()
4641 !isOperationLegalOrCustomOrPromote(ISD::OR, VT))) in expandCTLZ()
4655 Op = DAG.getNode(ISD::OR, dl, VT, Op, in expandCTLZ()
4656 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp)); in expandCTLZ()
4658 Op = DAG.getNOT(dl, Op, VT); in expandCTLZ()
4659 Result = DAG.getNode(ISD::CTPOP, dl, VT, Op); in expandCTLZ()
4666 EVT VT = Node->getValueType(0); in expandCTTZ() local
4668 unsigned NumBitsPerElt = VT.getScalarSizeInBits(); in expandCTTZ()
4672 isOperationLegalOrCustom(ISD::CTTZ, VT)) { in expandCTTZ()
4673 Result = DAG.getNode(ISD::CTTZ, dl, VT, Op); in expandCTTZ()
4678 if (isOperationLegalOrCustom(ISD::CTTZ_ZERO_UNDEF, VT)) { in expandCTTZ()
4680 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); in expandCTTZ()
4681 SDValue CTTZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, VT, Op); in expandCTTZ()
4682 SDValue Zero = DAG.getConstant(0, dl, VT); in expandCTTZ()
4684 Result = DAG.getNode(ISD::SELECT, dl, VT, SrcIsZero, in expandCTTZ()
4685 DAG.getConstant(NumBitsPerElt, dl, VT), CTTZ); in expandCTTZ()
4690 if (VT.isVector() && (!isPowerOf2_32(NumBitsPerElt) || in expandCTTZ()
4691 (!isOperationLegalOrCustom(ISD::CTPOP, VT) && in expandCTTZ()
4692 !isOperationLegalOrCustom(ISD::CTLZ, VT)) || in expandCTTZ()
4693 !isOperationLegalOrCustom(ISD::SUB, VT) || in expandCTTZ()
4694 !isOperationLegalOrCustomOrPromote(ISD::AND, VT) || in expandCTTZ()
4695 !isOperationLegalOrCustomOrPromote(ISD::XOR, VT))) in expandCTTZ()
4703 ISD::AND, dl, VT, DAG.getNOT(dl, Op, VT), in expandCTTZ()
4704 DAG.getNode(ISD::SUB, dl, VT, Op, DAG.getConstant(1, dl, VT))); in expandCTTZ()
4707 if (isOperationLegal(ISD::CTLZ, VT) && !isOperationLegal(ISD::CTPOP, VT)) { in expandCTTZ()
4709 DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(NumBitsPerElt, dl, VT), in expandCTTZ()
4710 DAG.getNode(ISD::CTLZ, dl, VT, Tmp)); in expandCTTZ()
4714 Result = DAG.getNode(ISD::CTPOP, dl, VT, Tmp); in expandCTTZ()
4721 EVT VT = N->getValueType(0); in expandABS() local
4722 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout()); in expandABS()
4726 if (VT.isVector() && (!isOperationLegalOrCustom(ISD::SRA, VT) || in expandABS()
4727 !isOperationLegalOrCustom(ISD::ADD, VT) || in expandABS()
4728 !isOperationLegalOrCustomOrPromote(ISD::XOR, VT))) in expandABS()
4732 DAG.getNode(ISD::SRA, dl, VT, Op, in expandABS()
4733 DAG.getConstant(VT.getScalarSizeInBits() - 1, dl, ShVT)); in expandABS()
4734 SDValue Add = DAG.getNode(ISD::ADD, dl, VT, Op, Shift); in expandABS()
4735 Result = DAG.getNode(ISD::XOR, dl, VT, Add, Shift); in expandABS()
4857 EVT VT = LD->getValueType(0); in expandUnalignedLoad() local
4862 if (VT.isFloatingPoint() || VT.isVector()) { in expandUnalignedLoad()
4879 if (LoadedVT != VT) in expandUnalignedLoad()
4880 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND : in expandUnalignedLoad()
4881 ISD::ANY_EXTEND, dl, VT, Result); in expandUnalignedLoad()
4943 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase, in expandUnalignedLoad()
4972 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(), in expandUnalignedLoad()
4977 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, in expandUnalignedLoad()
4982 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(), in expandUnalignedLoad()
4987 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, in expandUnalignedLoad()
4997 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); in expandUnalignedLoad()
4998 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); in expandUnalignedLoad()
5013 EVT VT = Val.getValueType(); in expandUnalignedStore() local
5020 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); in expandUnalignedStore()
5116 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); in expandUnalignedStore()
5262 EVT VT = Op.getOperand(0).getValueType(); in lowerCmpEqZeroToCtlzSrl() local
5264 if (VT.bitsLT(MVT::i32)) { in lowerCmpEqZeroToCtlzSrl()
5265 VT = MVT::i32; in lowerCmpEqZeroToCtlzSrl()
5266 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0)); in lowerCmpEqZeroToCtlzSrl()
5268 unsigned Log2b = Log2_32(VT.getSizeInBits()); in lowerCmpEqZeroToCtlzSrl()
5269 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); in lowerCmpEqZeroToCtlzSrl()
5270 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz, in lowerCmpEqZeroToCtlzSrl()
5282 EVT VT = LHS.getValueType(); in expandAddSubSat() local
5286 if (Opcode == ISD::USUBSAT && isOperationLegalOrCustom(ISD::UMAX, VT)) { in expandAddSubSat()
5287 SDValue Max = DAG.getNode(ISD::UMAX, dl, VT, LHS, RHS); in expandAddSubSat()
5288 return DAG.getNode(ISD::SUB, dl, VT, Max, RHS); in expandAddSubSat()
5291 if (VT.isVector()) { in expandAddSubSat()
5377 EVT VT = LHS.getValueType(); in getExpandedFixedPointMultiplication() local
5378 assert(Scale < VT.getScalarSizeInBits() && in getExpandedFixedPointMultiplication()
5382 return DAG.getNode(ISD::MUL, dl, VT, LHS, RHS); in getExpandedFixedPointMultiplication()
5386 if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) { in getExpandedFixedPointMultiplication()
5388 DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), LHS, RHS); in getExpandedFixedPointMultiplication()
5391 } else if (isOperationLegalOrCustom(ISD::MULHS, VT)) { in getExpandedFixedPointMultiplication()
5392 Lo = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS); in getExpandedFixedPointMultiplication()
5393 Hi = DAG.getNode(ISD::MULHS, dl, VT, LHS, RHS); in getExpandedFixedPointMultiplication()
5401 EVT ShiftTy = getShiftAmountTy(VT, DAG.getDataLayout()); in getExpandedFixedPointMultiplication()
5402 Lo = DAG.getNode(ISD::SRL, dl, VT, Lo, DAG.getConstant(Scale, dl, ShiftTy)); in getExpandedFixedPointMultiplication()
5404 ISD::SHL, dl, VT, Hi, in getExpandedFixedPointMultiplication()
5405 DAG.getConstant(VT.getScalarSizeInBits() - Scale, dl, ShiftTy)); in getExpandedFixedPointMultiplication()
5406 return DAG.getNode(ISD::OR, dl, VT, Lo, Hi); in getExpandedFixedPointMultiplication()