Lines Matching refs:VT
192 bool isTypeLegal(Type *Ty, MVT &VT);
193 bool isLoadTypeLegal(Type *Ty, MVT &VT);
196 bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
199 bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
202 void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3);
207 unsigned ARMMaterializeFP(const ConstantFP *CFP, MVT VT);
208 unsigned ARMMaterializeInt(const Constant *C, MVT VT);
209 unsigned ARMMaterializeGV(const GlobalValue *GV, MVT VT);
210 unsigned ARMMoveToFPReg(MVT VT, unsigned SrcReg);
211 unsigned ARMMoveToIntReg(MVT VT, unsigned SrcReg);
213 unsigned ARMLowerPICELF(const GlobalValue *GV, unsigned Align, MVT VT);
241 void AddLoadStoreOperands(MVT VT, Address &Addr,
401 unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) { in ARMMoveToFPReg() argument
402 if (VT == MVT::f64) return 0; in ARMMoveToFPReg()
404 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMoveToFPReg()
411 unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) { in ARMMoveToIntReg() argument
412 if (VT == MVT::i64) return 0; in ARMMoveToIntReg()
414 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMoveToIntReg()
424 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) { in ARMMaterializeFP() argument
426 bool is64bit = VT == MVT::f64; in ARMMaterializeFP()
430 if (TLI.isFPImmLegal(Val, VT)) { in ARMMaterializeFP()
440 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeFP()
456 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeFP()
467 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) { in ARMMaterializeInt() argument
468 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1) in ARMMaterializeInt()
486 if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) { in ARMMaterializeInt()
504 ResultReg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); in ARMMaterializeInt()
510 if (VT != MVT::i32) in ARMMaterializeInt()
520 ResultReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeInt()
540 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) { in ARMMaterializeGV() argument
542 if (VT != MVT::i32 || GV->isThreadLocal()) return 0; in ARMMaterializeGV()
583 return ARMLowerPICELF(GV, Align, VT); in ARMMaterializeGV()
613 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeGV()
627 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeGV()
650 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant() local
653 return ARMMaterializeFP(CFP, VT); in fastMaterializeConstant()
655 return ARMMaterializeGV(GV, VT); in fastMaterializeConstant()
657 return ARMMaterializeInt(C, VT); in fastMaterializeConstant()
668 MVT VT; in fastMaterializeAlloca() local
669 if (!isLoadTypeLegal(AI->getType(), VT)) return 0; in fastMaterializeAlloca()
678 const TargetRegisterClass* RC = TLI.getRegClassFor(VT); in fastMaterializeAlloca()
692 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) { in isTypeLegal() argument
697 VT = evt.getSimpleVT(); in isTypeLegal()
701 return TLI.isTypeLegal(VT); in isTypeLegal()
704 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) { in isLoadTypeLegal() argument
705 if (isTypeLegal(Ty, VT)) return true; in isLoadTypeLegal()
709 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16) in isLoadTypeLegal()
821 void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) { in ARMSimplifyAddress() argument
823 switch (VT.SimpleTy) { in ARMSimplifyAddress()
873 void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr, in AddLoadStoreOperands() argument
879 if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64) in AddLoadStoreOperands()
919 bool ARMFastISel::ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, in ARMEmitLoad() argument
925 switch (VT.SimpleTy) { in ARMEmitLoad()
979 VT = MVT::i32; in ARMEmitLoad()
984 RC = TLI.getRegClassFor(VT); in ARMEmitLoad()
995 RC = TLI.getRegClassFor(VT); in ARMEmitLoad()
999 ARMSimplifyAddress(Addr, VT, useAM3); in ARMEmitLoad()
1007 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3); in ARMEmitLoad()
1042 MVT VT; in SelectLoad() local
1043 if (!isLoadTypeLegal(I->getType(), VT)) in SelectLoad()
1051 if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment())) in SelectLoad()
1057 bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr, in ARMEmitStore() argument
1061 switch (VT.SimpleTy) { in ARMEmitStore()
1121 VT = MVT::i32; in ARMEmitStore()
1138 ARMSimplifyAddress(Addr, VT, useAM3); in ARMEmitStore()
1145 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3); in ARMEmitStore()
1173 MVT VT; in SelectStore() local
1174 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT)) in SelectStore()
1186 if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment())) in SelectStore()
1627 MVT VT; in SelectSelect() local
1628 if (!isTypeLegal(I->getType(), VT)) in SelectSelect()
1632 if (VT != MVT::i32) return false; in SelectSelect()
1644 assert(VT == MVT::i32 && "Expecting an i32."); in SelectSelect()
1703 MVT VT; in SelectDiv() local
1705 if (!isTypeLegal(Ty, VT)) in SelectDiv()
1716 if (VT == MVT::i8) in SelectDiv()
1718 else if (VT == MVT::i16) in SelectDiv()
1720 else if (VT == MVT::i32) in SelectDiv()
1722 else if (VT == MVT::i64) in SelectDiv()
1724 else if (VT == MVT::i128) in SelectDiv()
1732 MVT VT; in SelectRem() local
1734 if (!isTypeLegal(Ty, VT)) in SelectRem()
1740 if (!TLI.hasStandaloneRem(VT)) { in SelectRem()
1745 if (VT == MVT::i8) in SelectRem()
1747 else if (VT == MVT::i16) in SelectRem()
1749 else if (VT == MVT::i32) in SelectRem()
1751 else if (VT == MVT::i64) in SelectRem()
1753 else if (VT == MVT::i128) in SelectRem()
1803 MVT VT = FPVT.getSimpleVT(); in SelectBinaryFPOp() local
1806 if (VT.isVector()) in SelectBinaryFPOp()
1820 bool is64bit = VT == MVT::f64 || VT == MVT::i64; in SelectBinaryFPOp()
1839 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); in SelectBinaryFPOp()
2460 MVT VT; in ARMTryEmitSmallMemCpy() local
2463 VT = MVT::i32; in ARMTryEmitSmallMemCpy()
2465 VT = MVT::i16; in ARMTryEmitSmallMemCpy()
2468 VT = MVT::i8; in ARMTryEmitSmallMemCpy()
2473 VT = MVT::i16; in ARMTryEmitSmallMemCpy()
2475 VT = MVT::i8; in ARMTryEmitSmallMemCpy()
2481 RV = ARMEmitLoad(VT, ResultReg, Src); in ARMTryEmitSmallMemCpy()
2483 RV = ARMEmitStore(VT, ResultReg, Dest); in ARMTryEmitSmallMemCpy()
2487 unsigned Size = VT.getSizeInBits()/8; in ARMTryEmitSmallMemCpy()
2923 MVT VT; in tryToFoldLoadIntoMI() local
2924 if (!isLoadTypeLegal(LI->getType(), VT)) in tryToFoldLoadIntoMI()
2940 MVT((MVT::SimpleValueType)FLE.ExpectedVT) == VT) { in tryToFoldLoadIntoMI()
2952 if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false)) in tryToFoldLoadIntoMI()
2960 unsigned Align, MVT VT) { in ARMLowerPICELF() argument
2989 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMLowerPICELF()
3001 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMLowerPICELF()