Lines Matching refs:VT
74 for (MVT VT : MVT::integer_valuetypes()) { in R600TargetLowering() local
75 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
76 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
77 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
79 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
80 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
81 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
83 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
84 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
85 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
257 for (MVT VT : ScalarIntVTs) { in R600TargetLowering() local
258 setOperationAction(ISD::ADDC, VT, Expand); in R600TargetLowering()
259 setOperationAction(ISD::SUBC, VT, Expand); in R600TargetLowering()
260 setOperationAction(ISD::ADDE, VT, Expand); in R600TargetLowering()
261 setOperationAction(ISD::SUBE, VT, Expand); in R600TargetLowering()
529 EVT VT = Op.getValueType(); in LowerOperation() local
597 return LowerImplicitParameter(DAG, VT, DL, 0); in LowerOperation()
599 return LowerImplicitParameter(DAG, VT, DL, 1); in LowerOperation()
601 return LowerImplicitParameter(DAG, VT, DL, 2); in LowerOperation()
603 return LowerImplicitParameter(DAG, VT, DL, 3); in LowerOperation()
605 return LowerImplicitParameter(DAG, VT, DL, 4); in LowerOperation()
607 return LowerImplicitParameter(DAG, VT, DL, 5); in LowerOperation()
609 return LowerImplicitParameter(DAG, VT, DL, 6); in LowerOperation()
611 return LowerImplicitParameter(DAG, VT, DL, 7); in LowerOperation()
613 return LowerImplicitParameter(DAG, VT, DL, 8); in LowerOperation()
617 R600::T1_X, VT); in LowerOperation()
620 R600::T1_Y, VT); in LowerOperation()
623 R600::T1_Z, VT); in LowerOperation()
626 R600::T0_X, VT); in LowerOperation()
629 R600::T0_Y, VT); in LowerOperation()
632 R600::T0_Z, VT); in LowerOperation()
635 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1)); in LowerOperation()
638 return DAG.getNode(AMDGPUISD::RSQ_CLAMP, DL, VT, Op.getOperand(1)); in LowerOperation()
758 EVT VT = Op.getValueType(); in LowerTrig() local
763 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, DL, VT, in LowerTrig()
764 DAG.getNode(ISD::FADD, DL, VT, in LowerTrig()
765 DAG.getNode(ISD::FMUL, DL, VT, Arg, in LowerTrig()
779 SDValue TrigVal = DAG.getNode(TrigNode, DL, VT, in LowerTrig()
780 DAG.getNode(ISD::FADD, DL, VT, FractPart, in LowerTrig()
785 return DAG.getNode(ISD::FMUL, DL, VT, TrigVal, in LowerTrig()
791 EVT VT = Op.getValueType(); in LowerSHLParts() local
796 SDValue Zero = DAG.getConstant(0, DL, VT); in LowerSHLParts()
797 SDValue One = DAG.getConstant(1, DL, VT); in LowerSHLParts()
799 SDValue Width = DAG.getConstant(VT.getSizeInBits(), DL, VT); in LowerSHLParts()
800 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT); in LowerSHLParts()
801 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width); in LowerSHLParts()
802 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift); in LowerSHLParts()
809 SDValue Overflow = DAG.getNode(ISD::SRL, DL, VT, Lo, CompShift); in LowerSHLParts()
810 Overflow = DAG.getNode(ISD::SRL, DL, VT, Overflow, One); in LowerSHLParts()
812 SDValue HiSmall = DAG.getNode(ISD::SHL, DL, VT, Hi, Shift); in LowerSHLParts()
813 HiSmall = DAG.getNode(ISD::OR, DL, VT, HiSmall, Overflow); in LowerSHLParts()
814 SDValue LoSmall = DAG.getNode(ISD::SHL, DL, VT, Lo, Shift); in LowerSHLParts()
816 SDValue HiBig = DAG.getNode(ISD::SHL, DL, VT, Lo, BigShift); in LowerSHLParts()
822 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi); in LowerSHLParts()
827 EVT VT = Op.getValueType(); in LowerSRXParts() local
832 SDValue Zero = DAG.getConstant(0, DL, VT); in LowerSRXParts()
833 SDValue One = DAG.getConstant(1, DL, VT); in LowerSRXParts()
837 SDValue Width = DAG.getConstant(VT.getSizeInBits(), DL, VT); in LowerSRXParts()
838 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT); in LowerSRXParts()
839 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width); in LowerSRXParts()
840 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift); in LowerSRXParts()
847 SDValue Overflow = DAG.getNode(ISD::SHL, DL, VT, Hi, CompShift); in LowerSRXParts()
848 Overflow = DAG.getNode(ISD::SHL, DL, VT, Overflow, One); in LowerSRXParts()
850 SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift); in LowerSRXParts()
851 SDValue LoSmall = DAG.getNode(ISD::SRL, DL, VT, Lo, Shift); in LowerSRXParts()
852 LoSmall = DAG.getNode(ISD::OR, DL, VT, LoSmall, Overflow); in LowerSRXParts()
854 SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift); in LowerSRXParts()
855 SDValue HiBig = SRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, Width1) : Zero; in LowerSRXParts()
860 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi); in LowerSRXParts()
866 EVT VT = Op.getValueType(); in LowerUADDSUBO() local
871 SDValue OVF = DAG.getNode(ovf, DL, VT, Lo, Hi); in LowerUADDSUBO()
873 OVF = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, OVF, in LowerUADDSUBO()
876 SDValue Res = DAG.getNode(mainop, DL, VT, Lo, Hi); in LowerUADDSUBO()
878 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF); in LowerUADDSUBO()
901 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT, in LowerImplicitParameter() argument
905 PointerType * PtrType = PointerType::get(VT.getTypeForEVT(*DAG.getContext()), in LowerImplicitParameter()
911 return DAG.getLoad(VT, DL, DAG.getEntryNode(), in LowerImplicitParameter()
942 EVT VT = Op.getValueType(); in LowerSELECT_CC() local
951 if (VT == MVT::f32) { in LowerSELECT_CC()
953 SDValue MinMax = combineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI); in LowerSELECT_CC()
991 (CompareVT == VT || VT == MVT::i32)) { in LowerSELECT_CC()
993 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC); in LowerSELECT_CC()
1029 if (CompareVT != VT) { in LowerSELECT_CC()
1054 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode); in LowerSELECT_CC()
1076 return DAG.getNode(ISD::SELECT_CC, DL, VT, in LowerSELECT_CC()
1237 EVT VT = Value.getValueType(); in LowerSTORE() local
1245 VT.isVector()) { in LowerSTORE()
1274 assert(VT.bitsLE(MVT::i32)); in LowerSTORE()
1286 SDValue BitShift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex, in LowerSTORE()
1287 DAG.getConstant(3, DL, VT)); in LowerSTORE()
1290 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, BitShift); in LowerSTORE()
1293 SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant); in LowerSTORE()
1294 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, BitShift); in LowerSTORE()
1309 } else if (Ptr->getOpcode() != AMDGPUISD::DWORDADDR && VT.bitsGE(MVT::i32)) { in LowerSTORE()
1450 EVT VT = Op.getValueType(); in LowerLOAD() local
1456 VT.isVector()) { in LowerLOAD()
1480 if (!VT.isVector()) { in LowerLOAD()
1503 ISD::EXTLOAD, DL, VT, Chain, Ptr, LoadNode->getPointerInfo(), MemVT, in LowerLOAD()
1505 SDValue Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, NewLoad, in LowerLOAD()
1518 assert(VT == MVT::i32); in LowerLOAD()
1594 EVT VT = In.VT; in LowerFormalArguments() local
1596 if (!VT.isVector() && MemVT.isVector()) { in LowerFormalArguments()
1603 SDValue Register = DAG.getCopyFromReg(Chain, DL, Reg, VT); in LowerFormalArguments()
1608 PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()), in LowerFormalArguments()
1619 if (MemVT.getScalarSizeInBits() != VT.getScalarSizeInBits()) { in LowerFormalArguments()
1633 unsigned Alignment = MinAlign(VT.getStoreSize(), PartOffset); in LowerFormalArguments()
1637 ISD::UNINDEXED, Ext, VT, DL, Chain, in LowerFormalArguments()
1650 EVT VT) const { in getSetCCResultType()
1651 if (!VT.isVector()) in getSetCCResultType()
1653 return VT.changeVectorElementTypeToInteger(); in getSetCCResultType()
1665 bool R600TargetLowering::allowsMisalignedMemoryAccesses(EVT VT, in allowsMisalignedMemoryAccesses() argument
1672 if (!VT.isSimple() || VT == MVT::Other) in allowsMisalignedMemoryAccesses()
1675 if (VT.bitsLT(MVT::i32)) in allowsMisalignedMemoryAccesses()
1682 return VT.bitsGT(MVT::i32) && Align % 4 == 0; in allowsMisalignedMemoryAccesses()
1796 EVT VT = LoadNode->getValueType(0); in constBufferLoad() local
1823 if (VT.isVector()) { in constBufferLoad()
1824 NewVT = VT; in constBufferLoad()
1825 NumElements = VT.getVectorNumElements(); in constBufferLoad()
1828 if (!VT.isVector()) { in constBufferLoad()
1899 EVT VT = InVec.getValueType(); in PerformDAGCombine() local
1902 if (!isOperationLegal(ISD::BUILD_VECTOR, VT)) in PerformDAGCombine()
1918 unsigned NElts = VT.getVectorNumElements(); in PerformDAGCombine()
1937 return DAG.getBuildVector(VT, DL, Ops); in PerformDAGCombine()