Lines Matching refs:VT
183 bool isTypeLegal(Type *Ty, MVT &VT);
184 bool isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed = false);
188 bool simplifyAddress(Address &Addr, MVT VT);
228 unsigned emitLoad(MVT VT, MVT ResultVT, Address Addr, bool WantZExt = true,
230 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
232 bool emitStoreRelease(MVT VT, unsigned SrcReg, unsigned AddrReg,
239 unsigned emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill, int64_t Imm);
276 unsigned materializeInt(const ConstantInt *CI, MVT VT);
277 unsigned materializeFP(const ConstantFP *CFP, MVT VT);
331 static unsigned getImplicitScaleFactor(MVT VT) { in getImplicitScaleFactor() argument
332 switch (VT.SimpleTy) { in getImplicitScaleFactor()
381 unsigned AArch64FastISel::materializeInt(const ConstantInt *CI, MVT VT) { in materializeInt() argument
382 if (VT > MVT::i64) in materializeInt()
386 return fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); in materializeInt()
389 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass in materializeInt()
391 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in materializeInt()
398 unsigned AArch64FastISel::materializeFP(const ConstantFP *CFP, MVT VT) { in materializeFP() argument
404 if (VT != MVT::f32 && VT != MVT::f64) in materializeFP()
408 bool Is64Bit = (VT == MVT::f64); in materializeFP()
411 if (TLI.isFPImmLegal(Val, VT)) { in materializeFP()
416 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm); in materializeFP()
429 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP()
449 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP()
510 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant() local
513 return materializeInt(CI, VT); in fastMaterializeConstant()
515 return materializeFP(CFP, VT); in fastMaterializeConstant()
525 MVT VT; in fastMaterializeFloatZero() local
526 if (!isTypeLegal(CFP->getType(), VT)) in fastMaterializeFloatZero()
529 if (VT != MVT::f32 && VT != MVT::f64) in fastMaterializeFloatZero()
532 bool Is64Bit = (VT == MVT::f64); in fastMaterializeFloatZero()
535 return fastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg, /*IsKill=*/true); in fastMaterializeFloatZero()
950 bool AArch64FastISel::isTypeLegal(Type *Ty, MVT &VT) { in isTypeLegal() argument
956 VT = evt.getSimpleVT(); in isTypeLegal()
959 if (VT == MVT::f128) in isTypeLegal()
964 return TLI.isTypeLegal(VT); in isTypeLegal()
971 bool AArch64FastISel::isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed) { in isTypeSupported() argument
975 if (isTypeLegal(Ty, VT)) in isTypeSupported()
980 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16) in isTypeSupported()
994 bool AArch64FastISel::simplifyAddress(Address &Addr, MVT VT) { in simplifyAddress() argument
995 unsigned ScaleFactor = getImplicitScaleFactor(VT); in simplifyAddress()
1457 MVT VT = EVT.getSimpleVT(); in emitCmp() local
1459 switch (VT.SimpleTy) { in emitCmp()
1467 return emitICmp(VT, LHS, RHS, IsZExt); in emitCmp()
1470 return emitFCmp(VT, LHS, RHS); in emitCmp()
1532 unsigned AArch64FastISel::emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill, in emitAdd_ri_() argument
1536 ResultReg = emitAddSub_ri(false, VT, Op0, Op0IsKill, -Imm); in emitAdd_ri_()
1538 ResultReg = emitAddSub_ri(true, VT, Op0, Op0IsKill, Imm); in emitAdd_ri_()
1543 unsigned CReg = fastEmit_i(VT, VT, ISD::Constant, Imm); in emitAdd_ri_()
1547 ResultReg = emitAddSub_rr(true, VT, Op0, Op0IsKill, CReg, true); in emitAdd_ri_()
1649 MVT VT = std::max(MVT::i32, RetVT.SimpleTy); in emitLogicalOp() local
1650 ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, LHSIsKill, RHSReg, RHSIsKill); in emitLogicalOp()
1752 unsigned AArch64FastISel::emitLoad(MVT VT, MVT RetVT, Address Addr, in emitLoad() argument
1754 if (!TLI.allowsMisalignedMemoryAccesses(VT)) in emitLoad()
1758 if (!simplifyAddress(Addr, VT)) in emitLoad()
1761 unsigned ScaleFactor = getImplicitScaleFactor(VT); in emitLoad()
1829 switch (VT.SimpleTy) { in emitLoad()
1869 if (VT == MVT::i1) { in emitLoad()
1877 if (WantZExt && RetVT == MVT::i64 && VT <= MVT::i32) { in emitLoad()
1890 MVT VT; in selectAddSub() local
1891 if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true)) in selectAddSub()
1894 if (VT.isVector()) in selectAddSub()
1902 ResultReg = emitAdd(VT, I->getOperand(0), I->getOperand(1)); in selectAddSub()
1905 ResultReg = emitSub(VT, I->getOperand(0), I->getOperand(1)); in selectAddSub()
1916 MVT VT; in selectLogicalOp() local
1917 if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true)) in selectLogicalOp()
1920 if (VT.isVector()) in selectLogicalOp()
1928 ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1)); in selectLogicalOp()
1931 ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1)); in selectLogicalOp()
1934 ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1)); in selectLogicalOp()
1945 MVT VT; in selectLoad() local
1949 if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true) || in selectLoad()
1975 MVT RetVT = VT; in selectLoad()
1982 RetVT = VT; in selectLoad()
1987 RetVT = VT; in selectLoad()
1993 emitLoad(VT, RetVT, Addr, WantZExt, createMachineMemOperandFor(I)); in selectLoad()
2016 if (RetVT == MVT::i64 && VT <= MVT::i32) { in selectLoad()
2056 bool AArch64FastISel::emitStoreRelease(MVT VT, unsigned SrcReg, in emitStoreRelease() argument
2060 switch (VT.SimpleTy) { in emitStoreRelease()
2078 bool AArch64FastISel::emitStore(MVT VT, unsigned SrcReg, Address Addr, in emitStore() argument
2080 if (!TLI.allowsMisalignedMemoryAccesses(VT)) in emitStore()
2084 if (!simplifyAddress(Addr, VT)) in emitStore()
2087 unsigned ScaleFactor = getImplicitScaleFactor(VT); in emitStore()
2119 switch (VT.SimpleTy) { in emitStore()
2147 MVT VT; in selectStore() local
2152 if (!isTypeSupported(Op0->getType(), VT, /*IsVectorAllowed=*/true)) in selectStore()
2175 SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in selectStore()
2178 VT = MVT::getIntegerVT(VT.getSizeInBits()); in selectStore()
2179 SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in selectStore()
2198 return emitStoreRelease(VT, SrcReg, AddrReg, in selectStore()
2208 if (!emitStore(VT, SrcReg, Addr, createMachineMemOperandFor(I))) in selectStore()
2275 MVT VT; in emitCompareAndBranch() local
2276 if (!isTypeSupported(LHS->getType(), VT)) in emitCompareAndBranch()
2279 unsigned BW = VT.getSizeInBits(); in emitCompareAndBranch()
2321 if (VT == MVT::i1) in emitCompareAndBranch()
2372 SrcReg = emitIntExt(VT, SrcReg, MVT::i32, /*IsZExt=*/true); in emitCompareAndBranch()
2678 MVT VT; in selectSelect() local
2679 if (!isTypeSupported(I->getType(), VT)) in selectSelect()
2684 switch (VT.SimpleTy) { in selectSelect()
2953 MVT VT = ArgVT.getSimpleVT().SimpleTy; in fastLowerArguments() local
2954 if (VT.isFloatingPoint() && !Subtarget->hasFPARMv8()) in fastLowerArguments()
2957 if (VT.isVector() && in fastLowerArguments()
2961 if (VT >= MVT::i1 && VT <= MVT::i64) in fastLowerArguments()
2963 else if ((VT >= MVT::f16 && VT <= MVT::f64) || VT.is64BitVector() || in fastLowerArguments()
2964 VT.is128BitVector()) in fastLowerArguments()
2991 MVT VT = TLI.getSimpleValueType(DL, Arg.getType()); in fastLowerArguments() local
2994 if (VT >= MVT::i1 && VT <= MVT::i32) { in fastLowerArguments()
2997 VT = MVT::i32; in fastLowerArguments()
2998 } else if (VT == MVT::i64) { in fastLowerArguments()
3001 } else if (VT == MVT::f16) { in fastLowerArguments()
3004 } else if (VT == MVT::f32) { in fastLowerArguments()
3007 } else if ((VT == MVT::f64) || VT.is64BitVector()) { in fastLowerArguments()
3010 } else if (VT.is128BitVector()) { in fastLowerArguments()
3202 MVT VT; in fastLowerCall() local
3203 if (!isTypeLegal(Val->getType(), VT) && in fastLowerCall()
3204 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)) in fastLowerCall()
3208 if (VT.isVector() || VT.getSizeInBits() > 64) in fastLowerCall()
3211 OutVTs.push_back(VT); in fastLowerCall()
3300 MVT VT; in tryEmitSmallMemCpy() local
3303 VT = MVT::i64; in tryEmitSmallMemCpy()
3305 VT = MVT::i32; in tryEmitSmallMemCpy()
3307 VT = MVT::i16; in tryEmitSmallMemCpy()
3309 VT = MVT::i8; in tryEmitSmallMemCpy()
3314 VT = MVT::i32; in tryEmitSmallMemCpy()
3316 VT = MVT::i16; in tryEmitSmallMemCpy()
3318 VT = MVT::i8; in tryEmitSmallMemCpy()
3322 unsigned ResultReg = emitLoad(VT, VT, Src); in tryEmitSmallMemCpy()
3326 if (!emitStore(VT, ResultReg, Dest)) in tryEmitSmallMemCpy()
3329 int64_t Size = VT.getSizeInBits() / 8; in tryEmitSmallMemCpy()
3582 MVT VT; in fastLowerIntrinsicCall() local
3583 if (!isTypeLegal(II->getType(), VT)) in fastLowerIntrinsicCall()
3587 switch (VT.SimpleTy) { in fastLowerIntrinsicCall()
3601 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
3615 MVT VT; in fastLowerIntrinsicCall() local
3616 if (!isTypeLegal(RetTy, VT)) in fastLowerIntrinsicCall()
3624 unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg, Op0IsKill); in fastLowerIntrinsicCall()
3642 MVT VT; in fastLowerIntrinsicCall() local
3643 if (!isTypeLegal(RetTy, VT)) in fastLowerIntrinsicCall()
3646 if (VT != MVT::i32 && VT != MVT::i64) in fastLowerIntrinsicCall()
3682 ResultReg1 = emitAdd(VT, LHS, RHS, /*SetFlags=*/true); in fastLowerIntrinsicCall()
3686 ResultReg1 = emitAdd(VT, LHS, RHS, /*SetFlags=*/true); in fastLowerIntrinsicCall()
3690 ResultReg1 = emitSub(VT, LHS, RHS, /*SetFlags=*/true); in fastLowerIntrinsicCall()
3694 ResultReg1 = emitSub(VT, LHS, RHS, /*SetFlags=*/true); in fastLowerIntrinsicCall()
3709 if (VT == MVT::i32) { in fastLowerIntrinsicCall()
3713 MulReg = fastEmitInst_extractsubreg(VT, MulReg, /*IsKill=*/true, in fastLowerIntrinsicCall()
3715 ShiftReg = fastEmitInst_extractsubreg(VT, ShiftReg, /*IsKill=*/true, in fastLowerIntrinsicCall()
3717 emitSubs_rs(VT, ShiftReg, /*IsKill=*/true, MulReg, /*IsKill=*/false, in fastLowerIntrinsicCall()
3720 assert(VT == MVT::i64 && "Unexpected value type."); in fastLowerIntrinsicCall()
3723 MulReg = emitMul_rr(VT, LHSReg, /*IsKill=*/false, RHSReg, in fastLowerIntrinsicCall()
3725 unsigned SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, LHSIsKill, in fastLowerIntrinsicCall()
3727 emitSubs_rs(VT, SMULHReg, /*IsKill=*/true, MulReg, /*IsKill=*/false, in fastLowerIntrinsicCall()
3744 if (VT == MVT::i32) { in fastLowerIntrinsicCall()
3749 MulReg = fastEmitInst_extractsubreg(VT, MulReg, /*IsKill=*/true, in fastLowerIntrinsicCall()
3752 assert(VT == MVT::i64 && "Unexpected value type."); in fastLowerIntrinsicCall()
3755 MulReg = emitMul_rr(VT, LHSReg, /*IsKill=*/false, RHSReg, in fastLowerIntrinsicCall()
3757 unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, LHSIsKill, in fastLowerIntrinsicCall()
3759 emitSubs_rr(VT, AArch64::XZR, /*IsKill=*/true, UMULHReg, in fastLowerIntrinsicCall()
3767 ResultReg1 = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
4628 MVT VT; in selectMul() local
4629 if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true)) in selectMul()
4632 if (VT.isVector()) in selectMul()
4645 MVT SrcVT = VT; in selectMul()
4649 MVT VT; in selectMul() local
4650 if (isValueAvailable(ZExt) && isTypeSupported(ZExt->getSrcTy(), VT)) { in selectMul()
4651 SrcVT = VT; in selectMul()
4658 MVT VT; in selectMul() local
4659 if (isValueAvailable(SExt) && isTypeSupported(SExt->getSrcTy(), VT)) { in selectMul()
4660 SrcVT = VT; in selectMul()
4673 emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt); in selectMul()
4691 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill); in selectMul()
4869 MVT VT; in selectSDiv() local
4870 if (!isTypeLegal(I->getType(), VT)) in selectSDiv()
4877 if ((VT != MVT::i32 && VT != MVT::i64) || !C || in selectSDiv()
4888 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Src0IsKill, Lg2); in selectSDiv()
4896 unsigned AddReg = emitAdd_ri_(VT, Src0Reg, /*IsKill=*/false, Pow2MinusOne); in selectSDiv()
4901 if (!emitICmp_ri(VT, Src0Reg, /*IsKill=*/false, 0)) in selectSDiv()
4906 if (VT == MVT::i64) { in selectSDiv()
4921 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in selectSDiv()
4924 ResultReg = emitAddSub_rs(/*UseAdd=*/false, VT, ZeroReg, /*IsKill=*/true, in selectSDiv()
4927 ResultReg = emitASR_ri(VT, VT, SelectReg, /*IsKill=*/true, Lg2); in selectSDiv()
4971 MVT VT = TLI.getPointerTy(DL); in selectGetElementPtr() local
4993 N = emitAdd_ri_(VT, N, NIsKill, TotalOffs); in selectGetElementPtr()
5009 unsigned C = fastEmit_i(VT, VT, ISD::Constant, ElementSize); in selectGetElementPtr()
5012 IdxN = emitMul_rr(VT, IdxN, IdxNIsKill, C, true); in selectGetElementPtr()
5017 N = fastEmit_rr(VT, VT, ISD::ADD, N, NIsKill, IdxN, IdxNIsKill); in selectGetElementPtr()
5023 N = emitAdd_ri_(VT, N, NIsKill, TotalOffs); in selectGetElementPtr()
5040 MVT VT; in selectAtomicCmpXchg() local
5041 if (!isTypeLegal(RetTy, VT)) in selectAtomicCmpXchg()
5048 if (VT == MVT::i32) { in selectAtomicCmpXchg()
5052 } else if (VT == MVT::i64) { in selectAtomicCmpXchg()
5082 .addDef(VT == MVT::i32 ? AArch64::WZR : AArch64::XZR) in selectAtomicCmpXchg()