Lines Matching refs:VT
406 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) { in getSYNC() argument
409 switch (VT.SimpleTy) { \ in getSYNC()
587 for (MVT VT : MVT::all_valuetypes()) { in initActions() local
591 setIndexedLoadAction(IM, VT, Expand); in initActions()
592 setIndexedStoreAction(IM, VT, Expand); in initActions()
596 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand); in initActions()
599 setOperationAction(ISD::FGETSIGN, VT, Expand); in initActions()
600 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand); in initActions()
601 setOperationAction(ISD::FMINNUM, VT, Expand); in initActions()
602 setOperationAction(ISD::FMAXNUM, VT, Expand); in initActions()
603 setOperationAction(ISD::FMINNUM_IEEE, VT, Expand); in initActions()
604 setOperationAction(ISD::FMAXNUM_IEEE, VT, Expand); in initActions()
605 setOperationAction(ISD::FMINIMUM, VT, Expand); in initActions()
606 setOperationAction(ISD::FMAXIMUM, VT, Expand); in initActions()
607 setOperationAction(ISD::FMAD, VT, Expand); in initActions()
608 setOperationAction(ISD::SMIN, VT, Expand); in initActions()
609 setOperationAction(ISD::SMAX, VT, Expand); in initActions()
610 setOperationAction(ISD::UMIN, VT, Expand); in initActions()
611 setOperationAction(ISD::UMAX, VT, Expand); in initActions()
612 setOperationAction(ISD::ABS, VT, Expand); in initActions()
613 setOperationAction(ISD::FSHL, VT, Expand); in initActions()
614 setOperationAction(ISD::FSHR, VT, Expand); in initActions()
615 setOperationAction(ISD::SADDSAT, VT, Expand); in initActions()
616 setOperationAction(ISD::UADDSAT, VT, Expand); in initActions()
617 setOperationAction(ISD::SSUBSAT, VT, Expand); in initActions()
618 setOperationAction(ISD::USUBSAT, VT, Expand); in initActions()
619 setOperationAction(ISD::SMULFIX, VT, Expand); in initActions()
622 setOperationAction(ISD::SADDO, VT, Expand); in initActions()
623 setOperationAction(ISD::SSUBO, VT, Expand); in initActions()
624 setOperationAction(ISD::UADDO, VT, Expand); in initActions()
625 setOperationAction(ISD::USUBO, VT, Expand); in initActions()
626 setOperationAction(ISD::SMULO, VT, Expand); in initActions()
627 setOperationAction(ISD::UMULO, VT, Expand); in initActions()
630 setOperationAction(ISD::ADDCARRY, VT, Expand); in initActions()
631 setOperationAction(ISD::SUBCARRY, VT, Expand); in initActions()
632 setOperationAction(ISD::SETCCCARRY, VT, Expand); in initActions()
635 setOperationAction(ISD::ADDC, VT, Expand); in initActions()
636 setOperationAction(ISD::ADDE, VT, Expand); in initActions()
637 setOperationAction(ISD::SUBC, VT, Expand); in initActions()
638 setOperationAction(ISD::SUBE, VT, Expand); in initActions()
641 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand); in initActions()
642 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand); in initActions()
644 setOperationAction(ISD::BITREVERSE, VT, Expand); in initActions()
647 setOperationAction(ISD::FROUND, VT, Expand); in initActions()
648 setOperationAction(ISD::FPOWI, VT, Expand); in initActions()
651 if (VT.isVector()) { in initActions()
652 setOperationAction(ISD::FCOPYSIGN, VT, Expand); in initActions()
653 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand); in initActions()
654 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand); in initActions()
655 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand); in initActions()
659 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand); in initActions()
678 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) { in initActions()
679 setOperationAction(ISD::FCBRT, VT, Expand); in initActions()
680 setOperationAction(ISD::FLOG , VT, Expand); in initActions()
681 setOperationAction(ISD::FLOG2, VT, Expand); in initActions()
682 setOperationAction(ISD::FLOG10, VT, Expand); in initActions()
683 setOperationAction(ISD::FEXP , VT, Expand); in initActions()
684 setOperationAction(ISD::FEXP2, VT, Expand); in initActions()
685 setOperationAction(ISD::FFLOOR, VT, Expand); in initActions()
686 setOperationAction(ISD::FNEARBYINT, VT, Expand); in initActions()
687 setOperationAction(ISD::FCEIL, VT, Expand); in initActions()
688 setOperationAction(ISD::FRINT, VT, Expand); in initActions()
689 setOperationAction(ISD::FTRUNC, VT, Expand); in initActions()
690 setOperationAction(ISD::FROUND, VT, Expand); in initActions()
715 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const { in canOpTrap()
716 assert(isTypeLegal(VT)); in canOpTrap()
735 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const { in getTypeConversion()
737 if (VT.isSimple()) { in getTypeConversion()
738 MVT SVT = VT.getSimpleVT(); in getTypeConversion()
757 if (!VT.isVector()) { in getTypeConversion()
758 assert(VT.isInteger() && "Float types must be simple"); in getTypeConversion()
759 unsigned BitSize = VT.getSizeInBits(); in getTypeConversion()
762 EVT NVT = VT.getRoundIntegerType(Context); in getTypeConversion()
763 assert(NVT != VT && "Unable to round integer VT"); in getTypeConversion()
773 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2)); in getTypeConversion()
777 unsigned NumElts = VT.getVectorNumElements(); in getTypeConversion()
778 EVT EltVT = VT.getVectorElementType(); in getTypeConversion()
790 if (!VT.isPow2VectorType()) { in getTypeConversion()
857 if (!VT.isPow2VectorType()) { in getTypeConversion()
858 EVT NVT = VT.getPow2VectorType(Context); in getTypeConversion()
863 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2); in getTypeConversion()
867 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, in getVectorTypeBreakdownMVT() argument
872 unsigned NumElts = VT.getVectorNumElements(); in getVectorTypeBreakdownMVT()
873 MVT EltTy = VT.getVectorElementType(); in getVectorTypeBreakdownMVT()
1045 MVT VT) const { in findRepresentativeClass()
1046 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; in findRepresentativeClass()
1170 MVT VT = (MVT::SimpleValueType) i; in computeRegisterProperties() local
1171 if (isTypeLegal(VT)) in computeRegisterProperties()
1174 MVT EltVT = VT.getVectorElementType(); in computeRegisterProperties()
1175 unsigned NElts = VT.getVectorNumElements(); in computeRegisterProperties()
1177 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT); in computeRegisterProperties()
1191 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); in computeRegisterProperties()
1209 ValueTypeActions.setTypeAction(VT, TypeWidenVector); in computeRegisterProperties()
1223 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT, in computeRegisterProperties()
1227 MVT NVT = VT.getPow2VectorType(); in computeRegisterProperties()
1228 if (NVT == VT) { in computeRegisterProperties()
1232 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector); in computeRegisterProperties()
1234 ValueTypeActions.setTypeAction(VT, TypeSplitVector); in computeRegisterProperties()
1237 ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector in computeRegisterProperties()
1241 ValueTypeActions.setTypeAction(VT, TypeWidenVector); in computeRegisterProperties()
1265 EVT VT) const { in getSetCCResultType()
1266 assert(!VT.isVector() && "No default SetCC type for vectors!"); in getSetCCResultType()
1282 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, in getVectorTypeBreakdown() argument
1286 unsigned NumElts = VT.getVectorNumElements(); in getVectorTypeBreakdown()
1293 LegalizeTypeAction TA = getTypeAction(Context, VT); in getVectorTypeBreakdown()
1295 EVT RegisterEVT = getTypeToTransformTo(Context, VT); in getVectorTypeBreakdown()
1305 EVT EltTy = VT.getVectorElementType(); in getVectorTypeBreakdown()
1361 EVT VT = ValueVTs[j]; in GetReturnInfo() local
1373 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { in GetReturnInfo()
1375 if (VT.bitsLT(MinVT)) in GetReturnInfo()
1376 VT = MinVT; in GetReturnInfo()
1380 TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT); in GetReturnInfo()
1382 TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT); in GetReturnInfo()
1396 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0)); in GetReturnInfo()
1409 const DataLayout &DL, EVT VT, in allowsMemoryAccess() argument
1418 Type *Ty = VT.getTypeForEVT(Context); in allowsMemoryAccess()
1427 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Fast); in allowsMemoryAccess()
1698 static std::string getReciprocalOpName(bool IsSqrt, EVT VT) { in getReciprocalOpName() argument
1699 std::string Name = VT.isVector() ? "vec-" : ""; in getReciprocalOpName()
1704 if (VT.getScalarType() == MVT::f64) { in getReciprocalOpName()
1707 assert(VT.getScalarType() == MVT::f32 && in getReciprocalOpName()
1741 static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) { in getOpEnabled() argument
1774 std::string VTName = getReciprocalOpName(IsSqrt, VT); in getOpEnabled()
1801 static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) { in getOpRefinementSteps() argument
1829 std::string VTName = getReciprocalOpName(IsSqrt, VT); in getOpRefinementSteps()
1847 int TargetLoweringBase::getRecipEstimateSqrtEnabled(EVT VT, in getRecipEstimateSqrtEnabled() argument
1849 return getOpEnabled(true, VT, getRecipEstimateForFunc(MF)); in getRecipEstimateSqrtEnabled()
1852 int TargetLoweringBase::getRecipEstimateDivEnabled(EVT VT, in getRecipEstimateDivEnabled() argument
1854 return getOpEnabled(false, VT, getRecipEstimateForFunc(MF)); in getRecipEstimateDivEnabled()
1857 int TargetLoweringBase::getSqrtRefinementSteps(EVT VT, in getSqrtRefinementSteps() argument
1859 return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF)); in getSqrtRefinementSteps()
1862 int TargetLoweringBase::getDivRefinementSteps(EVT VT, in getDivRefinementSteps() argument
1864 return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF)); in getDivRefinementSteps()