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Searched refs:isReg (Results 1 – 25 of 445) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsInstPrinter.cpp129 if (Op.isReg()) { in printOperand()
274 return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) && in printAlias()
276 (isReg<Mips::ZERO>(MI, 1) && in printAlias()
285 return isReg<Mips::ZERO>(MI, 1) && in printAlias()
293 return isReg<Mips::ZERO>(MI, 0) && in printAlias()
297 return isReg<Mips::FCC0>(MI, 0) && in printAlias()
301 return isReg<Mips::FCC0>(MI, 0) && in printAlias()
308 (isReg<Mips::RA>(MI, 0) && in printAlias()
321 return isReg<Mips::ZERO>(MI, 2) && in printAlias()
331 return isReg<Mips::ZERO>(MI, 2) && in printAlias()
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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DMachineOperand.h221 return isReg() ? 0 : SubReg_TargetFlags; in getTargetFlags()
320 bool isReg() const { return OpKind == MO_Register; } in isReg() function
365 assert(isReg() && "Wrong MachineOperand accessor"); in getSubReg()
370 assert(isReg() && "Wrong MachineOperand accessor"); in isUse()
375 assert(isReg() && "Wrong MachineOperand accessor"); in isDef()
380 assert(isReg() && "Wrong MachineOperand accessor"); in isImplicit()
465 if ((isReg() && isImplicit()) || isRegMask()) in isValidExcessOperand()
481 assert(isReg() && "Wrong MachineOperand mutator"); in setSubReg()
505 assert(isReg() && "Wrong MachineOperand mutator");
521 assert(isReg() && "Wrong MachineOperand mutator");
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIOptimizeExecMasking.cpp101 if (Src.isReg() && Src.getReg() == Exec) in isCopyFromExec()
116 if (Dst.isReg() && Dst.getReg() == Exec && MI.getOperand(1).isReg()) in isCopyToExec()
213 bool RegSrc = MI.getOperand(1).isReg(); in removeTerminatorBit()
600 if (Src0->isReg()) in optimizeVCMPSaveExecSequence()
602 if (Src1->isReg()) in optimizeVCMPSaveExecSequence()
634 if (!SaveExecSrc0->isReg()) in tryRecordVCmpxAndSaveexecSequence()
689 if (Src0->isReg()) in tryRecordVCmpxAndSaveexecSequence()
692 if (Src1->isReg()) in tryRecordVCmpxAndSaveexecSequence()
717 if (XorDst.isReg() && XorDst.getReg() == Exec && XorSrc0.isReg() && in tryRecordOrSaveexecXorSequence()
718 XorSrc1.isReg() && in tryRecordOrSaveexecXorSequence()
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H A DSIShrinkInstructions.cpp95 if (Src0.isReg()) { in foldImmediates()
190 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask()) in copyExtraImplicitOps()
198 if (!MI.getOperand(0).isReg()) in shrinkScalarCompare()
203 if (!Src0.isReg()) in shrinkScalarCompare()
481 if (Dest->getReg().isVirtual() && SrcReg->isReg()) { in shrinkScalarLogicOp()
514 if (!MO.isReg()) in instAccessReg()
596 if (!Xop.isReg()) in matchSwap()
621 !MovY->getOperand(1).isReg() || in matchSwap()
784 if (!Src0->isReg() && Src1->isReg()) { in runOnMachineFunction()
881 if (Op0.isReg()) { in runOnMachineFunction()
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H A DSIFoldOperands.cpp59 bool isReg() const { in isReg() function
184 assert(Old.isReg()); in updateOperand()
410 if (!OtherOp.isReg() || in tryAddToFoldList()
494 assert(Sub->isReg()); in getRegSeqInit()
540 if (!OpToFold.isReg()) in tryToFoldACImm()
603 if (UseOp.isReg() && OpToFold.isReg()) { in foldOperand()
1036 if (Op.isReg()) { in getImmOrMaterializedImm()
1274 if (Fold.isReg()) { in foldInstOperand()
1307 if (!Src0->isReg() || !Src1->isReg() || in isClamp()
1462 if (Src0->isReg() && Src1->isReg() && Src0->getReg() == Src1->getReg() && in isOMod()
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H A DSIPeepholeSDWA.cpp89 assert(Target->isReg()); in SDWAOperand()
90 assert(Replaced->isReg()); in SDWAOperand()
246 assert(To.isReg() && From.isReg()); in copyRegOperand()
258 return LHS.isReg() && in isSameReg()
259 RHS.isReg() && in isSameReg()
288 if (!Reg->isReg()) in findSingleRegDef()
446 Operand->isReg() && in convertToSDWA()
468 if (!MO.isReg()) in convertToSDWA()
499 if (Op.isReg()) { in foldToImm()
697 if (!Op1 || !Op1->isReg() || !Op2 || !Op2->isReg()) in matchSDWAOperand()
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/llvm-project-15.0.7/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCCodeEmitter.cpp47 if (MO.isReg() || MO.isImm()) in getDirectBrEncoding()
125 assert(!MO.isReg() && "Not expecting a register for this operand."); in getImm34Encoding()
155 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIEncoding()
173 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIXEncoding()
191 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIX16Encoding()
216 assert(RegMO.isReg() && "Base address must be a register."); in getMemRIHashEncoding()
334 assert(MI.getOperand(OpNo+1).isReg()); in getSPE8DisEncoding()
349 assert(MI.getOperand(OpNo+1).isReg()); in getSPE4DisEncoding()
364 assert(MI.getOperand(OpNo+1).isReg()); in getSPE2DisEncoding()
377 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI); in getTLSRegEncoding()
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/llvm-project-15.0.7/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiMCCodeEmitter.cpp112 if (MCOp.isReg()) in getMachineOpValue()
146 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr()))) in adjustPqBits()
150 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && in adjustPqBits()
154 (Op2.isReg() && Op2.getReg() != Lanai::R0))) in adjustPqBits()
193 assert(Op1.isReg() && "First operand is not register."); in getRiMemoryOpValue()
225 assert(Op1.isReg() && "First operand is not register."); in getRrMemoryOpValue()
227 assert(Op2.isReg() && "Second operand is not register."); in getRrMemoryOpValue()
264 assert(Op1.isReg() && "First operand is not register."); in getSplsOpValue()
292 if (MCOp.isReg() || MCOp.isImm()) in getBranchTargetOpValue()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCMacroFusion.cpp73 if (!Op1.isReg() || !Op2.isReg()) in matchingRegOps()
105 if (!RA.isReg()) in checkOpConstraints()
114 if (!RT.isReg()) in checkOpConstraints()
171 if (!BT.isReg() || in checkOpConstraints()
183 if (!BT.isReg() || in checkOpConstraints()
208 if (!SI.isImm() || !RA.isReg()) in checkOpConstraints()
219 if (!SI.isImm() || !RA.isReg()) in checkOpConstraints()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineInstr.cpp151 if (MO.isReg()) in removeRegOperandsFromUseLists()
157 if (MO.isReg()) in addRegOperandsToUseLists()
248 if (NewMO->isReg()) { in addOperand()
283 if (Operands[i].isReg()) in removeOperand()
598 if (!MO.isReg()) { in isIdenticalTo()
844 if (!getOperand(OpIdx).isReg()) in getRegClassConstraint()
906 assert(MO.isReg() && in getRegClassConstraintEffect()
1462 if (!Op.isReg()) in getTypeToPrint()
2074 if (MO.isReg()) in BuildMI()
2099 if (MO.isReg()) in BuildMI()
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H A DMIRCanonicalizerPass.cpp155 if (!MO.isReg()) in rescheduleCanonically()
175 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg())) in rescheduleCanonically()
187 if (II->getOperand(i).isReg()) { in rescheduleCanonically()
302 if (!MI->getOperand(0).isReg()) in propagateLocalCopies()
304 if (!MI->getOperand(1).isReg()) in propagateLocalCopies()
342 if (!MO.isReg()) in doDefKillClear()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiDelaySlotFiller.cpp107 assert(RI->getOpcode() == Lanai::LDW_RI && RI->getOperand(0).isReg() && in runOnMachineBasicBlock()
109 RI->getOperand(1).isReg() && in runOnMachineBasicBlock()
114 RI->getOperand(0).isReg() && in runOnMachineBasicBlock()
116 RI->getOperand(1).isReg() && in runOnMachineBasicBlock()
205 if (!MO.isReg() || !(Reg = MO.getReg())) in delayHasHazard()
234 if (!MO.isReg() || !(Reg = MO.getReg())) in insertDefsUses()
H A DLanaiMemAluCombiner.cpp185 return ((Op.isReg() && Op.getReg() == Lanai::R0) || in isZeroOperand()
247 assert((AluOffset.isReg() || AluOffset.isImm()) && in insertMergedInstruction()
264 if (AluOffset.isReg()) in insertMergedInstruction()
307 if (Offset.isReg() && Offset.getReg() == Lanai::R0) in isSuitableAluInstr()
318 } else if (Op2.isReg()) { in isSuitableAluInstr()
320 if (Offset.isReg() && Op2.getReg() == Offset.getReg()) in isSuitableAluInstr()
356 if (Offset->isReg() && InstrUsesReg(First, Offset)) in findClosestSuitableAluInstr()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp677 if (Op1.isReg()) { in getLoopTripCount()
707 if (EndValue->isReg()) { in getLoopTripCount()
737 if (Start->isReg()) { in computeCount()
743 if (End->isReg()) { in computeCount()
851 bool RegToReg = Start->isReg() && End->isReg(); // for (reg..reg) in computeCount()
888 if (Start->isReg()) { in computeCount()
1205 if (TripCount->isReg()) { in convertToHardwareLoop()
1413 if (!InitVal->isReg()) in loopCountMayWrapOrUnderFlow()
1497 if (!MO.isReg()) in checkForImmediate()
1578 assert(MO.isReg()); in setImmediate()
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H A DHexagonExpandCondsets.cpp584 if (SO.isReg()) { in getCondTfrOpcode()
643 if (SrcOp.isReg()) { in genCondTfrFor()
682 if (Op.isReg()) in split()
691 if (ST.isReg() && SF.isReg()) { in split()
801 if (!Op.isReg()) in canMoveOver()
902 if (Op.isReg()) in predicateAt()
994 if (!Op.isReg()) in predicate()
1082 if (Op.isReg()) in predicateInBlock()
1193 if (!S1.isReg() && !S2.isReg()) in coalesceSegments()
1222 if (S1.isReg()) { in coalesceSegments()
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H A DHexagonVLIWPacketizer.cpp152 if (!MO.isReg() || !MO.isDef()) in hasWriteToReadDep()
436 if (MO.isReg() && MO.getReg() == DestReg) in canPromoteToDotCur()
584 if (MO.isReg() && MO.isDef()) in getPostIncrementOperand()
658 if (Val.isReg() && Val.getReg() != DepReg) in canPromoteToNewValueStore()
711 if (!MO.isReg()) in canPromoteToNewValueStore()
723 if (!MO.isReg()) in canPromoteToNewValueStore()
785 if (MO.isReg() && MO.getReg() == DepReg) in canPromoteToNewValueStore()
955 if (Op.isReg() && Op.getReg() && Op.isUse() && in getPredicatedRegister()
1218 if (!MO.isReg() || !MO.isDef() || !MO.isDead()) in hasDeadDependence()
1287 if (OpI.isReg()) { in hasRegMaskDependence()
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H A DHexagonNewValueJump.cpp151 if (!Op.isReg() || !Op.isDef()) in INITIALIZE_PASS_DEPENDENCY()
176 if (II->getOperand(i).isReg() && in INITIALIZE_PASS_DEPENDENCY()
561 if (foundJump && !foundCompare && MI.getOperand(0).isReg() && in runOnMachineFunction()
568 isSecondOpReg = MI.getOperand(2).isReg(); in runOnMachineFunction()
597 if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef() && in runOnMachineFunction()
648 if (!MO.isReg() || !MO.isUse()) in runOnMachineFunction()
655 if (!Op.isReg() || !Op.isUse() || !Op.isKill()) in runOnMachineFunction()
701 if (cmpInstr->getOperand(0).isReg() && in runOnMachineFunction()
704 if (cmpInstr->getOperand(1).isReg() && in runOnMachineFunction()
H A DHexagonSplitDouble.cpp179 if (MI->getOperand(1).isReg()) in isFixedInstr()
184 if (MI->getOperand(0).isReg()) in isFixedInstr()
211 if (!Op.isReg()) in isFixedInstr()
596 if (!Op.isReg()) { in createHalfInstr()
728 assert(Op0.isReg()); in splitCombine()
736 if (!Op1.isReg()) { in splitCombine()
744 if (!Op2.isReg()) { in splitCombine()
757 assert(Op0.isReg() && Op1.isReg()); in splitExt()
780 assert(Op0.isReg() && Op1.isReg() && Op2.isImm()); in splitShift()
905 assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm()); in splitAslOr()
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H A DHexagonGenMux.cpp172 if (!MO.isReg() || MO.isImplicit()) in getDefsUses()
209 bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg(); in getMuxOpcode()
302 Register SR1 = Src1->isReg() ? Src1->getReg() : Register(); in genMuxInBlock()
303 Register SR2 = Src2->isReg() ? Src2->getReg() : Register(); in genMuxInBlock()
367 if (!Op.isReg() || !Op.isUse()) in genMuxInBlock()
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizer.cpp77 assert(MI.getOperand(2).isReg() && "Reg operand is expected"); in addConstantsToTrack()
105 while (MI.getOperand(NumOp).isReg()) { in foldConstantsIntoIntrinsics()
128 assert(MI.getOperand(2).isReg()); in insertBitcasts()
151 if (MI->getOperand(0).isReg()) { in propagateSPIRVType()
173 MachineInstr *Def = Op.isReg() ? MRI.getVRegDef(Op.getReg()) : nullptr; in propagateSPIRVType()
338 if (!Op.isReg() || Op.isDef()) in processInstr()
406 assert(MI.getOperand(1).isReg()); in processSwitches()
415 assert(MI.getOperand(0).isReg() && MI.getOperand(1).isPredicate() && in processSwitches()
416 MI.getOperand(3).isReg()); in processSwitches()
444 (NextMBB->front().getOperand(2).isReg() && in processSwitches()
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/llvm-project-15.0.7/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcInstPrinter.cpp64 if (!MI->getOperand(0).isReg()) in printSparcAliasInstr()
88 || (!MI->getOperand(0).isReg()) in printSparcAliasInstr()
114 if (MO.isReg()) { in printOperand()
156 if (Op1.isReg() && Op1.getReg() != SP::G0) { in printMemOperand()
164 PrintedFirstOperand && ((Op2.isReg() && Op2.getReg() == SP::G0) || in printMemOperand()
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXProxyRegErasure.cpp99 assert(InOp.isReg() && "ProxyReg input operand should be a register."); in replaceMachineInstructionUsage()
100 assert(OutOp.isReg() && "ProxyReg output operand should be a register."); in replaceMachineInstructionUsage()
113 if (Op.isReg() && Op.getReg() == From.getReg()) { in replaceRegisterUsage()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyDebugFixup.cpp82 if (MO.isReg() && MO.getReg().isValid() && in runOnMachineFunction()
109 if (MO.isReg() && MFI.isVRegStackified(MO.getReg())) { in runOnMachineFunction()
130 if (MO.isReg() && MFI.isVRegStackified(MO.getReg())) { in runOnMachineFunction()
/llvm-project-15.0.7/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRMCCodeEmitter.cpp71 assert(MI.getOperand(0).isReg() && MI.getOperand(1).isReg() && in loadStorePostEncoder()
119 assert(MO.isReg()); in encodeLDSTPtrReg()
143 assert(RegOp.isReg() && "Expected register operand"); in encodeMemri()
258 if (MO.isReg()) in getMachineOpValue()
/llvm-project-15.0.7/llvm/lib/Target/M68k/AsmParser/
H A DM68kAsmParser.cpp158 bool isReg() const override;
300 bool M68kOperand::isReg() const { in isReg() function in M68kOperand
305 assert(isReg()); in getReg()
310 assert(isReg() && "wrong operand kind"); in addRegOperands()
522 if (Operand.isReg() && in validateTargetOperandClass()
530 if (Operand.isReg() && in validateTargetOperandClass()
537 if (Operand.isReg() && in validateTargetOperandClass()
546 if (Operand.isReg() && in validateTargetOperandClass()
553 if (Operand.isReg() && in validateTargetOperandClass()
560 if (Operand.isReg() && in validateTargetOperandClass()
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